TW202015197A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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TW202015197A
TW202015197A TW108122395A TW108122395A TW202015197A TW 202015197 A TW202015197 A TW 202015197A TW 108122395 A TW108122395 A TW 108122395A TW 108122395 A TW108122395 A TW 108122395A TW 202015197 A TW202015197 A TW 202015197A
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Taiwan
Prior art keywords
semiconductor die
semiconductor
thermally conductive
conductive layer
item
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TW108122395A
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English (en)
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TWI712121B (zh
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林俊成
盧思維
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供半導體封裝。所述半導體封裝中的一種包括半導體晶粒、導熱圖案、包封體及導熱層。所述導熱圖案設置於所述半導體晶粒旁邊。所述包封體包封所述半導體晶粒及所述導熱圖案。所述導熱層覆蓋所述半導體晶粒的背表面，其中所述導熱圖案藉由所述導熱層而熱耦合至所述半導體晶粒且與所述半導體晶粒電性絕緣。

Description

半導體封裝
在積體電路的封裝中，可藉由模塑化合物來封裝半導體晶粒且半導體晶粒可結合至例如中介層（interposer）及封裝基底等的其他封裝組件。熱量耗散是半導體封裝中的挑戰。在有效地耗散半導體封裝內部晶粒所產生的熱量方面存在瓶頸。
以下揭露內容提供用於實作所提供標的的不同特徵的諸多不同的實施例或實例。以下闡述組件及構造的具體實例以簡化本揭露內容。當然，該些僅為實例而不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可使用例如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（些）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外，亦涵蓋裝置在使用或操作中的不同定向。設備可被另外定向（旋轉90度或處於其他定向），且本文所用的空間相對性描述語可同樣相應地作出解釋。
另外，為易於說明，本文中可使用例如「第一」、「第二」、「第三」、「第四」等用語來闡述圖中所示的相似或不同的元件或特徵，且所述用語可依據存在次序或說明上下文而可互換地加以使用。
本發明亦可包括其他特徵及製程。例如，可包括測試結構，以幫助對三維（3D）封裝或三維積體電路（3DIC）裝置進行驗證測試。測試結構可例如包括測試接墊，所述測試接墊在重佈線路結構中形成、或者在容許對3D封裝或3DIC進行測試、容許使用探針及/或探針卡等的基底上形成。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可與併入有對已知良好晶粒進行中間驗證的測試方法一起使用，以提高良率並降低成本。
圖1是示出根據一些實施例形成半導體封裝的方法的製程步驟的示例性流程圖。圖2A至圖2I是根據一些實施例形成半導體封裝的方法的剖視圖。圖3是圖2I的簡化俯視圖。為使說明簡單及清晰起見，圖3的簡化俯視圖中僅示出幾個元件，例如半導體晶粒、穿孔、導熱圖案及導熱層。
參照圖1及圖2A，在步驟S10中，提供上面塗佈有緩衝層104的載板102。在一些實施例中，載板102可為玻璃載板或任何適用於為半導體封裝的製造方法承載半導體晶圓或重構晶圓（reconstituted wafer）的載板。在一些實施例中，緩衝層104包括剝離層（debond layer），且所述剝離層的材料可為任何適用於將載板102與設置於載板102上的上方層或晶圓結合及剝離的材料。在一些實施例中，緩衝層104例如包括光/熱轉換（light-to-heat conversion，「LTHC」）層，且此種層允許藉由施加雷射輻照而自載板進行剝離。在一些實施例中，緩衝層104可更包括介於剝離層與載板102之間的介電層，且所述介電層由包括苯環丁烷（benzocyclobutene，「BCB」）、聚苯並噁唑（polybenzooxazole，「PBO」）、或任何其他適合的聚合物系介電材料在內的介電材料製成。
在步驟S20中，在緩衝層104之上形成穿孔106a、106b及導熱圖案108。在一些實施例中，例如，在緩衝層104上形成多個穿孔106a、106b以環繞半導體晶粒的區域。在一些實施例中，如圖3中所示，穿孔106a、106b可沿環繞半導體晶粒的區域的至少一個環形路徑排列。在一些實施例中，例如，由穿孔106a形成的第一群組沿第一環形路徑排列，且由穿孔106b形成的第二群組沿環繞第一環形路徑的第二環形路徑排列。換言之，穿孔106a設置於穿孔106b與半導體晶粒的區域之間。在一些實施例中，同一群組的穿孔106a、106b可規則地排列，亦即，同一群組的相鄰的穿孔106a、106b之間的距離是恆定的。在一些替代實施例中，同一群組的穿孔106a、106b可不規則地或隨機地排列，亦即，同一群組的穿孔106a、106b之間的距離不是恆定的。在一些替代實施例中，穿孔可沿一個環形路徑或多於二個環形路徑排列。在一些替代實施例中，當穿孔沿多於二個環形路徑排列時，相鄰的由穿孔形成的群組之間的距離可為恆定的。
在一些實施例中，穿孔106a、106b的材料包括銅（Cu）、鋁（Al）、鋁銅合金（AlCu）、金、鈦、鈷、其合金、或任何適合的導電材料。可例如藉由電化學鍍覆（electrochemical plating，ECP）、電鍍、無電鍍覆或任何其他適合的製程來形成穿孔106a、106b。
在一些實施例中，導熱圖案108在緩衝層104上設置於穿孔106a、106b與半導體晶粒的區域之間。在一些實施例中，例如，導熱圖案108包括多個離散穿孔108a。在一些實施例中，例如，穿孔108a沿環繞半導體晶粒的區域的一個環形路徑P1排列。在一些實施例中，穿孔108a可規則地排列，亦即，相鄰的穿孔108a之間的距離是恆定的。在一些替代實施例中，穿孔108a可不規則地或隨機地排列，亦即，穿孔108a之間的距離不是恆定的。在一些替代實施例中，例如，環形路徑P1是矩形的。然而，視半導體晶粒的形狀及/或要求而定，環形路徑P1可被設計為其他適合的環形狀，例如圓形、正方形或多邊形。
本文中，穿孔106a、106b表示功能性穿孔，且穿孔108a表示非功能性穿孔。具體而言，封裝結構中的穿孔106a、106b電性連接至同一封裝結構或另一封裝結構的前側或背側重佈線路結構或電性組件。然而，穿孔108a可處於浮置電位且與同一封裝結構或另一封裝結構的前側或背側重佈線路結構或電性組件電性絕緣。
在一些實施例中，如圖3中所示，穿孔108a可在第一方向及第二方向中的至少一者上與穿孔106a、106b部分地對齊，所述第一方向及第二方向垂直於將晶粒及半導體裝置進行堆疊所沿的堆疊方向。在一些實施例中，例如，第一方向及第二方向是例如x方向及y方向等的水平方向，且堆疊方向是例如z方向等的垂直方向。在一些替代實施例中，穿孔108a可不在第一方向及/或第二方向上與穿孔106a、106b對齊。在一些實施例中，穿孔108a與半導體晶粒的區域之間的距離可小於相鄰的穿孔106a、108a之間的距離。然而，在一些替代實施例中，穿孔108a與半導體晶粒的區域之間的距離可大於或實質上等於相鄰的穿孔106a、108a之間的距離。在一些實施例中，相鄰的穿孔106a、108a之間的距離可大於相鄰的穿孔106a、106b之間的距離。在一些實施例中，相鄰的穿孔106a、108a之間的距離可為相鄰的穿孔106a、106b之間的距離的二倍或更多倍長。例如，相鄰的穿孔106a、108a之間的距離可為相鄰的穿孔106a、106b之間的距離的三倍、四倍、五倍或六倍長。然而，在一些替代實施例中，相鄰的穿孔106a、108a之間的距離可小於或實質上等於相鄰的穿孔106a、106b之間的距離。
在一些實施例中，導熱圖案108的頂表面可與穿孔106a、106b的頂表面實質上齊平且共面。在一些實施例中，例如，穿孔108a的頂表面可與穿孔106a、106b的頂表面實質上齊平且共面。然而，在一些替代實施例中，導熱圖案108的頂表面可低於或高於穿孔106a、106b的頂表面。
在一些實施例中，導熱圖案108的材料包括銅（Cu）、鋁（Al）、鋁銅合金（AlCu）、金、鈦、鈷、其合金、或任何其他適合的導電材料。可例如藉由電化學鍍覆（ECP）、電鍍、無電鍍覆或任何其他適合的製程來形成導熱圖案108。在一些實施例中，例如，導熱圖案108的材料可與穿孔106a、106b的材料相同。在一些替代實施例中，導熱圖案108的材料可不同於穿孔106a、106b的材料。在一些實施例中，導熱圖案108與穿孔106a、106b可同時形成。例如，穿孔108a與穿孔106a、106b可同時形成。在一些實施例中，為達成鍍覆均勻性，穿孔108a的尺寸（例如，寬度W2）介於穿孔106a、106b中的一者的尺寸（例如，寬度W1）的一半至二倍的範圍內。在一些實施例中，例如，寬度W2小於寬度W1。在一些替代實施例中，穿孔106a、106b與導熱圖案108可分別形成。
參照圖1及圖2B，在步驟S30中，提供半導體晶粒110並將其設置於載板102之上暴露出的緩衝層104上。在一些實施例中，半導體晶粒110可為數位晶片、類比晶片、或混合訊號晶片，例如應用專用積體電路（application-specific integrated circuit，「ASIC」）晶片、感測晶片、無線與射頻晶片、記憶體晶片、邏輯晶片、電壓調節器晶片、或任何其他適合的晶片。在一些實施例中，例如，半導體晶粒110為系統晶片（system on chip，SoC）。在一些實施例中，半導體晶粒110包括基底112、主動表面114a、與主動表面114a相對的背表面114b、分佈於主動表面114a上的多個接墊116、覆蓋主動表面114a的鈍化層118、多個金屬柱120、及保護層122。基底112可為例如矽基底等半導體基底，但其可由包括但不限於矽鍺、矽碳、砷化鎵等的其他半導體材料形成。半導體晶粒110可包括形成於基底112中或基底112上的裝置層。在一些實施例中，裝置層可包括電晶體、電阻器、電容器、電感器等。接墊116可形成於裝置層上並電性連接至所述裝置層，且可為內連結構的接墊。接墊116由鈍化層118部分地暴露出，且金屬柱120設置於接墊116上並電性連接至接墊116。例如，接墊116為鋁接觸窗接墊。例如，金屬柱120為銅柱或銅合金柱。保護層122覆蓋金屬柱120及鈍化層118。在一些替代實施例中，在將半導體晶粒110放置於載板102上之前，金屬柱120是不被覆蓋的（即，未被模塑或包封的裸露晶粒）。在一些實施例中，保護層122是聚合物層。例如，保護層122包含例如PBO、聚醯亞胺、BCB、其組合等感光性材料。
在一些實施例中，半導體晶粒110的頂表面不與穿孔106a、106b的及導熱圖案108的頂表面共面。在一些實施例中，例如，半導體晶粒110的頂表面低於穿孔106a、106b的及導熱圖案108的頂表面。在一些替代實施例中，半導體晶粒110的頂表面可實質上齊平於或高於穿孔106a、106b的及導熱圖案108的頂表面。在一些實施例中，在半導體晶粒110的背表面114b與緩衝層104之間設置有晶粒貼合膜124以達成更佳貼合，且半導體晶粒110的背表面114b黏附至載板102。在一些實施例中，半導體晶粒110在導熱圖案108旁邊的區域中放置於載板102之上。在一些實施例中，半導體晶粒110設置於由導熱圖案108環繞的區域內。
在一些實施例中，導熱圖案108環繞半導體晶粒110，且穿孔106a、106b環繞導熱圖案108。換言之，導熱圖案108設置於半導體晶粒110與穿孔106a、106b之間。因此，穿孔108a與半導體晶粒110之間的第一最小距離D1小於穿孔106a與半導體晶粒110之間的第二最小距離D2。在一些實施例中，例如，穿孔106a、106b及導熱圖案108分別分佈於半導體晶粒110的四側處。在一些實施例中，例如，穿孔106a、106b及穿孔108a分別分佈於半導體晶粒110的四側處。在一些實施例中，在半導體晶粒110的一側的穿孔106a、106b及穿孔108a的分佈與在半導體晶粒110的另一側的穿孔106a、106b及穿孔108a的分佈實質上對稱。具體而言，相對於中心半導體晶粒110，一側處的穿孔106a、106b及穿孔108a在配置及位置上與另一側處的穿孔106a、106b及穿孔108a對稱。在一些實施例中，如圖2B中所示，虛線表示在後續切割製程中整個封裝的切割線，並且穿孔106b被排列成靠近切割線但不位於切割線上且圍繞導熱圖案108及半導體晶粒110排列。
參照圖1及圖2C，在步驟S40中，在載板102之上形成包封體130，以包封半導體晶粒110、穿孔106a、106b及導熱圖案108。在一些實施例中，包封體130覆蓋緩衝層104且填充於半導體晶粒110、導熱圖案108及穿孔106a、106b之中。在一些實施例中，包封體130設置於半導體晶粒110、穿孔108a及穿孔106a、106b之中。在一些實施例中，包封體130橫向包封半導體晶粒110，亦即，半導體晶粒110的側壁由包封體130包封。在一些實施例中，藉由以下來形成包封體130：藉由包覆模塑製程（over-molding process）來形成對半導體晶粒110的頂表面、穿孔106a、106b的頂表面及導熱圖案108的頂表面進行覆蓋的模塑材料，然後藉由平坦化製程移除模塑材料的部分以暴露出半導體晶粒110的頂表面、穿孔106a、106b的頂表面及導熱圖案108的頂表面。在一些實施例中，用於將模塑材料以及半導體晶粒110、穿孔106a、106b及導熱圖案108平坦化的平坦化製程包括飛切（fly cut）製程、研磨製程、化學機械拋光（chemical mechanical polishing，「CMP」）製程或任何其他適合的製程。在一些實施例中，半導體晶粒110的保護層122的部分、穿孔106a、106b的部分及導熱圖案108的部分亦藉由所述平坦化製程移除。在一些實施例中，包封體130的第一表面130a與半導體晶粒110的保護層122及金屬柱120的頂表面、穿孔106a、106b的頂表面及導熱圖案108的頂表面實質上共面且齊平。在一些實施例中，穿孔106a、106b及導熱圖案108分別穿透且嵌入於包封體130。在一些實施例中，包封體130包含模塑化合物、模塑底膠、樹脂（例如環氧樹脂）、感光性材料（例如PBO）、聚醯亞胺、BCB、其組合等。
參照圖1及圖2D，在步驟S50中，在一些實施例中，在包封體130、半導體晶粒110、穿孔106a、106b及導熱圖案108之上形成重佈線路結構140。在一些實施例中，重佈線路結構140形成於包封體130的第一表面130a、半導體晶粒110的主動表面114a、以及穿孔106a、106b的及導熱圖案108的頂表面之上。在一些實施例中，重佈線路結構140設置於半導體晶粒110的金屬柱120的頂表面上。在一些實施例中，重佈線路結構140電性連接至穿孔106a、106b及半導體晶粒110且與導熱圖案108電性絕緣。
在一些實施例中，重佈線路結構140包括介電層142及位於介電層142中的多個重佈線圖案144。在一些實施例中，重佈線圖案144電性連接至同一封裝結構的穿孔106a、106b或電性組件（例如半導體晶粒110的金屬柱120）。在一些實施例中，重佈線圖案144與導熱圖案108電性絕緣。在一些實施例中，例如，重佈線路結構140的底部重佈線圖案144接觸穿孔106a、106b及半導體晶粒110的金屬柱120。在一些實施例中，導熱圖案108藉由介電層142與重佈線圖案144電性絕緣。在一些實施例中，例如，導熱圖案108接觸底部介電層142。在一些實施例中，重佈線圖案144的材料包括鋁、鈦、銅、鎳、鎢、銀及/或其合金。在一些實施例中，介電層142的材料包括聚醯亞胺、苯環丁烷、或聚苯並噁唑。在一些實施例中，介電層142可為單層式或多層式結構。在一些實施例中，重佈線路結構140是電性連接至半導體晶粒110的前側重佈線路結構且電性連接至穿孔106a、106b。在一些實施例中，由於下方的包封體130提供較佳的平坦化及平整度，因此可在平坦且齊整的包封體130之上以均勻線寬度或平整輪廓來形成稍後形成的重佈線路結構140（尤其是具有細線寬度或緊密間距的重佈線圖案144），進而得到改良的線/佈線可靠性。
在一些實施例中，多個導電元件146設置於重佈線路結構140上並電性連接至重佈線路結構140。在一些實施例中，在設置導電元件146之前，可施加助焊劑（flux），以使導電元件146更佳地固定至重佈線路結構140的頂部重佈線圖案144，且頂部重佈線圖案144可作為導電元件146的接觸接墊。在一些實施例中，導電元件146例如為放置於重佈線路結構140上的焊料球或球柵陣列（ball grid array，「BGA」）球，且在導電元件146之下的頂部重佈線圖案144作為球接墊。在一些實施例中，導電元件146中的一些藉由重佈線路結構140電性連接至半導體晶粒110，且導電元件146中的一些電性連接至穿孔106a、106b。在一些實施例中，導電元件146與導熱圖案108電性絕緣。
參照圖1以及圖2D及圖2E，在步驟S60中，在一些實施例中，將整個封裝自載板102剝離，以將半導體晶粒110與載板102分離。在一些實施例中，在自載板102剝離之後，藉由蝕刻製程或清潔製程來移除保留於整個封裝上的緩衝層104。作為另一選擇，在一些替代實施例中，可保留緩衝層104。
然後，在一些實施例中，將整個封裝倒置並設置於載板膜150上。由於封裝結構被倒置，因此頂表面可變為底表面且相對位置關係（例如上方、下方、更高或更低）可變為與以上所述的封裝結構相反，但相同的表面、共同的表面或介面將以與所述半導體封裝相同的參考編號來標記。在自載板102剝離之後，晶粒貼合膜124暴露出。在一些實施例中，晶粒貼合膜124的頂表面與包封體130的頂表面、穿孔106a、106b的頂表面及導熱圖案108的頂表面實質上共面且齊平。
之後，移除晶粒貼合膜124，且因此在包封體130中於半導體晶粒110之上形成溝渠132。在一些實施例中，在移除晶粒貼合膜124之後，半導體晶粒110的背表面114b暴露出。在一些實施例中，半導體晶粒110的背表面114b低於包封體130的與第一表面130a相對的第二表面130b。另外，半導體晶粒110的背表面114b低於穿孔106a、106b的頂表面及導熱圖案108的頂表面。
參照圖1以及圖2E及2F，在步驟S70中，在一些實施例中，於半導體晶粒110及包封體130之上形成導熱層160，其中導熱圖案108藉由導熱層160熱耦合至半導體晶粒110。在一些實施例中，熱量耗散結構包括導熱圖案108及導熱層160。如本文中所使用，熱耦合意指引起熱量耗散結構的溫度改變將會引起半導體晶粒的溫度改變，反之亦然。在一些實施例中，導熱層160形成於半導體晶粒110的背表面114b之上，以填充溝渠132。因此，導熱層160及重佈線路結構140設置於半導體晶粒110的相對二側上。在一些實施例中，導熱層160自半導體晶粒110的背表面114b向外延伸，以覆蓋包封體130的第二表面130b的部分及導熱圖案108的頂表面。在一些實施例中，導熱層160覆蓋包封體130的在導熱圖案108的頂表面旁邊的第二表面130b。在一些實施例中，導熱層160與穿孔106a、106b的頂表面分隔開，以與穿孔106a、106b電性絕緣。換言之，導熱層160的邊緣與穿孔106a的邊緣分隔開，且因此導熱層160與穿孔106a電性絕緣。
在一些實施例中，導熱層160可接觸半導體晶粒110的背表面114b、包封體130的第二表面130b的部分及導熱圖案108的頂表面。在一些實施例中，例如，導熱層160完全覆蓋導熱圖案108的頂表面。然而，在一些替代實施例中，導熱層160可部分地覆蓋導熱圖案108，或者可不覆蓋導熱圖案108。
在一些實施例中，導熱層160包括覆蓋半導體晶粒110的第一部分162、以及覆蓋包封體130及導熱圖案108的第二部分164。在一些實施例中，例如，第一部分162的頂表面與第二部分164的頂表面實質上齊平。然而，在一些替代實施例中，第一部分162的頂表面與第二部分164的頂表面可不彼此共面。在一些實施例中，由於第一部分162的一部分填充於溝渠132中，因此第一部分162厚於第二部分164。換言之，第一部分162的自半導體晶粒110的背表面114b至第一部分162自身的頂表面的厚度T1大於第二部分164的自包封體130的第二表面130b至第二部分164自身的頂表面的厚度T2。在一些實施例中，例如，厚度T2可大於或等於5微米（μm）。在一些實施例中，半導體晶粒110與導熱層160之間的介面低於包封體130與導熱層160之間的介面。導熱層160是例如銀膏等的導電膏，且例如是藉由印刷製程形成。
參照圖1及圖2G，在步驟S80中，將半導體裝置170堆疊於半導體晶粒110之上並電性連接至半導體晶粒110。在一些實施例中，半導體裝置170是例如動態隨機存取記憶體（dynamic random access memory，DRAM）封裝等的封裝、或任何其他適合的半導體裝置。在一些實施例中，半導體裝置170設置於半導體晶粒110之上的導熱層160上，且導熱層160設置於半導體晶粒110與半導體裝置170之間。在一些實施例中，半導體裝置170包括多個觸點172。例如，觸點172可為接墊或接墊上的金屬柱。半導體裝置170的觸點172藉由導電元件174及穿孔106a、106b電性連接至重佈線路結構140。在一些實施例中，導電元件174例如是放置於半導體裝置170上的焊料球或BGA球。在一些實施例中，在半導體裝置170與導熱層160之間形成有間隙G，亦即，間隙G小於導電元件174的高度。因此，導熱層160與半導體裝置170不接觸且因此電性絕緣。在一些實施例中，例如，間隙G可介於導電元件174的高度的25%至40%的範圍內。在一些實施例中，例如，半導體晶粒110與半導體裝置170之間的垂直距離可介於50微米至60微米的範圍內，且間隙G可大於10微米。在一些替代實施例中，導熱層160的至少一部分直接接觸半導體裝置170。換言之，例如，導熱層160的部分可接觸半導體裝置170，導熱層160的部分可與半導體裝置170有距離地分隔開，且導熱層160的頂表面可並非是平坦的。
參照圖2H，在一些實施例中，在導電元件174、半導體裝置170及導熱層160之中形成底膠176。因此，間隙G填充有底膠176。在一些實施例中，半導體裝置170與導熱層160之間的間隙G中的底膠176確保半導體裝置170與導熱層160之間的電性絕緣。
參照圖1、圖2H及圖2I，在一些實施例中，執行切分製程，以沿切割線（虛線）將整個封裝結構切割（至少切穿包封體130及重佈線路結構140）成單獨且分開的半導體封裝100，如圖2I中所示。在一個實施例中，切分製程是包括機械刀片鋸切或雷射切割的晶圓切分製程。在一些實施例中，例如，半導體封裝100是積體扇出型疊層封裝（integrated fan-out Package-on-Package，InFO PoP）裝置。在一些替代實施例中，例如，半導體封裝100可更安裝於電子裝置上，所述電子裝置可為例如印刷電路板（printed circuit board PCB）等的板。在一些替代實施例中，半導體封裝100可與附加封裝、晶片/晶粒或其他電子裝置安裝於一起。
在一些實施例中，如圖2I中所示，穿孔106a、106b及導熱圖案108在半導體晶粒110旁邊嵌入於包封體130中，且導熱層160設置於半導體晶粒110上並延伸至包封體130上。穿孔106a、106b電性連接至半導體晶粒110，且導熱圖案108與半導體晶粒110電性絕緣，但藉由導熱層160熱耦合至半導體晶粒110。因此，由半導體封裝100的任何組件（例如半導體晶粒110或半導體裝置170）產生的熱量可藉由導熱層160及導熱圖案108而耗散，且半導體封裝100的熱耗散面積得以擴展。因此，例如，與不具有導熱圖案及導熱層的傳統半導體封裝、具有導熱層（其不接觸半導體裝置）而不具有導熱圖案的傳統半導體封裝或者具有導熱層（其接觸半導體裝置）而不具有導熱圖案的傳統半導體封裝相較，半導體晶粒的熱耗散效率可得以改良。
在一些實施例中，導熱圖案108被示作具有沿一個環形路徑P1排列的多個離散穿孔108a，然而，本發明並非僅限於此。換言之，導熱圖案可沿多個環形路徑排列。在一些實施例中，如圖4中所示，導熱圖案108可包括沿多個環形路徑P1、P2排列的多個穿孔108a、108b。在一些實施例中，由離散穿孔108a形成的第一群組沿第一環形路徑P1排列，由離散穿孔108b形成的第二群組沿環繞第一環形路徑P1的第二環形路徑P2排列，且環形路徑P1、P2分別環繞半導體晶粒110。在一些實施例中，由穿孔108b形成的第二群組設置於由穿孔108a形成的第一群組與由穿孔106a形成的第一群組之間。在一些實施例中，穿孔108a的寬度可與穿孔108b的寬度相同或不同。在一些實施例中，例如，在與半導體晶粒110及半導體裝置170的堆疊方向垂直的方向上，第一群組的穿孔108a中的一者與第二群組的穿孔108b中的一者部分地對齊。另外，經對齊的穿孔108a、108b可更與經對齊的穿孔106a及穿孔106b對齊。然而，在一些替代實施例中，穿孔106a、106b可不彼此對齊，或者可不與穿孔108a、108b對齊。例如，在一些實施例中，如圖5中所示，在與堆疊方向垂直的方向上，第一群組的穿孔108a中的一者及第二群組的穿孔108b中的一者彼此緊鄰，且其可交替地設置。另外，在一些實施例中，彼此緊鄰的穿孔106a及穿孔106b亦可交替地設置。在一些實施例中，例如，在與堆疊方向垂直的方向上，第一群組的穿孔108a中的一者可與第一群組的穿孔106a中的一者部分地對齊，且類似地，第二群組的穿孔108b中的一者與第二群組的穿孔106b中的一者部分地對齊。
導熱圖案108可具有其他配置。例如，如圖6中所示，導熱圖案108包括環繞半導體晶粒110的環形結構108c。環形結構108c沿環形路徑P連續地形成。換言之，環形結構108c圍繞半導體晶粒110連續地設置。在一些實施例中，例如，環形結構108c的寬度W2可為實質上相同的，且寬度W2可介於穿孔106a、106b中的一者的尺寸（例如，寬度W1）的一半至二倍的範圍內。在一些替代實施例中，導熱圖案108可包括分別沿環繞半導體晶粒110的多個環形路徑設置的多個環形結構。
在一些實施例中，如圖7及圖8中所示，導熱圖案108可包括多個離散壁形結構108d。壁形結構108d彼此分隔開，且壁形結構108d沿一個環形路徑P排列。在一些實施例中，如圖7中所示，壁形結構108d分別設置於半導體晶粒110的一側處。在一些實施例中，例如，壁形結構108d為立方體。在一些實施例中，如圖8中所示，至少一個壁形結構108d可設置於半導體晶粒110的二個相鄰側處。在一些替代實施例中，例如，一個壁形結構108d可設置於半導體晶粒110的三個或四個相鄰側處。在一些實施例中，例如，壁形結構108d的寬度W2可為實質上相同的，且寬度W2可介於穿孔106a、106b中的一者的尺寸（例如，寬度W1）的一半至二倍的範圍內。在一些替代實施例中，壁形結構108d的寬度W2可為不同的。在一些替代實施例中，壁形結構108d可沿分別環繞半導體晶粒110的多個環形路徑排列。另外，應注意，在圖3至圖8中，半導體晶粒110與導熱圖案108之間或導熱圖案108與穿孔106a之間的距離是為說明起見而例示，實際上，在一些實施例中，例如，上述距離可大於相鄰的二個穿孔106a、106b之間的距離。然而，在一些替代實施例中，上述距離可等於或小於相鄰的二個穿孔106a、106b之間的距離。此外，圖3至圖8中的導熱圖案108的材料可為例如針對穿孔108a所述的導電材料等的導電材料。
在上述實施例中，導熱圖案被示作沿一個環形路徑或二個環形路徑排列，然而，本發明並非僅限於此。換言之，導熱圖案可沿多於二個環形路徑排列。另外，各環形路徑可具有相同或不同的形狀，且導熱圖案的沿相鄰的二個環形路徑的組件之間的間距可為相同或不同的。
圖9是示出根據一些實施例的半導體封裝的示意性剖視圖。圖9所示半導體封裝與圖2I所示半導體封裝之間的差異在於重佈線路結構更包括虛擬圖案（dummy pattern）。以下詳細地說明所述差異，且本文中不再對相似處予以贅述。在一些實施例中，如圖9中所示，重佈線路結構140更包括與封裝結構中的重佈線圖案144或者同一封裝結構或另一封裝結構的電性組件電性絕緣的虛擬圖案148。在一些實施例中，虛擬圖案148設置於重佈線路結構140的底部處。在一些實施例中，虛擬圖案148設置於包封體130的第一表面130a上且設置於重佈線路結構140的介電層142中。在一些實施例中，導熱圖案108連接至虛擬圖案148，此意味著導熱圖案108電性連接至虛擬圖案148。在一些實施例中，例如，導熱圖案108可接觸虛擬圖案148。在一些實施例中，導熱圖案108在第一側處熱耦合至導熱層160，且在與第一側相對的第二側處熱耦合至虛擬圖案148。因此，由半導體封裝產生的熱量可藉由導熱層160、導熱圖案108及虛擬圖案148而耗散，且半導體晶粒110的熱耗散面積得以擴展。因此，熱耗散效率可得以改良。
圖10是示出根據一些實施例的半導體封裝的示意性剖視圖。圖10所示半導體封裝與圖2I所示半導體封裝之間的差異在於半導體封裝更包括晶粒貼合膜。以下詳細地說明所述差異，且本文中不再對相似處予以贅述。在一些實施例中，如圖10中所示，例如，若晶粒貼合膜124具有良好導熱性，則晶粒貼合膜124在形成導熱層160之前可不被移除，且因此，晶粒貼合膜124可設置於半導體晶粒110與導熱層160之間。在一些實施例中，導熱層160可實質上具有恆定厚度T，亦即，半導體晶粒110之上的第一部分162與包封體130及導熱圖案108之上的第二部分164可實質上具有相同的厚度T。例如，厚度T可大於或等於5微米。
在一些實施例中，半導體封裝具有熱耦合至半導體晶粒的熱量耗散結構。在一些實施例中，熱量耗散結構包括半導體晶粒旁邊的導熱圖案及設置於半導體晶粒上且延伸至導熱圖案上的導熱層。因此，導熱圖案可藉由導熱層熱耦合至半導體晶粒。藉由設置熱量耗散結構，半導體封裝的熱耗散面積可大幅擴展，且半導體封裝的熱量耗散效率可顯著改良。另外，雖然導熱層設置於半導體晶粒與半導體裝置之間，但導熱層的高度受到控制以防止與其之上的半導體裝置接觸。因此，可防止例如晶圓上封裝（Package on Wafer，PoW）冷縫（cold joint）風險等的冷縫風險及其他製程問題。此外，使導熱層延伸至包封體及導熱圖案上會增加半導體晶粒與導熱層之間的接觸面積，藉此增強導熱層與半導體晶粒的黏附性。因此，半導體封裝的熱耗散是穩定的且得以改良。
根據一些實施例，一種半導體封裝包括半導體晶粒、導熱圖案、包封體及導熱層。所述導熱圖案設置於所述半導體晶粒旁邊。所述包封體包封所述半導體晶粒及所述導熱圖案。所述導熱層覆蓋所述半導體晶粒的背表面，其中所述導熱圖案藉由所述導熱層而熱耦合至所述半導體晶粒且與所述半導體晶粒電性絕緣。
根據一些實施例，一種半導體封裝包括半導體晶粒、包封體、第一穿孔、第二穿孔及導熱層。所述包封體橫向包封所述半導體晶粒。所述第一穿孔嵌入於所述包封體中且電性連接至所述半導體晶粒。所述第二穿孔嵌入於所述包封體中且與所述半導體晶粒電性絕緣。所述導熱層覆蓋所述半導體晶粒，其中所述第二穿孔藉由所述導熱層而熱耦合至所述半導體晶粒。
根據一些實施例，一種半導體封裝包括半導體晶粒、包封體、第一穿孔、第二穿孔及導熱層。所述包封體橫向包封所述半導體晶粒。所述第一穿孔嵌入於所述包封體中且電性連接至所述半導體晶粒。所述第二穿孔嵌入於所述包封體中且與所述半導體晶粒電性絕緣。所述導熱層覆蓋所述半導體晶粒及所述包封體，其中所述導熱層包括覆蓋所述半導體晶粒的第一部分及覆蓋所述第二穿孔的第二部分，且所述導熱層的所述第一部分厚於所述導熱層的所述第二部分。上述內容概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應瞭解，其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
100:半導體封裝 102:載板 104:緩衝層 106a、106b、108a、108a、108b:穿孔 108:導熱圖案 108c:環形結構 108d:壁形結構 110:半導體晶粒 112:基底 114a:主動表面 114b:背表面 116:接墊 118:鈍化層 120:金屬柱 122:保護層 124:晶粒貼合膜 130:包封體 130a:第一表面 130b:第二表面 132:溝渠 140:重佈線路結構 142:介電層 144:重佈線圖案 146、174:導電元件 148:虛擬圖案 150:載板膜 160:導熱層 162:第一部分 164:第二部分 170:半導體裝置 172:觸點 176:底膠 D1:第一最小距離 D2:第二最小距離 G:間隙 P、P1、P2:環形路徑 S10、S20、S30、S40、S50、S60、S70、S80:步驟 T、T1、T2:厚度 W1、W2:寬度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據業界中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1是示出根據一些實施例形成半導體封裝的方法的製程步驟的示例性流程圖。 圖2A至圖2I是根據一些實施例形成半導體封裝的方法的剖視圖。 圖3是圖2I的簡化俯視圖。 圖4是根據一些實施例的半導體封裝的簡化俯視圖。 圖5是根據一些實施例的半導體封裝的簡化俯視圖。 圖6是根據一些實施例的半導體封裝的簡化俯視圖。 圖7是根據一些實施例的半導體封裝的簡化俯視圖。 圖8是根據一些實施例的半導體封裝的簡化俯視圖。 圖9是示出根據一些實施例的半導體封裝的示意性剖視圖。 圖10是示出根據一些實施例的半導體封裝的示意性剖視圖。
100:半導體封裝
106a、106b、108a:穿孔
108:導熱圖案
110:半導體晶粒
112:基底
114a:主動表面
114b:背表面
116:接墊
118:鈍化層
120:金屬柱
122:保護層
130:包封體
130a:第一表面
130b:第二表面
140:重佈線路結構
142:介電層
144:重佈線圖案
146、174:導電元件
160:導熱層
162:第一部分
164:第二部分
170:半導體裝置
172:觸點
176:底膠
T1、T2:厚度

Claims (20)

  1. 一種半導體封裝，包括： 半導體晶粒； 導熱圖案，在所述半導體晶粒旁邊； 包封體，包封所述半導體晶粒及所述導熱圖案；以及 導熱層，覆蓋所述半導體晶粒的背表面，其中所述導熱圖案藉由所述導熱層而熱耦合至所述半導體晶粒且與所述半導體晶粒電性絕緣。
  2. 如申請專利範圍第1項所述的半導體封裝，更包括堆疊於所述半導體晶粒之上且電性連接至所述半導體晶粒的半導體裝置。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述導熱圖案包括多個離散穿孔。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述多個離散穿孔沿環繞所述半導體晶粒的至少一個環形路徑排列。
  5. 如申請專利範圍第1項所述的半導體封裝，其中所述導熱圖案包括環繞所述半導體晶粒的環形結構。
  6. 如申請專利範圍第1項所述的半導體封裝，其中所述導熱圖案包括多個離散壁形結構。
  7. 如申請專利範圍第1項所述的半導體封裝，更包括設置於所述半導體晶粒的主動表面及所述包封體的第一表面之上的重佈線路結構，其中所述半導體晶粒的所述主動表面與所述半導體晶粒的所述背表面相對，且所述重佈線路結構電性連接至所述半導體晶粒。
  8. 如申請專利範圍第7項所述的半導體封裝，其中所述重佈線路結構更包括設置於所述包封體的所述第一表面上的虛擬圖案，且所述導熱圖案連接至所述虛擬圖案。
  9. 如申請專利範圍第1項所述的半導體封裝，其中所述導熱層自所述半導體晶粒的所述背表面向外延伸以部分地覆蓋所述包封體的第二表面，且所述包封體的所述第二表面與所述包封體的所述第一表面相對。
  10. 一種半導體封裝，包括： 半導體晶粒； 包封體，橫向包封所述半導體晶粒； 第一穿孔，嵌入於所述包封體中且電性連接至所述半導體晶粒； 第二穿孔，嵌入於所述包封體中且與所述半導體晶粒電性絕緣；以及 導熱層，覆蓋所述半導體晶粒，其中所述第二穿孔藉由所述導熱層而熱耦合至所述半導體晶粒。
  11. 如申請專利範圍第10項所述的半導體封裝，更包括堆疊於所述半導體晶粒之上且電性連接至所述半導體晶粒的半導體裝置，其中所述導熱層與所述半導體裝置有距離地分隔開。
  12. 如申請專利範圍第10項所述的半導體封裝，其中所述導熱層設置於所述半導體晶粒之上且延伸至所述第二穿孔上。
  13. 如申請專利範圍第10項所述的半導體封裝，其中所述導熱層接觸所述半導體晶粒及所述第二穿孔。
  14. 如申請專利範圍第10項所述的半導體封裝，其中所述導熱層包括覆蓋所述半導體晶粒的第一部分以及覆蓋所述包封體的第二部分，且所述第一部分厚於所述第二部分。
  15. 如申請專利範圍第10項所述的半導體封裝，其中所述第一穿孔與所述半導體晶粒之間的第一最小距離小於所述第二穿孔與所述半導體晶粒之間的第二最小距離。
  16. 一種半導體封裝，包括： 半導體晶粒； 包封體，橫向包封所述半導體晶粒； 第一穿孔，嵌入於所述包封體中且電性連接至所述半導體晶粒； 第二穿孔，嵌入於所述包封體中且與所述半導體晶粒電性絕緣；以及 導熱層，覆蓋所述半導體晶粒及所述包封體，其中所述導熱層包括覆蓋所述半導體晶粒的第一部分及覆蓋所述第二穿孔的第二部分，且所述導熱層的所述第一部分厚於所述導熱層的所述第二部分。
  17. 如申請專利範圍第16項所述的半導體封裝，其中所述導熱層部分地覆蓋所述包封體。
  18. 如申請專利範圍第16項所述的半導體封裝，其中所述第一穿孔與所述半導體晶粒之間的第一最小距離大於所述第二穿孔與所述半導體晶粒之間的第二最小距離。
  19. 如申請專利範圍第16項所述的半導體封裝，其中所述第二通孔的第二寬度介於所述第一穿孔的第一寬度的一半至二倍的範圍內。
  20. 如申請專利範圍第16項所述的半導體封裝，其中所述導熱層接觸所述第二穿孔。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10916488B2 (en) * 2018-06-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having thermal conductive pattern surrounding the semiconductor die
EP3621104A1 (en) * 2018-09-05 2020-03-11 Infineon Technologies Austria AG Semiconductor package and method of manufacturing a semiconductor package
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
KR20210073809A (ko) * 2019-12-11 2021-06-21 삼성전자주식회사 반도체 패키지 및 그 제조방법
FR3109466A1 (fr) * 2020-04-16 2021-10-22 Stmicroelectronics (Grenoble 2) Sas Dispositif de support d’une puce électronique et procédé de fabrication correspondant
KR102328997B1 (ko) * 2020-04-21 2021-11-18 삼성전기주식회사 방열부를 갖는 전자 소자 모듈 및 그 제조 방법
JP2022002237A (ja) * 2020-06-19 2022-01-06 日本電気株式会社 量子デバイス及びその製造方法
US11527518B2 (en) 2020-07-27 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation in semiconductor packages and methods of forming same
KR20220042028A (ko) * 2020-09-25 2022-04-04 삼성전자주식회사 반도체 패키지
US11682602B2 (en) * 2021-02-04 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
WO2022236216A1 (en) * 2021-05-06 2022-11-10 Qualcomm Technologies, Inc. High power die heat sink with vertical heat pin
US11948853B2 (en) * 2021-05-06 2024-04-02 QUALCOMM Technologies Incorporated High-power die heat sink
US11929299B2 (en) * 2021-05-06 2024-03-12 Qualcomm Incorporated High-power die heat sink with vertical heat path
US11967591B2 (en) * 2021-08-06 2024-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Info packages including thermal dissipation blocks

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3281254A (en) 1963-03-28 1966-10-25 Bausch & Lomb Fluophosphate glasses
US3299649A (en) 1966-02-01 1967-01-24 Carrier Corp Separation systems
US8237252B2 (en) 2009-07-22 2012-08-07 Stats Chippac, Ltd. Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation
US8003496B2 (en) * 2009-08-14 2011-08-23 Stats Chippac, Ltd. Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
KR101257218B1 (ko) 2011-09-30 2013-04-29 에스티에스반도체통신 주식회사 패키지 온 패키지 및 이의 제조방법
US8710640B2 (en) 2011-12-14 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with heat slug and method of manufacture thereof
CN102543970A (zh) * 2011-12-26 2012-07-04 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US9136202B2 (en) 2012-04-17 2015-09-15 Qualcomm Incorporated Enhanced package thermal management using external and internal capacitive thermal material
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
TW201442203A (zh) * 2013-02-11 2014-11-01 Marvell World Trade Ltd 層疊封裝結構
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9269694B2 (en) * 2013-12-11 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal management features for reduced thermal crosstalk and methods of forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9978660B2 (en) * 2014-03-14 2018-05-22 Taiwan Semiconductor Manufacturing Company Package with embedded heat dissipation features
JP6415365B2 (ja) 2014-03-28 2018-10-31 株式会社ジェイデバイス 半導体パッケージ
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR102265243B1 (ko) 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9746889B2 (en) * 2015-05-11 2017-08-29 Qualcomm Incorporated Package-on-package (PoP) device comprising bi-directional thermal electric cooler
KR102424402B1 (ko) * 2015-08-13 2022-07-25 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
CN106971993B (zh) 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
US9881908B2 (en) * 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9960150B2 (en) 2016-06-13 2018-05-01 Micron Technology, Inc. Semiconductor device assembly with through-mold cooling channel formed in encapsulant
US10332843B2 (en) 2016-08-19 2019-06-25 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR101983185B1 (ko) 2016-08-19 2019-05-29 삼성전기주식회사 팬-아웃 반도체 패키지
KR102442623B1 (ko) 2017-08-08 2022-09-13 삼성전자주식회사 반도체 패키지
US10916488B2 (en) * 2018-06-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having thermal conductive pattern surrounding the semiconductor die

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