TW201442203A - 層疊封裝結構 - Google Patents

層疊封裝結構 Download PDF

Info

Publication number
TW201442203A
TW201442203A TW103104424A TW103104424A TW201442203A TW 201442203 A TW201442203 A TW 201442203A TW 103104424 A TW103104424 A TW 103104424A TW 103104424 A TW103104424 A TW 103104424A TW 201442203 A TW201442203 A TW 201442203A
Authority
TW
Taiwan
Prior art keywords
package
die
substrate layer
solder balls
arrangement
Prior art date
Application number
TW103104424A
Other languages
English (en)
Inventor
Hua-Hung Kao
Shiann-Ming Liou
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/176,695 external-priority patent/US20140151880A1/en
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW201442203A publication Critical patent/TW201442203A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H01L23/4275—Cooling by change of state, e.g. use of heat pipes by melting or evaporation of solids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本揭露內容之實施例提供一種層疊封裝佈置，其包含一第一封裝，該第一封裝包括：一基材層，其包括一頂側及與該頂側相對之一底側，其中該基材層之該頂側界定一大體上平坦的表面；以及一第一晶粒，其耦接至該基材層之該底側。該佈置亦包含一第二封裝，該第二封裝包括複數列焊球及一主動元件或一被動元件中之一或兩者中之至少一個。該第二封裝係經由該等複數列焊球附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。該主動元件及/或一被動元件附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。

Description

層疊封裝結構 【相關申請案之交互參照】
本申請案主張2013年2月11日申請之美國臨時申請案第61/763,285號之優先權，該美國臨時申請案之完整說明以引用方式併入本文中。本申請案亦為2012年8月13日申請之美國專利申請案第13/584,027號之部分連續案，該美國專利申請案主張2011年8月19日申請之美國臨時申請案第61/525,521號之優先權，該美國臨時申請案之完整說明以引用方式併入本文中。
本揭露內容之實施例係關於層疊封裝(POP)結構，且更具體而言係關於併入有晶粒朝下倒裝式(die-down flipped)結構之基本封裝的封裝佈置。
本文提供之背景描述係出於大體上呈現本揭露內容之上下文之目的。既未明確承認亦未默示承認當前署名發明者之著作在該著作在此背景部分中描述之程度上，以及在申請時在其他方面可能無法取得先前技術資格的描述之各觀點為相對於本揭露內容之先前技術。
通常，在許多多晶片封裝佈置的情況下，封裝佈置係佈置在層疊封裝(PoP)佈置或多晶片模組(MCM)佈置之一中。此等封裝佈置傾向於相當厚實(例如，近似1.7毫米至2.0毫米)。
PoP佈置可包括積體電路，該積體電路組合彼此疊加的兩個或兩個以上封裝。舉例而言，PoP佈置可使用兩個或兩個以上記憶體裝置封裝來組配。PoP佈置亦可使用混合邏輯-記憶體堆疊來組配，該混合邏輯-記憶體堆疊包括位於底部封裝中之邏輯及位於頂部封裝中之記憶體，或反之亦然。
通常，與位於PoP佈置之底部上的封裝(本文稱為「底部封裝」)相關聯之晶粒將位於底部封裝上方之封裝(本文稱為「頂部封裝」)的覆蓋區域限制於一特定大小。另外，此組態大體上將頂部封裝限制於兩列周邊焊球。此封裝佈置1100之一實例於圖11中例示出，且包括頂部封裝1102及底部封裝1104。如可看出，底部封裝1104包括經由黏合劑1110附接至基材1108之晶粒1106。晶粒1106係經由線接合製程使用線1112耦接至基材1108。焊球1114經提供以用於將封裝佈置1100耦接至諸如像印刷電路板(PCB)之另一基材(未例示)。頂部封裝1102包括耦接至基材1116之晶粒1116。焊球1120經提供以將頂部封裝1102耦接至底部封裝1104。頂部封裝1102可包括包殼1122，必要時，該包殼大體上以包封體之形式。如可看出，由於底部封裝1104之晶粒1106及包殼1124(大體上以包封體之形式且可能包括在內或不包括在內)之存在而僅可提供兩列焊球1120。因此，可能需要頂部封裝具有較大的大小或覆蓋區域，以便在頂部封裝附接至底部封裝時避開底部封裝之晶粒1106。此類封裝佈置1100亦可存在問題，即頂部封裝1102相對於晶粒1106及/或包殼1124之間隙問題。
圖11例示出封裝佈置1200之另一實例，其中已使用膜封陣列處理(MAP)創建底部封裝1204。底部封裝1204類似於圖11之底部封裝1104且包括包封體1206。包封體1206通常經蝕刻以暴露焊球1208。或者，包封體1206經蝕刻且隨後焊球1208沈積於開口1210中。此封裝佈置1200再次由於晶粒1106及包封體1206之存在而僅允許在頂部封裝1102之周邊周圍包括兩列焊球1120。此類封裝佈置1200亦可存在問題，即頂部封裝1102相對於晶粒1106及包封體1206之間隙問題，以及相對於開口1210之對準問題。
在各種實施例中，本揭露內容提供一種層疊封裝佈置，其包含一第一封裝，該第一封裝包括：一基材層，該基材層包括(i)一頂側及(ii)與該頂側相對之一底側，其中該基材層之該頂側界定一大體上平坦的表面；以及一第一晶粒，其耦接至該基材層之該底側。該層疊封裝佈置亦包含一第二封裝，該第二封裝包括複數列焊球及(i)主動元件或(ii)一被動元件 中之一或兩者中之至少一個。該第二封裝係經由該等複數列焊球附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。(i)一主動元件或(ii)一被動元件中之一或兩者中之該至少一個附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
在各種實施例中，本揭露內容亦提供一種方法，其包含提供一第一封裝，該第一封裝包括一基材層，其中該基材層包括(i)一頂側及(ii)與該頂側相對之一底側，其中該基材層之該頂側界定一大體上平坦的表面，且其中該第一封裝進一步包括一第一晶粒，該第一晶粒耦接至該基材層之該底側。該方法進一步包含：提供一第二封裝，其具有複數列焊球，該等複數列焊球附接至該第二封裝之一底表面；經由該第二封裝之該等複數列焊球將該第二封裝附接至該第一封裝之該大體上平坦的表面；以及將(i)一主動元件或(ii)一被動元件中之一或兩者中之至少一個附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
各種實施例潛在地包括以下優勢中之一或多者。根據本文所述之各種實施例，封裝佈置可提供增加的接腳數。又，可對於使用根據本文所述之各種實施例的封裝佈置的電子裝置實現更快的速度。
100‧‧‧封裝佈置
102‧‧‧頂部封裝
104‧‧‧底部封裝
106‧‧‧基材層
108‧‧‧第一晶粒/晶粒
110‧‧‧第二晶粒/晶粒
112‧‧‧焊球
114‧‧‧底部填充材料
115‧‧‧焊球
116‧‧‧基材層
117a‧‧‧頂側
117b‧‧‧底側
118‧‧‧晶粒
120‧‧‧黏合劑層
122(a)‧‧‧接合墊
122(b)‧‧‧接合墊
124(a)‧‧‧基材墊
124(b)‧‧‧基材墊
126(a)‧‧‧接合線
126(b)‧‧‧接合線
128‧‧‧包殼
129‧‧‧焊球
130‧‧‧焊球
131‧‧‧開口
200‧‧‧封裝佈置
204‧‧‧底部封裝
206‧‧‧導熱材料
208‧‧‧黏合劑層
210‧‧‧熱介面材料/TIM
300‧‧‧封裝佈置
304‧‧‧底部封裝
306‧‧‧焊球/焊點凸塊
308‧‧‧底部填充材料
310‧‧‧熱介面材料
400‧‧‧封裝佈置
404‧‧‧底部封裝
406‧‧‧矽穿孔/TSV
408‧‧‧焊球
500‧‧‧封裝佈置
504‧‧‧底部封裝
506‧‧‧PCB/中介層
510‧‧‧基材層
512‧‧‧焊球
600‧‧‧封裝佈置
604‧‧‧底部封裝
606‧‧‧焊球
608‧‧‧PCB或中介層
610‧‧‧焊球
700‧‧‧方法
800‧‧‧封裝佈置
802‧‧‧裝置
804‧‧‧底部封裝
806‧‧‧焊球
808‧‧‧基材層
810‧‧‧被動及/或主動電子元件/被動元件/主動元件
812‧‧‧導線
814‧‧‧焊料
900‧‧‧封裝佈置
902‧‧‧晶粒
904‧‧‧底部封裝
906‧‧‧焊球
910‧‧‧被動及/或主動元件/被動元件/主動元件
912‧‧‧導線
914‧‧‧焊料
916‧‧‧晶粒
918‧‧‧線
920‧‧‧黏合劑層
1000‧‧‧方法
1100‧‧‧封裝佈置
1102‧‧‧頂部封裝
1104‧‧‧底部封裝
1106‧‧‧晶粒
1108‧‧‧基材
1110‧‧‧黏合劑
1112‧‧‧線
1114‧‧‧焊球
1116‧‧‧晶粒
1120‧‧‧焊球
1122‧‧‧包殼
1124‧‧‧包殼
1200‧‧‧封裝佈置
1204‧‧‧底部封裝
1206‧‧‧包封體
1208‧‧‧焊球
1210‧‧‧開口
藉由以下結合隨附圖式之詳細描述將容易理解本揭露內容之實施例。為便於此描述，相同的參考數字指示相同的結構元件。在隨附圖式之諸圖中以實例之方式而非限制之方式例示出本文實施例。
圖1A示意性地例示出示例性封裝佈置，其包括晶粒朝下倒裝式PoP結構之示例性晶粒佈置。
圖1B示意性地例示出圖1A之示例性封裝佈置，其中頂部封裝附接至底部封裝。
圖2示意性地例示出另一示例性封裝佈置，其包括具有暴露材料以提供用於熱散逸之路徑的晶粒朝下倒裝式PoP結構之另一示例性晶粒佈置。
圖3示意性地例示出另一示例性封裝佈置，其包括經暴露以提供用於熱散逸之路徑的晶粒朝下倒裝式PoP結構之另一示例性晶粒佈置。
圖4示意性地例示出另一示例性封裝佈置，其包括具有矽穿孔(TSV)之晶粒朝下倒裝式PoP結構之另一示例性晶粒佈置。
圖5示意性地例示出另一示例性封裝佈置，其包括具有嵌入式印刷電路板(PCB)及/或中介層之晶粒朝下倒裝式PoP結構之另一示例性晶粒佈置。
圖6示意性地例示出另一示例性封裝佈置，其包括具有PCB/中介層之晶粒朝下倒裝式PoP結構之另一示例性晶粒佈置。
圖7為用於製作本文所述之PoP結構之方法的製程流程圖。
圖8示意性地例示出另一示例性封裝佈置，其包括示例性封裝式裝置佈置以及被動及/或主動電子元件。
圖9示意性地例示出另一示例性封裝佈置，其包括多個晶粒以及被動及/或主動電子元件。
圖10為用於製作本文所述之PoP結構之方法的另一製程流程圖。
圖11示意性地例示出示例性PoP封裝佈置。
圖12示意性地例示出另一示例性PoP封裝佈置。
圖1A例示出根據一實施例之封裝佈置100，其中層疊封裝(PoP)封裝佈置包括頂部封裝102及底部封裝104。出於說明性目的，將封裝作為單獨項目例示出。頂部封裝102包括基材層106。頂部封裝102內之晶粒佈置可包括第一晶粒108及第二晶粒110，其中每一晶粒108、110係經由焊球112附接至基材層106。此組態可包括位於焊球112與基材層106之間的空間中之底部填充材料114。焊球112通常位於接合墊或接觸區域(未例示)處。晶粒108、110可經由倒裝晶片操作耦接至基材層106。或者，線接合製程及黏合劑層(未例示)可用來將晶粒108、110耦接至基材層106。另外，頂部封裝102可包含兩個或兩個以上獨立頂部封裝102(未例示)，其中每一獨立頂部封裝102皆包括一或多個晶粒。
根據各種實施例，第一晶粒108及第二晶粒110為記憶體裝置，根據一實施例，第一晶粒108及第二晶粒110係用於行動裝置的行動 雙倍資料速率(mDDR)同步動態隨機存取記憶體(DRAM)。行動DDR亦稱為低功率DDR。然而，可利用其他類型之記憶體裝置，包括但不限於雙倍資料速率同步動態隨機存取記憶體(DDR SDRAM)、動態隨機存取記憶體(DRAM)、NOR或NAND快閃記憶體、靜態隨機存取記憶體(SRAM)及其類似者。
根據另一實施例，具有第一晶粒108及第二晶粒110之頂部封裝102係針對特殊應用產品，且根據一實施例，第一晶粒108及/或第二晶粒110可代表用於行動裝置的特殊應用積體電路(ASIC)。
頂部封裝102進一步包括複數個焊球115。該等複數個焊球115可附接至頂部封裝102之基材層106的底側。在圖1A之實施例中，該等複數個焊球115形成用於將頂部封裝102電氣地且實體地附接或堆疊在底部封裝104上之組態。
為清楚起見，本文中可能並未詳細例示出且/或描述頂部封裝102內使用之材料及頂部封裝102內之其他元件。此等材料及元件在該項技術中通常係熟知的。
底部封裝104包括基材層116，該基材層包括頂側117a及底側117b。如圖1A中所示，頂側117a界定底部封裝104之大體上平坦的表面，亦即實質上無凹槽、凸塊、壓痕、凹部等之大體上光滑的表面。在一實施例中，頂側117a之大體上平坦的表面不含有任何元件，此容許頂側117a接收(或支撐)頂部封裝102之各種設計及選擇。因此，底部封裝104之平坦頂表面提供便利的方式，以用於頂部封裝102之複數個焊球115附接至底部封裝104，此允許設計頂部封裝102(或多個獨立頂部封裝102)及藉此設計封裝佈置100過程中之更大的靈活性。
底部封裝104包括晶粒118，該晶粒經由晶粒朝下倒裝式結構中之黏合劑層120附接至基材層116之底側117b。在其他實施例中，如本文將進一步論述，晶粒118可經由焊球附接至基材層116之底側117b。
根據各種實施例，晶粒118可係記憶體裝置，諸如用於行動裝置的行動雙倍資料速率(mDDR)同步動態隨機存取記憶體(DRAM)。可利用其他類型之記憶體裝置，包括但不限於雙倍資料速率同步動態隨機存取 記憶體(DDR SDRAM)、動態隨機存取記憶體(DRAM)、NOR或NAND快閃記憶體、靜態隨機存取記憶體(SRAM)及其類似者。根據另一實施例，晶粒118可係用於創建混合邏輯-記憶體堆疊之邏輯裝置，該混合邏輯-記憶體堆疊包括底部封裝104上之邏輯及頂部封裝102上之記憶體。
晶粒118具有包括一或多個接合墊122a、122b之表面。一或多個接合墊122a、122b通常包含諸如像鋁或銅之導電材料。在其他實施例中可使用其他適合的材料。晶粒118係經由耦接至對應的接合墊122a、122b之接合線126a、126b耦接至位於基材層116上之一或多個基材墊124a、124b。晶粒118可藉由模製材料附貼至底部封裝104。在其他實施例中，晶粒118可經由倒裝晶片或導電性黏合劑與基材層116電氣互連。晶粒118之電氣信號可包括例如用於形成於晶粒118上之積體電路(IC)裝置(未例示)的輸入/輸出(I/O)信號及/或功率/接地。
根據一實施例，底部封裝104係經由膜封陣列處理(MAP)創建。底部封裝104進一步包括大體上以包封體之形式的包殼128。包殼128經蝕刻以暴露焊球129。或者，在蝕刻包殼128之後將焊球129添加至包殼128之蝕刻的開口131中。焊球130被添加至焊球129且可用來將封裝佈置100耦接至諸如像印刷電路板(PCB)、另一封裝等之基材(未例示)。或者，在蝕刻包殼128之後將單個焊球(組合焊球129及焊球130)添加至蝕刻的開口131中。焊球130通常在側邊處或在底部封裝104之周邊周圍，藉此形成球柵陣列(BGA)。
為清楚起見，本文中可能並未詳細例示出且/或描述底部封裝104內使用之材料及底部封裝104內之其他元件。此等材料及元件在該項技術中通常係熟知的。
圖1B例示出封裝佈置100，其中頂部封裝102附接至底部封裝104。在圖1A及圖1B之實施例中，複數個焊球115形成用於將頂部封裝102電氣地且實體地附接或堆疊至底部封裝104之組態。如先前所述，頂部封裝102可包含附接至底部封裝104之兩個或兩個以上獨立頂部封裝。
本揭露內容之額外實施例一般而言涉及包括具有晶粒朝下倒裝式結構之底部封裝104之各種實施例且在圖2至圖6中例示出的封裝 佈置。為簡明起見，本文並未進一步論述與圖2至圖7中之元件相同或類似的圖1A及圖1B中所例示之元件。
圖2例示出包括頂部封裝102及底部封裝204之封裝佈置200的另一實施例。在圖2之實施例中，導熱材料206係包括在晶粒118之底側上。在一實施例中，導熱材料206係經由黏合劑層208附接至晶粒118之底側。導熱材料206包括但不限於金屬、矽或適合於良好導熱性之任何材料。
底部封裝204包括熱介面材料(TIM)210，該熱介面材料耦接至導熱材料206。TIM 210包括但不限於薄膜、油脂組合物及底部填充材料。薄膜可係超薄導熱材料，該超薄導熱材料可藉由沈積非晶材料來製備。油脂組合物可包括具有高導熱性及極佳分配特性之組合物。常見的TIM為白色膏狀或熱油脂，通常為充滿氧化鋁、氧化鋅或氮化硼之矽油。一些類型之TIM使用微粉化銀或化銀。另一種類型之TIM包括相變材料。相變材料通常在室溫下為固態，但在操作溫度下液化且表現如油脂。
可基於所需實體性質來選擇底部填充材料。因此，導熱材料206為TIM 210提供用於熱散逸之路徑。封裝佈置200可耦接至諸如像PCB或另一封裝佈置之基材(未例示)。可在基材中提供一孔以適應TIM 210。
圖3例示出包括頂部封裝102及底部封裝304之封裝佈置300的實施例。晶粒118係經由焊球306附接至基材層116。根據各種實施例，底部填充材料308係提供於晶粒118與基材層116之間的焊球306之中。底部填充材料308為藉由焊球306形成之接點提供保護。底部填充材料亦防止晶粒118之內層的開裂及脫層。底部填充材料308可為高純度、低應力液態環氧樹脂。大體而言，焊球306之大小愈大，對底部填充材料308之需求愈小。
底部封裝304包括熱介面材料(TIM)310，該熱介面材料耦接至晶粒118之背面。TIM 310包括但不限於薄膜、油脂組合物及底部填充材料，如先前所述。在圖3之實施例中，晶粒118之背面係暴露的。晶粒118之暴露的背面為TIM 310提供用於熱散逸之路徑。封裝佈置300可耦接至諸如像PCB或另一封裝佈置之基材(未例示)。可在基材中提供一孔以適 應TIM 310。
圖4例示出包括頂部封裝102及底部封裝404之封裝佈置400的實施例。晶粒118係經由焊點凸塊306附接至基材層116。底部填充材料308係提供在位於晶粒118與底部封裝404之基材層116之間的空間中。底部填充材料308為藉由焊球306形成之接點提供保護。
在圖4之實施例中，晶粒118包括矽穿孔(TSV)406。在一實施例中，晶粒118可凹入包殼128內，以幫助暴露晶粒118之背面。TSV 406係經由晶粒118傳遞至焊球306之垂直電氣連接穿孔(垂直互連接入)。在一實施例中，底部封裝404包括額外焊球408，該等額外焊球附接至底部封裝404。額外焊球408可用於例如接地/功率及輸入/輸出。
一或多個TSV 406電氣耦接至接合墊(未例示)且通常充滿例如銅之導電材料，以經由晶粒118路由電氣信號。TSV 406傾向於提供相對於接合線之改良的效能，因為與接合線相比穿孔之密度大體上較高，且連接之長度較短。晶粒118之暴露的背面提供底部封裝404之熱散逸。因此，封裝佈置400可為使用封裝佈置400之電子裝置提供增加之接腳數及較高的速度。
圖5例示出包括頂部封裝102及底部封裝504之封裝佈置500的實施例。晶粒118係經由焊點凸塊306附接至基材層510。
在圖5之實施例中，底部封裝504包括一或多個PCB及/或中介層506，該一或多個PCB及/或中介層附接至晶粒118之底側。根據各種實施例，PCB/中介層506係使用熱壓縮製程或焊料回流製程接合至晶粒118。亦即，將一或多個導電結構(例如柱桿、凸塊、墊、再分配層)形成於PCB/中介層506及晶粒118上，以便在PCB/中介層506與晶粒118之間形成接合。
在一些實施例中，晶粒118及PCB/中介層506兩者包含具有相同或類似熱膨脹係數(CTE)之材料(例如矽)。將具有相同或類似CTE之材料使用於晶粒118及PCB/中介層506降低了與材料之加熱及/或冷卻失配相關聯之應力。
PCB/中介層506為晶粒118提供實體緩衝、支撐及強化劑 以便將晶粒118嵌入包殼128中，尤其在一或多個層之形成期間。亦即，如本文所述耦接至PCB/中介層506之晶粒118提供受保護之積體電路結構，該受保護之積體電路結構在結構上對於與製造包殼128相關聯之應力比單獨晶粒118更具彈性，從而導致底部封裝504之改良的產率及可靠度。
在一實施例中，底部封裝504包括額外焊球512。附接至PCB/中介層506之額外焊球512可用於例如接地/功率及輸入/輸出。
圖6例示出包括頂部封裝102及底部封裝604之封裝佈置600的實施例。晶粒118係經由黏合劑層120附接至基材層116。如所例示，晶粒118係經由線接合製程耦接至基材層116。
焊點凸塊606附接至晶粒118之底側。PCB或中介層608附接至焊球606。在一實施例中，PCB/中介層608可係暴露的或凹入的。在一實施例中，底部封裝604包括額外焊球610。額外焊球610可用於例如接地/功率及輸入/輸出。圖6之實施例可允許額外接腳數，且經由PCB/中介層608為底部封裝604之熱散逸提供路徑。
圖7例示出根據本揭露內容之一實施例的示例性方法700。在702處，方法700包括提供第一封裝，該第一封裝包括基材層，其中基材層包括(i)頂側及(ii)與頂側相對之底側，其中基材層之頂側界定大體上平坦的表面，且其中第一封裝進一步包括晶粒，該晶粒耦接至基材層之底側。
在704處，方法700包括提供第二封裝，該第二封裝具有複數列焊球，該等複數列焊球附接至第二封裝之底表面。
在706處，方法700包括經由第二封裝之複數列焊球將第二封裝附接至第一封裝之大體上平坦的表面。
圖8例示出包括底部封裝804之封裝佈置800。如可看出，底部封裝804係例示出為經佈置成與圖1A及圖1B中所例示之底部封裝104相同或類似。然而，應注意的是，必要時，底部封裝804可佈置成與圖2至圖6中所例示之底部封裝204、304、404、504及604相同或類似。為簡明起見，本文並未進一步論述圖1A及圖1B中所例示及相對於底部封裝104所述之元件。
封裝佈置800包括一或多個封裝的裝置802，該一或多個封 裝的裝置可經由焊球806耦接至底部封裝804之基材層116的頂側117a。封裝的裝置802可任選地包括基材層808，在該基材層上，可經由各種方法附接封裝的裝置802所包括之各種元件及/或晶粒(未例示)，以便創建封裝的裝置802。因此，封裝的裝置802可包括屬於記憶體裝置的一或多個晶粒(未例示)。例如，封裝裝置可類似於圖1至圖6中所例示之頂部封裝102。封裝的裝置802可包括以用於行動裝置的行動雙倍資料速率(mDDR)同步動態隨機存取記憶體(DRAM)之形式的一或多個晶粒(未例示)。行動DDR亦稱為低功率DDR。然而，可利用其他類型之記憶體裝置，包括但不限於雙倍資料速率同步動態隨機存取記憶體(DDR SDRAM)、動態隨機存取記憶體(DRAM)、NOR或NAND快閃記憶體、靜態隨機存取記憶體(SRAM)及其類似者。或者，封裝的裝置802之一或多個晶粒可代表用於行動裝置的特殊應用積體電路(ASIC)。
封裝佈置800進一步包括一或多個被動及/或主動電子元件810。被動及/或主動電子元件810可以任何適合的方式附接至基材116之頂側117a。例如，被動及/或主動電子元件810可經由導線812及焊料814附接至基材116之頂側117a。被動元件810之實例包括但不限於電容器、電阻器、導體、變壓器、轉換器、監察器及天線。被動元件之另一實例包括但不限於網路，例如電阻電容(RC)電路及電感電容(LC)電路。主動元件810之實例包括但不限於半導體晶粒、積體電路、二極體(例如發光二極體(LED)、雷射二極體等)、光電子裝置及電源。來自封裝的裝置802及/或被動/主動電子元件810之信號可經由基材116路由。必要時，封裝佈置800可包括佈置成彼此疊加之多個底部封裝804。多個底部封裝804可佈置成彼此相同或彼此不同。
圖9例示出與圖8之封裝佈置800類似之封裝佈置900的另一實例。再一次，封裝佈置900係例示出為包括底部封裝904，該底部封裝係佈置成與圖1A及圖1B中所例示之底部封裝104相同或類似。必要時，封裝佈置904可佈置成與圖2至圖6中所例示之底部封裝204、304、404、504及604相同或類似。為簡明起見，本文並未進一步論述圖1A及圖1B中所例示及相對於底部封裝104所述之元件。
封裝佈置900包括晶粒902，該晶粒為使用焊球906附接至底部封裝904之基材116的頂側117a之倒裝晶片。一或多個被動及/或主動元件910係附接至底部封裝904之基材116的頂側117a。被動及/或主動電子元件910可以任何適合的方式附接至基材116之頂側117a。例如，被動及/或主動電子元件910可經由導線912及焊料914附接至基材116之頂側117a。被動元件910之實例包括但不限於電容器、電阻器、導體、變壓器、轉換器、監察器及天線。被動元件之另一實例包括但不限於網路，例如電阻電容(RC)電路及電感電容(LC)電路。主動元件910之實例包括但不限於半導體晶粒、積體電路、二極體(例如發光二極體(LED)、雷射二極體等)、光電子裝置及電源。
封裝佈置900亦包括晶粒916，該晶粒附接至底部封裝904之基材116的頂側117a。晶粒912經由線918線接合至底部封裝904之基材116的頂側117a。黏合劑層920可利用來將晶粒916附接至基材116之頂側117a。來自晶粒902、被動/主動電子元件910及/或晶粒916之信號可經由底部封裝904之基材116路由。必要時，封裝佈置900可包括佈置成彼此疊加之多個底部封裝904。多個底部封裝904可佈置成彼此相同或彼此不同。
圖10例示出根據本揭露內容之實施例的示例性方法1000。在1002處，方法1000包括提供第一封裝，該第一封裝包括基材層，其中基材層包括(i)頂側及(ii)與頂側相對之底側，其中基材層之頂側界定大體上平坦的表面，且其中第一封裝進一步包括晶粒，該晶粒耦接至基材層之底側。
在1004處，方法1000包括提供第二封裝，該第二封裝具有複數列焊球，該等複數列焊球附接至第二封裝之底表面。
在1006處，方法1000包括經由第二封裝之複數列焊球將第二封裝附接至第一封裝之大體上平坦的表面。
在1008處，方法1000包括將(i)主動元件或(i)被動元件中之一或兩者中之至少一個附接至第一封裝之基材層的頂側之大體上平坦的表面。
描述可使用基於全景之描述，諸如上/下、上方/下方、及/或，或頂部/底部。此等描述僅用來便於論述，且並非意欲將本文所述之實施例之應用限制於任何特定方向。
出於本揭露內容之目的，用語「A/B」意味A或B。出於本揭露內容之目的，用語「A及/或B」意味「(A)、(B)或(A及B)」。出於本揭露內容之目的，用語「A、B及C中之至少一者」意味「(A)、(B)、(C)、(A及B)、(A及C)、(B及C)或(A、B及C)」。出於本揭露內容之目的，用語「(A)B」意味「(B)或(AB)」，亦即，A係任選的元素。
以最有助於理解所主張之主題之方式依次將各種操作描述為多個分離操作。然而，描述之次序不應被解釋為暗示此等操作必須依賴於次序。具體而言，可並非以呈現之次序執行此等操作。可以不同於所述實施例之次序執行所述操作。可執行各種額外操作，且/或在額外實施例中可省略所述操作。
描述使用用語「在一實施例中」、「在實施例中」或類似語言，該等用語可各自代表相同或不同的實施例中之一或多個。此外，如相對於本揭露內容之實施例所使用之術語「包含」、「包括」、「具有」及其類似者係同義詞。
術語晶片、積體電路、單塊裝置、半導體裝置、晶粒及微電子裝置通常可互換地使用於微電子領域中。本發明適用於上述各者，因為上述各者在本領域中通常係被充分理解的。
本發明之進一步觀點涉及以下條款中之一或多個。
層疊封裝佈置進一步包含第二晶粒，該第二晶粒附接至第一封裝之基材層的頂側之大體上平坦的表面。
第二晶粒經線接合至第一封裝之基材層的頂側之大體上平坦的表面。
第二晶粒係經由倒裝晶片製程附接至第一封裝之基材層的頂側之大體上平坦的表面。
層疊封裝佈置進一步包含黏合劑層，該黏合劑層位於第一晶粒與該基材層之間。黏合劑層將第一晶粒附接至第二封裝之基材層的底側。
層疊封裝佈置進一步包含：接合墊，其位於第一晶粒之底側上；以及基材墊，其位於第二封裝之基材層的底側上。晶粒之接合墊係經由線耦接至基材層之基材墊，以便路由第一晶粒之電氣信號。
複數列焊球包含第一焊球，且層疊封裝佈置進一步包含：第二焊球，其附接至基材層之底側，以將第一晶粒電氣連接至第二封裝之基材層；以及底部填充材料，其位於第二焊球與第二封裝之基材層之間。
複數列焊球包含第一焊球，且層疊封裝佈置進一步包含第二焊球，該等第二焊球附接至第二封裝之底側，且該等第二焊球係位於第二封裝之周邊周圍，以藉此形成球柵陣列。
複數列焊球包含第一焊球。基材層包含第一基材層。第一封裝進一步包含鄰近第一晶粒佈置的第二晶粒。第一晶粒及第二晶粒中每一者係經由第二焊球連接至第一封裝中之第二基材層。
層疊封裝佈置進一步包含熱介面材料，該熱介面材料附接至第一晶粒之底側。
層疊封裝佈置進一步包含導熱材料，該導熱材料附接至熱介面材料。
熱介面材料包含薄膜、油脂組合物或底部填充材料之一。
(i)中介層或(ii)印刷電路板之一附接至晶粒之底側。
複數列焊球包含第一複數列焊球，層疊封裝佈置進一步包含第三封裝，該第三封裝包括第二複數列焊球，第一封裝係經由第一複數列焊球附接至第二封裝之大體上平坦的表面，且第三封裝係經由第二複數列焊球附接至第二封裝之大體上平坦的表面。
複數列焊球包含第一焊球，且層疊封裝佈置進一步包含：第二焊球，其附接至基材層之底側及第一晶粒之頂側；以及複數個矽穿孔，其位於第一晶粒中，其中複數個矽穿孔分別在以下焊球之間延伸：第二焊球中之至少一些；以及複數個第三焊球，其附接至底部封裝之底側。
方法進一步包含將第二晶粒附接至第一封裝之基材層的頂側之大體上平坦的表面。
將第一晶粒附接至基材層之底側包含經由黏合劑層將第一 晶粒附接至基材層之底側。
複數列焊球包含第一焊球，且將第一晶粒附接至基材層之底側包含經由第二焊球將第一晶粒附接至基材層之底側。
方法進一步包含在位於(i)第二焊球之中及(ii)第一晶粒與第一封裝之基材層的底側之間的空間之間提供底部填充材料。
方法進一步包含：在第一晶粒上提供接合墊，其中接合墊係定位在第一晶粒之底側上；在基材層上提供基材墊，其中基材墊係定位在第一封裝之基材層的底側上；以及經由線接合製程將第一晶粒上之接合墊耦接至基材層上之基材墊，以藉此路由第一晶粒之電氣信號。
複數列焊球包含第一焊球，且方法進一步包含將第二焊球附接至第一封裝之底側，其中第二焊球係定位在第一封裝之右側及左側上。
方法進一步包含將熱介面材料附接至第一晶粒之底側。
複數列焊球包含第一焊球，且方法進一步包含在基材層之底側上附接第二焊球；經由第二焊球將第一晶粒附接至基材層之底側；以及在第一晶粒中提供矽穿孔以便將第二焊球連接至第三焊球，該等第三焊球附接至第一封裝之底側。
複數列焊球包含第一焊球，且方法進一步包含：將第二焊球附接至第一晶粒之底側；以及將(i)中介層或(ii)印刷電路板之一耦接至第二焊球。
複數列焊球包含第一複數列焊球，且方法進一步包含：提供第三封裝，其具有第二複數列焊球，該等第二複數列焊球附接至第三封裝之底表面；以及經由第二複數列焊球將第三封裝附接至第一封裝之大體上平坦的表面。
儘管本文已例示出且描述某些實施例，但是在不偏離本揭露內容之範疇的情況下，經計算以達成相同目的之各種替代及/或同等實施例或實行方案可以取代所例示且描述之實施例。本揭露內容意欲涵蓋本文論述之實施例的任何修改或變化。因此，應明顯預期的是，本文所述之實施例僅受申請專利範圍及其同效內容限制。
116‧‧‧基材層
117a‧‧‧頂側
117b‧‧‧底側
118‧‧‧晶粒
120‧‧‧黏合劑層
122(a)‧‧‧接合墊
122(b)‧‧‧接合墊
124(a)‧‧‧基材墊
124(b)‧‧‧基材墊
126(a)‧‧‧接合線
126(b)‧‧‧接合線
128‧‧‧包殼
129‧‧‧焊球
130‧‧‧焊球
131‧‧‧開口
800‧‧‧封裝佈置
802‧‧‧裝置
804‧‧‧底部封裝
806‧‧‧焊球
808‧‧‧基材層
810‧‧‧被動及/或主動電子元件/被動元件/主動元件
812‧‧‧導線
814‧‧‧焊料

Claims (28)

  1. 一種層疊封裝佈置，其包含：一第一封裝，其包括一基材層，其包括(i)一頂側及(ii)與該頂側相對之一底側，其中該基材層之該頂側界定一大體上平坦的表面，以及一第一晶粒，其耦接至該基材層之該底側；一第二封裝，其包括複數列焊球；以及(i)一主動元件或(ii)一被動元件中之一或兩者中之至少一個，其中該第二封裝係經由該等複數列焊球附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面，且其中(i)一主動元件或(ii)一被動元件中之一或兩者中之該至少一個附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  2. 如申請專利範圍第1項之層疊封裝佈置，其進一步包含：一第二晶粒，其附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  3. 如申請專利範圍第2項之層疊封裝佈置，其中：該第二晶粒經線接合至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  4. 如申請專利範圍第2項之層疊封裝佈置，其中：該第二晶粒係經由一倒裝晶片製程附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  5. 如申請專利範圍第1項之層疊封裝佈置，其進一步包含：一黏合劑層，其位於該第一晶粒與該基材層之間，其中該黏合劑層將該第一晶粒附接至該第二封裝之該基材層的該底側。
  6. 如申請專利範圍第1項之層疊封裝佈置，其進一步包含：一接合墊，其位於該第一晶粒之該底側上；以及一基材墊，其位於該第二封裝之該基材層的該底側上，其中該晶粒之該接合墊係經由一線耦接至該基材層之該基材墊，以便路由傳遞該第一晶粒之電氣信號。
  7. 如申請專利範圍第1項之層疊封裝佈置，其中該等複數列焊球包含第一焊球，且該層疊封裝佈置進一步包含：第二焊球，其附接至該基材層之該底側，以將該第一晶粒電氣連接至該第二封裝之該基材層；以及一底部填充材料，其位於該等第二焊球與該第二封裝之該基材層之間。
  8. 如申請專利範圍第1項之層疊封裝佈置，其中該等複數列焊球包含第一焊球，且該層疊封裝佈置進一步包含：第二焊球，其附接至該第二封裝之一底側；且該等第二焊球係位於該第二封裝之一周邊周圍，以藉此形成一球柵陣列。
  9. 如申請專利範圍第1項之層疊封裝佈置，其中：該等複數列焊球包含第一焊球；該基材層包含一第一基材層；該第一封裝進一步包含鄰近該第一晶粒佈置的一第二晶粒；且該第一晶粒及該第二晶粒中每一者係經由第二焊球連接至該第一封裝中之一第二基材層。
  10. 如申請專利範圍第1項之層疊封裝佈置，其進一步包含：熱介面材料，其附接至該第一晶粒之一底側。
  11. 如申請專利範圍第10項之層疊封裝佈置，其進一步包含：導熱材料，其附接至該熱介面材料。
  12. 如申請專利範圍第11項之層疊封裝佈置，其中該熱介面材料包含一薄膜、一油脂組合物或一底部填充材料之一。
  13. 如申請專利範圍第1項之層疊封裝佈置，其進一步包含：(i)一中介層或(ii)一印刷電路板之一，其附接至該晶粒之一底側。
  14. 如申請專利範圍第1項之層疊封裝佈置，其中：該等複數列焊球包含第一複數列焊球；該層疊封裝佈置進一步包含一第三封裝，該第三封裝包括第二複數列焊球；該第一封裝係經由該等第一複數列焊球附接至該第二封裝之該大體上平坦的表面；且 該第三封裝係經由該等第二複數列焊球附接至該第二封裝之該大體上平坦的表面。
  15. 如申請專利範圍第1項之層疊封裝佈置，其中該等複數列焊球包含第一焊球，且該層疊封裝佈置進一步包含：第二焊球，其附接至該基材層之該底側及該第一晶粒之一頂側；以及複數個矽穿孔，其位於該第一晶粒中，其中該等複數個矽穿孔分別在以下焊球之間延伸：該等第二焊球中之至少一些，以及複數個第三焊球，其附接至該底部封裝之一底側。
  16. 一種方法，其包含：提供一第一封裝，其包括一基材層，其中該基材層包括(i)一頂側及(ii)與該頂側相對之一底側，其中該基材層之該頂側界定一大體上平坦的表面，且其中該第一封裝進一步包括一第一晶粒，該第一晶粒耦接至該基材層之該底側；提供一第二封裝，其具有複數列焊球，該等複數列焊球附接至該第二封裝之一底表面；經由該第二封裝之該等複數列焊球將該第二封裝附接至該第一封裝之該大體上平坦的表面；以及將(i)一主動元件或(ii)一被動元件中之一或兩者中之至少一個附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  17. 如申請專利範圍第16項之方法，其進一步包含：將一第二晶粒附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  18. 如申請專利範圍第17項之方法，其中該第二晶粒經線接合至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  19. 如申請專利範圍第17項之方法，其中該第二晶粒係經由一倒裝晶片製程附接至該第一封裝之該基材層的該頂側之該大體上平坦的表面。
  20. 如申請專利範圍第16項之方法，其中將該第一晶粒附接至該基材層之該底側包含經由一黏合劑層將該第一晶粒附接至該基材層之該底側。
  21. 如申請專利範圍第16項之方法，其中該等複數列焊球包含第一焊球， 且將該第一晶粒附接至該基材層之該底側包含經由第二焊球將該第一晶粒附接至該基材層之該底側。
  22. 如申請專利範圍第21項之方法，其進一步包含：在位於(i)該等第二焊球之中及(ii)該第一晶粒與該第一封裝之該基材層的該底側之間的空間之間提供底部填充材料。
  23. 如申請專利範圍第16項之方法，其進一步包含：在該第一晶粒上提供一接合墊，其中該接合墊係定位在該第一晶粒之一底側上；在該基材層上提供一基材墊，其中該基材墊係定位在該第一封裝之該基材層的該底側上；以及經由一線接合製程將該第一晶粒上之該接合墊耦接至該基材層上之該基材墊，以藉此路由該第一晶粒之電氣信號。
  24. 如申請專利範圍第16項之方法，其中該等複數列焊球包含第一焊球，且該方法進一步包含：將第二焊球附接至該第一封裝之一底側，其中該等第二焊球係定位在該第一封裝之一右側及一左側上。
  25. 如申請專利範圍第16項之方法，其進一步包含：將一熱介面材料附接至該第一晶粒之一底側。
  26. 如申請專利範圍第16項之方法，其中該等複數列焊球包含第一焊球，且該方法進一步包含：在該基材層之該底側上附接第二焊球；經由該等第二焊球將該第一晶粒附接至該基材層之該底側；以及在該第一晶粒中提供矽穿孔以便將該等第二焊球連接至第三焊球，該等第三焊球附接至該第一封裝之一底側。
  27. 如申請專利範圍第16項之方法，其中該等複數列焊球包含第一焊球，且該方法進一步包含：將第二焊球附接至該第一晶粒之一底側；以及將(i)一中介層或(ii)一印刷電路板之一耦接至該等第二焊球。
  28. 如申請專利範圍第16項之方法，其中：該等複數列焊球包含第一複數列焊球；且 該方法進一步包含提供一第三封裝，其具有第二複數列焊球，該等第二複數列焊球附接至該第三封裝之一底表面，以及經由該等第二複數列焊球將該第三封裝附接至該第一封裝之該大體上平坦的表面。
TW103104424A 2013-02-11 2014-02-11 層疊封裝結構 TW201442203A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361763285P 2013-02-11 2013-02-11
US14/176,695 US20140151880A1 (en) 2011-08-19 2014-02-10 Package-on-package structures

Publications (1)

Publication Number Publication Date
TW201442203A true TW201442203A (zh) 2014-11-01

Family

ID=51625003

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103104424A TW201442203A (zh) 2013-02-11 2014-02-11 層疊封裝結構

Country Status (4)

Country Link
KR (1) KR102170197B1 (zh)
CN (1) CN105340078A (zh)
TW (1) TW201442203A (zh)
WO (1) WO2014158388A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI580139B (zh) * 2015-03-31 2017-04-21 Hou Chieh Lee 用於雷射二極體之封裝結構
TWI602269B (zh) * 2016-06-08 2017-10-11 力成科技股份有限公司 柱頂互連之封裝堆疊方法與構造
TWI678772B (zh) * 2017-04-28 2019-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI732548B (zh) * 2020-05-12 2021-07-01 宇瞻科技股份有限公司 封裝結構
US11610844B2 (en) 2017-10-11 2023-03-21 Octavo Systems Llc High performance module for SiP

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3310140B1 (en) 2016-10-14 2021-07-14 Vitesco Technologies GmbH Mounting assembly with a heatsink
US10916488B2 (en) * 2018-06-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having thermal conductive pattern surrounding the semiconductor die
KR20230026763A (ko) * 2021-08-18 2023-02-27 삼성전자주식회사 칩 패키지 구조 및 이를 포함하는 전자 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424034B1 (en) * 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
US6734539B2 (en) * 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
SG95637A1 (en) * 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US20070241441A1 (en) * 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
CN101958261B (zh) * 2009-08-25 2012-09-05 日月光半导体制造股份有限公司 半导体工艺及可堆栈式半导体封装结构
US20120126396A1 (en) * 2010-11-19 2012-05-24 Broadcom Corporation Die down device with thermal connector

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI580139B (zh) * 2015-03-31 2017-04-21 Hou Chieh Lee 用於雷射二極體之封裝結構
TWI602269B (zh) * 2016-06-08 2017-10-11 力成科技股份有限公司 柱頂互連之封裝堆疊方法與構造
TWI678772B (zh) * 2017-04-28 2019-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11610844B2 (en) 2017-10-11 2023-03-21 Octavo Systems Llc High performance module for SiP
TWI732548B (zh) * 2020-05-12 2021-07-01 宇瞻科技股份有限公司 封裝結構

Also Published As

Publication number Publication date
KR20150116844A (ko) 2015-10-16
WO2014158388A1 (en) 2014-10-02
CN105340078A (zh) 2016-02-17
KR102170197B1 (ko) 2020-10-27

Similar Documents

Publication Publication Date Title
US9666571B2 (en) Package-on-package structures
US11594462B2 (en) Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US20140151880A1 (en) Package-on-package structures
KR101639989B1 (ko) 윈도우 인터포저를 갖는 3d 집적 회로 패키지
US10847435B2 (en) Semiconductor package structure and fabrication method thereof
KR102170197B1 (ko) 패키지 온 패키지 구조들
US9806017B2 (en) Flip-chip, face-up and face-down centerbond memory wirebond assemblies
KR101830904B1 (ko) 리세스된 반도체 기판
CN102414815B (zh) 具有散热器的多管芯半导体封装
US7928590B2 (en) Integrated circuit package with a heat dissipation device
US20120299173A1 (en) Thermally Enhanced Stacked Package and Method
US10269676B2 (en) Thermally enhanced package-on-package (PoP)
US11671010B2 (en) Power delivery for multi-chip-package using in-package voltage regulator
KR101111423B1 (ko) 열방출 수단을 갖는 적층 칩 반도체 패키지
KR101056750B1 (ko) Ｔｓｖ를 이용한 적층 칩 패키지
KR100885918B1 (ko) 반도체 디바이스 스택 패키지, 이를 이용한 전기장치 및 그패키지의 제조방법
US20120168936A1 (en) Multi-chip stack package structure and fabrication method thereof
US20230099787A1 (en) Semiconductor package and method of fabricating the same
KR100855887B1 (ko) 스택형 반도체 패키지 및 그 스택 방법
WO2014171403A1 (ja) 半導体装置
TWI297203B (en) Microelectronic package