TWI297203B - Microelectronic package - Google Patents
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- TWI297203B TWI297203B TW92117870A TW92117870A TWI297203B TW I297203 B TWI297203 B TW I297203B TW 92117870 A TW92117870 A TW 92117870A TW 92117870 A TW92117870 A TW 92117870A TW I297203 B TWI297203 B TW I297203B
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- package substrate
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
1297203 皇號 92117870 五、發明說明（1) 發明所屬之技術領域 —日— 修正 本發明係提供一種微電子封裝構件（micr〇— electronic package)，尤指一種半導體封裝構件，且 RC被動兀件置於晶片之下方’藉此節省封基 積、， 並提昇電性增益效果。 衣土极囬積 先前技術 士丰ίΓΐ代，隨著資訊家電（IA)產品以及通訊產品（例 如手持式產品所需之SRAM、DRAM、Flash、1C、 Re^ulator IC等）的蓬勃發展，資訊傳輸容量大為擴增， 汛號傳輸的速度要求也大幅提高，同時在多功能手持式 ，子產品的驅動下，半導體製程發展無可避免朝高容 里 乍線1的咼密度化、高頻、低耗能、多功能整合方 向演進。在1C封裝技術方面，為配合高1/ 〇數、高散"熱以 及封裝尺寸縮小化的高標要求下，使得晶片級封裝 (Chip Scale Package， CSP)、覆晶（FlipChiprFC)等 $階封裝型態需求持續升高，一躍而成為目前封裝之主 流。在封裝尺寸小型化的要求下，封裝腳數達到3 〇 〇 P i n 以上的封裝型態，除了上述晶片級封裝（CSP)、覆晶（FC) 以外，還包括有球柵陣列封裝（ball grid array，BGA) 以及軟片自動接合（tape automatic b〇nding，TAB)等。 請參閱圖一，圖一為習知半導體封裝構件1297203 Emperor 92117870 V. INSTRUCTION DESCRIPTION (1) Technical Field of the Invention - Day - Correction The present invention provides a microelectronic package, especially a semiconductor package member, and an RC passive device Below the wafer 'to save the seal volume, and improve the electrical gain effect. The industry has been back-to-back, and the information technology (IA) products and communication products (such as SRAM, DRAM, Flash, 1C, Re^ulator IC, etc. required for handheld products) are booming. The transmission capacity is greatly expanded, and the speed requirement for the transmission of the nickname is also greatly improved. At the same time, under the driving of the multi-function handheld and sub-products, the development of the semiconductor process is inevitable to increase the density and high frequency of the 1 line 1 , low energy consumption, multi-functional integration direction evolution. In terms of 1C packaging technology, in order to meet the high standard requirements of high 1/〇, high dispersion "heat and package size reduction, the chip scale package (CSP), flip chip (FlipChiprFC), etc. The demand for package types continues to rise, and it has become the mainstream of current packaging. In the package size miniaturization requirements, the package type of the package pin number is more than 3 〇〇P in, in addition to the above wafer level package (CSP), flip chip (FC), also includes a ball grid array package (ball grid Array, BGA) and tape automatic b〇nding (TAB). Please refer to FIG. 1 , which is a conventional semiconductor package component.
第8頁 1297203 案號92117870 年 月 a 伙t . … 一... --一…-------------------------------------------------------------------1 ....... 一―修止 五、發明說明（2) . ——— 一 (semiconductoi: package)l之剖面示意圖。如圖一所 示，習知半導體封裝構件1包括有一封裂基板1〇，其具有 一上表面或主動表面（act ive surf ace) 2以及一下表面 3。封裝基板1 0可以為一多晶片模組（m u 1i — c乜i p module，MCM)基板，亦即可在同一基板上同時安裝多個 晶片。晶片1 0 1以及晶片1 〇 2係以覆晶方式藉由焊料凸塊 (solder bump) 12對準固定在封裝基板1〇的上表面2的預 疋位置上。晶片1 0 1以及晶片1 〇 2與封裝基板1〇之間縫隙 則以底膠（u n d e r f i 1 1 ) 1 3填滿並加以固化，以消除烊料凸 塊1 2連接處之之應力，並強化封裝基板· 1 〇與晶片1 〇 1、 1 0 2之間的結合。習知半導體封裝構件丨另包含有RC被動 元件(passive component) 11，例如電阻或電容元件，其 係以表面黏合技術（surf ace mount irig technique， 對準固定在封裝基板1 0的上表面2的預定位置上。在封裝 基板1 0的下表面3，最後則植以球柵陣列封裝（BGA)錫球 (solder ball) 14，半導體封裝構件！即可藉由BGA錫球14 與一印刷電路板（未顯示）構成電氣連結。 然而’上述習知半導體封裝構件1由於採被動元件]丄 與晶片101、102安置於封裝基板10之同一表面上，亦即 上表面2，而被動元件1 1佔據不少封裝基板丨〇的面積，導 致整體封裝尺寸以及成本的增加。此外，由於習知採被 動元件11與晶片101、102安置於封裝基板10之同一表面 上之設計，使得R C被動元件11距離晶片1 〇 1、1 〇 2較遠， 電性增益效果較差。 1297203 修正 --------------------------------------------------------------------------一 ··..····_ -一葷號92117870 年 日 i, ' ---------------------------------------------------------------------- x 、發明說明（3) · 發明内容 子封，2杜本發明之主要目的在於提供一種改良之微電 ^件’其具有RC被動元件配置於IC晶片或晶方 之間1電1·生方值…以^短R*動元件與IC晶片或晶方（die) 間的电性傳輸距離，藉此提昇晶片之電性增益效果。Page 8 1297201 Case No. 92117870 Month a gang t. ... one... -- one...---------------------------- ---------------------------------------1 ....... End five, invention description (2) . --- a schematic diagram of a (semiconductoi: package) l. As shown in Fig. 1, the conventional semiconductor package member 1 includes a split substrate 1 having an upper surface or an active surface surf 2 and a lower surface 3. The package substrate 10 may be a multi-chip module (m u 1i - c乜i p module, MCM) substrate, or a plurality of wafers may be simultaneously mounted on the same substrate. The wafer 1 0 1 and the wafer 1 〇 2 are fixed in a flip-chip manner by a solder bump 12 at a pre-position of the upper surface 2 of the package substrate 1 . The gap between the wafer 1 0 1 and the wafer 1 〇 2 and the package substrate 1 is filled with a primer (underfi 1 1 ) 13 and cured to eliminate the stress at the junction of the bumps 12 and strengthen The package substrate · 1 〇 is bonded to the wafer 1 〇 1, 1 0 2 . The conventional semiconductor package member further includes an RC passive component 11, such as a resistive or capacitive component, which is affixed to the upper surface 2 of the package substrate 10 by a surf ace mount irig technique. At a predetermined position, on the lower surface 3 of the package substrate 10, finally, a ball grid array package (BGA) solder ball 14 is mounted, and the semiconductor package member can be used by the BGA solder ball 14 and a printed circuit board. (not shown) constitutes an electrical connection. However, the above-mentioned conventional semiconductor package member 1 is disposed on the same surface of the package substrate 10 as the upper surface 2, and the passive element 1 1 is occupied by the passive element 丄 and the wafers 101, 102. The area of the package substrate is increased, resulting in an increase in the overall package size and cost. Further, since the design of the passive component 11 and the wafers 101, 102 are disposed on the same surface of the package substrate 10, the distance of the RC passive component 11 is The wafer 1 〇1, 1 〇2 is far away, and the electrical gain effect is poor. 1297203 Correction ------------------------------- -------------------------------------------One ········_ - One nickname 92117870 Year i, ' ------------------------------- --------------------------------------- x , invention description (3) · invention content The main purpose of the invention is to provide an improved micro-electric component that has an RC passive component disposed between the IC chip or the crystal. 1 electric 1 · raw value ... to short R * dynamic component and IC The electrical transmission distance between the wafer or the die, thereby enhancing the electrical gain effect of the wafer.
椹彼本t明之另一目的在於提供一種改良之微電子封裝 =件，/、具有RC被動元件與1C晶片或晶方分別配置在封 衣基板之相對應面上，以縮小封裝構件之整體尺以及 所需基板面積，降低生產成本。 本發明之又一目的在於提供一種改良之BGA封裝構 件’其具有RC被動元件配置在封裝基板下側之BGA錫球間 之封裝基板下表面上，以縮小封裝構件之整體尺寸以及 所需基板面積，降低生產成本。： 為達上述目的，本發明較佳實施例揭露一種微電子 封裝構件，包含有一封裝基板，其具有一上表面以及一 下表面；至少一晶片設於該封裝基板之上表面；複數個 球栅陣列（b a 1 1 g r i d a r r a y )錫球（s ο 1 d e r b a 1 1 )設於該 下表面；以及至少一 RC被動元件設於該晶片之正下方。 該晶片可以覆晶方式藉由焊料凸塊（solder bump)對準固 定於該封裝基板上表面之預定位置上。該RC被動元件係Another object of the invention is to provide an improved microelectronic package=piece, with RC passive components and 1C wafers or crystals respectively disposed on the corresponding faces of the sealing substrate to reduce the overall dimensions of the package members. And the required substrate area, reducing production costs. It is still another object of the present invention to provide an improved BGA package member having an RC passive component disposed on a lower surface of a package substrate between BGA solder balls on a lower side of a package substrate to reduce the overall size of the package member and a desired substrate area. ,reduce manufacturing cost. In order to achieve the above objective, a preferred embodiment of the present invention discloses a microelectronic package component including a package substrate having an upper surface and a lower surface; at least one wafer disposed on an upper surface of the package substrate; and a plurality of ball grid arrays (ba 1 1 gridarray) a solder ball (s ο 1 derba 1 1 ) is disposed on the lower surface; and at least one RC passive component is disposed directly under the wafer. The wafer can be flip-chip mounted by a solder bump to a predetermined position fixed to the upper surface of the package substrate. The RC passive component system
第10頁 1297203 i —室處」2117870 I五、發明說明（4) _— 一―^ 設於該複數個球柵陣列錫球 調整式泛用型電阻，其上具 板之該下表面上具有兩條金 塊中之兩凸塊，且該兩條金 式泛用型電阻之電阻值。 為了使貴審查委員能 及技術内容，請參閱以下有 圖。然而所附圖式僅供參考 本發明加以限制者。 實施方式 土a 之間。該RC被動元件為一可 有複數個凸塊，且該封裝基 屬導線相對應於該複數個凸 屬導線之距離決定該可調整 更近一步了解本發明之特徵 關本發明之詳細說明與附 與輔助說明用，並非用來對 凊麥閱圖二，圖二為依據本發明第一較佳實施你丨 覆晶BGA封裝構件4之剖面示意圖。如圖二所示，、覆曰_ ^ =構件4包括有一封裝基板.4〇，其具有—上表面覆或曰曰主^ t Ϊ δυΓί_)5以及一下表面6。封裝基板40可 以為一夕層電路板或一多晶片模組（mul ti_ch mc^ule，MCM)基板。一般，封裝基板4〇的成分包 i temperature，high Tg)的塑膠基板（〇rganic substrate)有機材料，例如 fr—4.8、 fr—5、聚丁一 (BT)樹脂、Driclad、Hitachi 679F等塑膠基板材一粗晞 不限於此。舉例而言，封震基板4〇可以為一兩居材姑斗’但 含有兩銅導線層分別設於封裝基板4〇之上表面反，包 有咼轉化溫度（high glass transfQ;rmatiQn '、 1297203 月 修正 曰 一 一———_________________92117870 年 五、發明說明（5) Ξ 6上//^及數個電路導通件（via)設於封裂基板40内 ，，用曰來，連接上下兩銅導線層。晶片4〇1係以覆晶方式 藉由知料凸塊（s〇lder bump)42對卑固定在封裝基板4〇的 上表面5的預定位置，例如相對應之凸塊焊墊（s〇 bump pad)上。晶片401與封裝基板4〇之間縫隙則以底膠 (underf 1 1 1 )43填滿並加以固化，以強化封裝基板4〇與晶 片4 0 1之間的結合。底膠4 3可以利用流動性或非流動性之 填膠方式進行。熟習該項技藝者應瞭解在某些情況下， 底膠4 3亦可以省略不用，並非必須要件。 覆晶BGA封裝構件4另包含有rC被動元件（passive component )4卜例如電阻或電容元件，其係以表面黏合 技術（surf ace mount ing technique，SMT)對準固定在封 裝基板4 0的下表面6的預定位置上，較佳位置在晶片4 〇 i 之正下方。在封I基板4〇的下表面6，最後則植以球柵·陣 列封裝（BGA)錫球（solder bal 1 )44，覆晶BGA封裝構件4 即可藉由BGA錫球44與一印刷電路板（未顧示）樣成電氣連 結0 請參閱圖三，圖三為圖二覆晶BGA封裝構件4之下表 面6之平面示意圖。依據本發明之第一較佳實施例，複數 個錫球4 4係設置在封裝基板4 0下表面6的中央部份，用來 增加覆晶BGA封裝構件4的散熱效果，將1C晶片401所產生 的高溫經由錫球4 4傳導至印刷電路板上。I C晶片4 0 1與印 刷電路板之電性傳輸則是經由錫球46進行。RC被動元件 1297203 - ---------------------•處〜lj 7870 年 月 日 修正 五、發明說明（6) . — 一 ——— 一―—————:—— ^1丄例如電阻或電容元件，係以表面黏合技術（SMT)對準 1疋在兩散熱錫球44之間封裝基板4〇下表面6的預定位置 請參閱^四，圖四為圖二覆晶BGA封裝構件4之下表 6之平面不意圖。依據本發明.之第二較佳實施例，複數 、錫球4 4係设置在封裝基板4 〇下表面6的中央部份，用來 ^ 士覆晶BGA封裝構件4的散熱效果，將IC晶片4〇1所產生 2二溫經由錫球44傳導至印刷電路板上。1(：晶片4〇1與印 i ί路板之電性傳輸則是經由錫球46進行。散熱錫球44 % =以陣列方式排列於封裝基板4〇下表面6的中央部份， 取ς 了安置RC被動元件41，可在形成散熱錫球44陣列時 :2或$數Τ錫球44。RC被動元件41/ :Γ兀件，可以表面黏合技術（SMT)對準固定在取消之散 熱錫球44位置上。 隹取兩之放 =線（Wire bonding)封裝。請參閱圖五，圖五為依 =本奄明第二較佳實施例之打線封裝構件7之剖面示“音 圖。如圖五所示，打線封裝構件7包右宜心 其具有一上表面5以及一下"^件7包括有一封裝基板4〇， 多声兩故描弋各日表6。封裝基板40可以為一 夕層私路板或一夕日日片拉組（MCM)基板。一射壯其^ 料，例如FR-4.8、FR-5、τ的塑膠基板有機木Page 10 1297201 i - room" 2117870 I 5, invention description (4) _ - a - ^ is set in the plurality of ball grid array solder ball adjustment type general-purpose resistor, which has a lower surface on the upper plate Two of the two gold nuggets, and the resistance values of the two gold-type general-purpose resistors. In order to enable your review board to have technical content, please refer to the following figure. However, the drawings are for reference only, and the invention is limited. Embodiments between soil a. The RC passive component is a plurality of bumps, and the distance of the package base conductor corresponding to the plurality of convex conductors is determined. The adjustment is further understood to understand the features of the present invention. For the purpose of explanation, it is not intended to refer to Fig. 2 for the buckwheat, and Fig. 2 is a schematic cross-sectional view of the BGA package member 4 according to the first preferred embodiment of the present invention. As shown in FIG. 2, the cover member _ ^ = member 4 includes a package substrate .4 〇 having an upper surface cover or a top surface ^ υΓ υΓ υΓ _ _ 5 and a lower surface 6. The package substrate 40 can be an integrated circuit board or a multi-chip module (MCM) substrate. Generally, the package substrate 4 is made of a plastic substrate of a temperature, high Tg), such as fr-4.8, fr-5, BT resin, Driclad, Hitachi 679F, etc. A rough plate is not limited to this. For example, the sealing substrate 4 can be one or two materials, but the two copper wires are respectively disposed on the upper surface of the package substrate 4, and have a transformation temperature (high glass transfQ; rmatiQn ', 1297203曰月曰一————_________________92117870 第五, invention description (5) Ξ 6 on / / ^ and several circuit conduction (via) is set in the cracked substrate 40, with 曰 to connect the upper and lower copper wire The wafer 4〇1 is fixed in a predetermined position on the upper surface 5 of the package substrate 4 by means of a bump bump 42 in a flip chip manner, for example, a corresponding bump pad (s The gap between the wafer 401 and the package substrate 4 is filled with a primer (underf 1 1 1 ) 43 and cured to strengthen the bond between the package substrate 4 and the wafer 410. The glue 4 3 can be carried out by means of a fluid or non-flowable filling method. Those skilled in the art should understand that in some cases, the primer 4 can also be omitted, not necessarily required. The flip chip BGA package member 4 Contains rC passive component 4 such as resistance or electricity The component is fixed at a predetermined position on the lower surface 6 of the package substrate 40 by a surf ace mount ing technique (SMT), preferably at a position directly below the wafer 4 〇i. 4 〇 lower surface 6, and finally implanted with ball grid array package (BGA) solder ball 1 (solder bal 1 ) 44, flip chip BGA package member 4 can be used BGA solder ball 44 and a printed circuit board (disregarded Referring to FIG. 3, FIG. 3 is a plan view showing the lower surface 6 of the flip-chip BGA package member 4. According to the first preferred embodiment of the present invention, a plurality of solder balls are arranged. In the central portion of the lower surface 6 of the package substrate 40, the heat dissipation effect of the flip-chip BGA package member 4 is increased, and the high temperature generated by the 1C wafer 401 is conducted to the printed circuit board via the solder ball 44. The IC chip 40 1 and the electrical transmission of the printed circuit board is carried out via the solder ball 46. RC passive components 1297203 - --------------------------- ~ lj 7870 Japanese Revision 5, Invention Description (6) . — ———————————————————————————————————————————————————————————————— Refer to ^4 for the predetermined position of the lower surface 6 of the package substrate 4 between the two heat-dissipating solder balls 44 by surface adhesion technology (SMT). Figure 4 is the top of the flip-chip BGA package member 4. According to a second preferred embodiment of the present invention, a plurality of solder balls 44 are disposed in a central portion of the lower surface 6 of the package substrate 4 for use in dissipating heat dissipation of the BGA package member 4. The two temperatures generated by the IC chip 4〇1 are conducted to the printed circuit board via the solder balls 44. 1 (: The electrical transmission of the wafer 4〇1 and the printed board is performed via the solder ball 46. The heat-dissipating solder balls 44% are arranged in an array on the central portion of the lower surface 6 of the package substrate 4, taking ς The RC passive component 41 can be placed in the form of an array of thermal solder balls 44: 2 or $ Τ tin balls 44. RC passive components 41 / : Γ兀, can be surface-bonded (SMT) aligned to fix the heat dissipation The solder ball 44 is positioned. Referring to FIG. 5, FIG. 5 is a cross-sectional view of the wire bonding package member 7 according to the second preferred embodiment of the present invention. As shown in FIG. 5, the wire bonding package 7 is provided with an upper surface 5 and a lower portion. The device 7 includes a package substrate 4, which is audible and readable. The package substrate 40 can be One-night private board or overnight MK substrate. A plastic substrate such as FR-4.8, FR-5, τ
Hitachi 679F等塑膠基板材料，作上脂、Driclad， 竹村但不限於此。舉例而Plastic substrate materials such as Hitachi 679F are used for grease, Driclad, and bamboo villages, but are not limited to this. For example
1297203 案號 92117870 曰 修正 五、發明說明（7) 舌’封裝基板4 0可以為一兩層板，包含有兩銅導線層分 別設於封裝基板4 0之上表面5以及下表面6上，以及複數 個電路導通件（V i a )設於封裝基板4 0内部，用來電連接上 下兩銅導線層。晶片40 1係以表面黏合技術（SMT)固定在 封裝基板4 0的上表面5的預定位置，並藉由打金線7 〇 2與 封t基板40電連接。晶片401最後以樹脂（r g s i η ) 7 0 1封 固0 打線封裝構件7另包含有R C被動元件4 1，例如電阻或 電容元件，其係以表面黏合技術（S Μ τ)對準固定在封裝基 板40的下表面6的預定位置上。在封裝基板4〇的下表面 6，最後則植以球柵陣列封裝（BGA)錫球44，覆晶上以封裝 構件卿可藉由BGA錫球44與一印刷電路板·(未顯示)構成 電氣連結。 請參閱圖六，圖六為依據本發明第四較佳實施例之 覆晶BGA封裝構件8之剖面示意圖。如圖六所示，覆晶BGA 封裝構件8包括有一封裝基板·4〇，其具有一上表面5以及 一下表面6。封裝基板40為一多晶片模組（multi 一chip module ’ MCM)基板。晶片401及40 2係以覆晶方式藉由焊 料凸塊（solder bump) 42對準固定在封裝基板40的上表面 5的預定位置，例如相對應之&塊焊墊（s〇lder bump pad)上。晶片401及40 2與封裝基板40之間縫隙則以底膠 (underf 1 1 1 )43填滿並加以固化，以強化封裝基板4〇與晶 片4 0 1及4 0 2之間的結合。底膠4 3可以利用流動性或非流1297203 Ref. 92117870 曰Revision 5, invention description (7) The tongue 'package substrate 40 can be a two-layer board, and two copper wire layers are respectively disposed on the upper surface 5 and the lower surface 6 of the package substrate 40, and A plurality of circuit conducting members (V ia ) are disposed inside the package substrate 40 for electrically connecting the upper and lower copper wire layers. The wafer 40 1 is fixed to a predetermined position of the upper surface 5 of the package substrate 40 by a surface bonding technique (SMT), and is electrically connected to the package t substrate 40 by a gold wire 7 〇 2 . The wafer 401 is finally sealed with a resin (rgsi η ) 701. The wire-wound package member 7 further includes an RC passive component 4 1, such as a resistive or capacitive component, which is fixed in the package by surface bonding technology (S Μ τ). The predetermined position of the lower surface 6 of the substrate 40. On the lower surface 6 of the package substrate 4, finally, a ball grid array package (BGA) solder ball 44 is implanted, and the package member is formed by the BGA solder ball 44 and a printed circuit board (not shown). Electrical connection. Referring to Figure 6, Figure 6 is a cross-sectional view of a flip-chip BGA package member 8 in accordance with a fourth preferred embodiment of the present invention. As shown in Fig. 6, the flip chip BGA package member 8 includes a package substrate 4 having an upper surface 5 and a lower surface 6. The package substrate 40 is a multi-chip module (MCM) substrate. The wafers 401 and 40 2 are fixed in a predetermined position on the upper surface 5 of the package substrate 40 by solder bumps 42 in a flip chip manner, for example, corresponding & pad bump pads )on. The gap between the wafers 401 and 40 2 and the package substrate 40 is filled with a primer (underf 1 1 1 ) 43 and cured to strengthen the bond between the package substrate 4 and the wafers 40 1 and 40 2 . The primer 4 3 can utilize fluidity or non-flow
1297203 _ 案號 92117870 ------------------ ........... ....-------------------------------------------- ’ I V/ .~ ------------- 五、發明說明（8) ―年 月 曰 修正 省些情1297203 _ Case No. 92117870 ------------------ ........... ....------------ -------------------------------- ' IV/ .~ ------------- V. Description of the invention (8)
復晶BGA封裝構件8另包含有rC被動元件41&及41b， ，如電阻或電容70件，其係以表面黏合技術（SMT)對準固 定在封裝基板40的下表面6的預定位置上，較佳位置在晶 片4 0 1及4 0 2之正下方。在封裝基板4 〇的下表面6，最後則 植以球桃陣列封I ( BGA )錫球（so 1 der ba 1 1 ) 44，覆晶BGA 封裝構件8即可藉由BGA錫球44與一印刷電路板（未顯示） 構成電氣連結。 · 舜曰清參閱圖七’圖七為依據本發明第五較佳賁施例之 覆晶BGA封裝構件9之剖面示意圖。如圖七所示，覆晶bga 封瓜構件9包括有一封裳基板4〇，其具有一上表面5以及 一下表面6。封裝基板4〇為一多晶片模組（.multi_chip ^odule ’ MCM)基板，其具有一凹穴9〇1形成於下表面6。 晶片401及40 2係以覆晶方式藉由焊料凸塊（s〇l der bump) 4 2對準固定在封裝基板4〇的上表面5的預定位置，例如相 對f之凸塊焊墊（solder bump pad)上。晶片401及4 0 2與 封裝基板40之間縫隙則以底膠（underf丨丨丨）43填滿並加以 固1 ’以強化封裝基板4 〇與晶片4 0 1及4 0 2之間的結合。 f f 4 3可以利用流動性或非流動性之填膠方式進行。熟 習該項技藝者應瞭解在某些情況下，底膠43亦可以省略 不用，並非必須要件。The polycrystalline BGA package member 8 further includes rC passive components 41 & and 41b, such as resistors or capacitors 70, which are fixed in a predetermined position on the lower surface 6 of the package substrate 40 by surface bonding technology (SMT). The preferred position is directly below the wafers 40 1 and 4 0 2 . On the lower surface 6 of the package substrate 4, finally, a spherical peach array I (BGA) solder ball (so 1 der ba 1 1 ) 44 is implanted, and the flip-chip BGA package member 8 can be used by the BGA solder ball 44 and a A printed circuit board (not shown) forms an electrical connection. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view of a flip-chip BGA package member 9 in accordance with a fifth preferred embodiment of the present invention. As shown in Fig. 7, the flip-chip bga sealing member 9 includes a skirting substrate 4 having an upper surface 5 and a lower surface 6. The package substrate 4 is a multi-chip module (MCM) substrate having a recess 9〇1 formed on the lower surface 6. The wafers 401 and 40 2 are fixed in a predetermined position on the upper surface 5 of the package substrate 4 by solder bumps by solder bumps, for example, bump bumps relative to f (solder) Bump on). The gap between the wafers 401 and 420 and the package substrate 40 is filled with an underfill 43 and solidified 1 ' to strengthen the bond between the package substrate 4 and the wafers 4 0 1 and 4 0 2 . . f f 4 3 can be carried out by means of a fluid or non-flowing filling method. Those skilled in the art should be aware that in some cases, the primer 43 may also be omitted, not necessarily required.
年 月 日 修正 ""… 一------------------- 1297203 親 92117870Year Month Day Amendment ""... One ------------------------ 1297203 Pro 92117870
----------------------------------- ----- ----------------------------------------------------------------------- Λ. % \J I \J 五、發明說明（9) 覆晶BGA封裝構件9另包含有RC被動元件41， ㊉ 阻或電容元件，其係以表面黏合技術（SMT)對準固^ 裝基板40的下表面6的凹穴9〇1内。最後則植以球冊^·、 封裝（BGA)錫球（solder ball)44。 挪陣列 請參閱圖八，圖八為依據本發明第六較佳實施彻 覆晶BGA封裝構件91之剖面示意圖。如圖八所示，费1日 BGA封裝構件91包括有一封裝基板40，其具有一上^ = 5 以及一下表面6。依據本發明第六較佳實施例，封^基板 40為一多晶片模組（mui ti—chip m〇dule，MCM)基板，土其 具有一凹穴9 01形成於上表面5。覆晶BGA封裝構件8包含 有晶1 401及40 2。晶片4〇 2以及R*動元件41，例如電3阻 或電容元件，係以表面黏合技術（SMT)對準固定在晶片 土〇 1的下方，並且容納於凹穴9 〇 i。晶片4 〇 m以覆晶方式 藉由焊料凸塊（solder bump) 4 2對準固定在封裝基板4〇的 上表面5的預定位置，例如相對應之凸塊焊墊（s〇lder b u m p p a d )上。晶片4 0 1與封裝基板4 0之間縫隙則以底膠 (underf i 1 1 )43填滿並加以固化，以強化封裝基板4〇與晶 片4 0 1之間的結合。底膠4 3可以利用流動性或非流動性之 填膠方式進行，可填滿凹穴901。熟習該項技藝者應瞭解 在某些情況下，底勝4 3亦可以省略不用，並非必須要 件。最後則植以球柵陣列封裝（BGA)錫球（.solder bal 1 ) 44，覆晶BGA封裝構件9 1即可藉由BGA錫球44與一印刷電 路板（未顯示）構成電氣連#。----------------------------------- ----- ---------- -------------------------------------------------- ----------- Λ. % \JI \J V. Invention Description (9) The flip chip BGA package member 9 additionally includes an RC passive component 41, a ten-resistance or capacitive component, which is bonded to the surface. The technique (SMT) is aligned in the recess 9〇1 of the lower surface 6 of the mounting substrate 40. Finally, a ball ball ^·, package (BGA) solder ball 44 is implanted. Referring to Figure 8, Figure 8 is a cross-sectional view of a flip-chip BGA package member 91 in accordance with a sixth preferred embodiment of the present invention. As shown in FIG. 8, the BGA package member 91 includes a package substrate 40 having an upper surface 5 and a lower surface 6. According to a sixth preferred embodiment of the present invention, the sealing substrate 40 is a multi-chip module (MCM) substrate having a recess 901 formed on the upper surface 5. The flip chip BGA package member 8 includes crystals 1 401 and 40 2 . The wafer 4 〇 2 and the R* moving element 41, such as an electrical 3 Ω or capacitive element, are fixed under the wafer raft 1 by surface bonding technique (SMT) and housed in the pocket 9 〇 i. The wafer 4 〇m is fixed in a flip chip manner by a solder bump 4 2 in a predetermined position fixed on the upper surface 5 of the package substrate 4, for example, a corresponding bump pad (s〇lder bumppad) . The gap between the wafer 401 and the package substrate 40 is filled with a primer (underf i 1 1 ) 43 and cured to strengthen the bond between the package substrate 4 and the wafer 410. The primer 43 can be filled with a fluid or non-flowing glue to fill the pocket 901. Those skilled in the art should be aware that in some cases, the bottom wins 4 3 can also be omitted, not necessary. Finally, a ball grid array package (BGA) solder ball (.solder bal 1 ) 44 is implanted, and the flip chip BGA package member 9 1 can be electrically connected to a printed circuit board (not shown) by the BGA solder ball 44.
第16頁 1297203 ..._—_ _____________案違 92117870 五、發明說明（10) 年 月 曰 修正 綜上所述，本發明之優點是RC被動元件為可 型，利用基板或晶片之接觸塾位置設計來調整電 容值大小。RC被動元件可置放於BGA基板下方凹； 請參閱圖九至圖十，依據本發明，RC被動元 設計為一可調整式泛用型RC被動元件。如圖九所 設計一可調式泛用型RC被動元件，其電阻及電$ 小可涵蓋一般應用範圍。作法上，可先在晶圓之 元件上植上凸塊A、B、C、D、E、F等，接著在晶 (wafer saw)後，等待SMT製程。如圖十所示，在 基板上亦有相對應之接觸墊（pad) A’、B，、C，、 E ’、F ’等來連接R C被動元件，所需的電阻或電容 可在接觸墊（pad) A’、B，、C，、D，、E，、F，延伸 屬導線（metal trace)lll決定之。最後，以現有 裝配（FC assembly )製程以及SMT製程，:將可調式 RC被動元件安置在基板或晶片上·，完成產品之^ 上’此設計不佔用基板上 件之大小。此外，本發明 assembly )製程以及SMT製 程技術。以上種種優點均 所規定之產業利用性、新 依專利法提出申請，敬請 表面空間，因此可縮小 可與現有之標準覆晶裝 程相容，無需發展其它 顯示本發明已完全符合 嶺性及進步性等法定要 詳查並賜准本案專利。 件4 1可 示，先 〔值之大 RC被動 圓切割 晶片或 D，、 值大小 做出金 之覆晶 泛用型 f裝。 調泛用 阻及電 【或晶片 封裝構 配（FC 新的製 專利法 件，爰 以上所述僅為本發明之較佳實 請專利範圍所做之均等變化與^飾 施例，凡依本 ，皆應屬本發 發明申 明專利Page 16 1297003 ... _ - _ _____________ Case 92117870 V. Invention Description (10) Yearly 曰 Amendment In summary, the advantage of the present invention is that the RC passive component is of a formable, utilizing the substrate or wafer contact 塾The position is designed to adjust the capacitance value. The RC passive component can be placed under the BGA substrate. Referring to Figures 9 through 10, the RC passive element is designed as an adjustable universal RC passive component in accordance with the present invention. As shown in Figure 9, an adjustable universal RC passive component is designed, and its resistance and power consumption can cover a wide range of applications. In practice, bumps A, B, C, D, E, F, etc. may be implanted on the components of the wafer, and then wait for the SMT process after wafer saw. As shown in Figure 10, there are corresponding pads (A), B, C, E', F', etc. on the substrate to connect the RC passive components. The required resistance or capacitance can be used in the contact pads. (pad) A', B, C, D, E, F, the extension of the metal trace lll determines. Finally, with the existing assembly (FC assembly) process and the SMT process, the adjustable RC passive components are placed on the substrate or wafer to complete the product. This design does not occupy the size of the substrate. In addition, the inventive assembly process and SMT process technology. All of the above advantages are subject to the industrial applicability and the new patent application, please respect the surface space, so it can be reduced to be compatible with the existing standard flip chip process, without developing other displays. The invention is fully consistent with the ridge and progress. The statutory is required to scrutinize and grant the patent in this case. Piece 4 1 can be shown, first [value of the large RC passive circular cutting wafer or D, the value of the size of the gold-clad flip-chip type f installed. Adjusting the general resistance and electricity [or wafer package configuration (FC new patented patents, the above is only the equivalent of the preferred patent scope of the present invention and the decoration examples, according to this , all should belong to the invention patent
案號 92117870 1297203 五、發明說明（11) 之涵蓋範圍。 1111·! 1297203 圖式簡單說明 室藏 92117870 生―…—η——…—日 修正 圖式之簡單說明 圖一為習知半導體封裝構件之剖面示意圖。 圖二為依據本發明第一較隹實施例之覆晶BGA封裝構 件之剖面示意圖。 圖三為圖二覆晶BGA封裝構件之下表面平面示意圖。 圖四為圖二覆晶BGΑ封裝構件之下表面平面示意圖 (第二較佳實施例）。 圖五為依據本發明第三較隹實施例之打線封裝構件 之剖面示意圖。 圖六為依據本發明第四較佳實施例之覆晶BGA封裝構 件之剖面示意圖。 圖七為依據本發明第五較佳實施例之覆晶BGA封裝構 件之剖面示意圖。 圖八為依據本發明第六較佳實施例之覆晶BGA封裝構 件之剖面示意圖。 圖九至圖十顯示本發明之RC被動元件設計為一可調 整式泛用型RC被動元件。 圖式之符號說明 1 半導體封裝構件 10 封裝基板 101 晶片 102 晶片 11 RC被動元件 12 焊料凸塊Case No. 92117870 1297203 V. Coverage of the invention (11). 1111·! 1297203 Brief description of the schema. Storing 92117870 sheng—...—η—...—Day Correction of the Drawings Figure 1 is a schematic cross-sectional view of a conventional semiconductor package. Figure 2 is a cross-sectional view showing a flip chip BGA package according to a first comparative embodiment of the present invention. Figure 3 is a schematic plan view of the lower surface of the flip-chip BGA package of Figure 2. Figure 4 is a plan view showing the lower surface of the flip-chip BG package member of Figure 2 (second preferred embodiment). Figure 5 is a cross-sectional view showing a wire bonding package member according to a third embodiment of the present invention. Figure 6 is a cross-sectional view showing a flip chip BGA package according to a fourth preferred embodiment of the present invention. Figure 7 is a cross-sectional view showing a flip chip BGA package according to a fifth preferred embodiment of the present invention. Figure 8 is a cross-sectional view showing a flip chip BGA package according to a sixth preferred embodiment of the present invention. Figures 9 through 10 show that the RC passive component of the present invention is designed as an adjustable universal RC passive component. DESCRIPTION OF SYMBOLS 1 Semiconductor package member 10 Package substrate 101 Wafer 102 Wafer 11 RC passive component 12 Solder bump
第19頁 1297203 圖式簡單說明 案薄 92117870 13 底膠 2 上表面 4 覆晶BGA封裝構件 401 晶片 42 焊料凸塊 44 B G A錫球 5 上表面 7 打線封裝構件 702 金線 9 覆晶BGA封裝構件 91 覆晶BGA封裝構件 41 aRC被動元件 ± n _ a „： ^iL 14 B G A錫球 3 下表面 40 封裝基板 41 RC被動元件 43 底膠 46 錫球焊墊 6 下表面 701 樹脂 8 覆晶B G A封裝構件 901 凹穴 111 金屬導線 41 bRC被動元件Page 191297203 Brief description of the case file 92117870 13 Primer 2 Upper surface 4 Flip-chip BGA package member 401 Wafer 42 Solder bump 44 BGA solder ball 5 Upper surface 7 Wire-wound package member 702 Gold wire 9 Flip-chip BGA package member 91 Flip-chip BGA package member 41 aRC passive component ± n _ a „: ^iL 14 BGA solder ball 3 lower surface 40 package substrate 41 RC passive component 43 primer 46 solder ball pad 6 lower surface 701 resin 8 flip-chip BGA package 901 pocket 111 metal wire 41 bRC passive component
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92117870A TWI297203B (en) | 2003-06-30 | 2003-06-30 | Microelectronic package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92117870A TWI297203B (en) | 2003-06-30 | 2003-06-30 | Microelectronic package |
Publications (2)
| Publication Number | Publication Date |
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| TW200501373A TW200501373A (en) | 2005-01-01 |
| TWI297203B true TWI297203B (en) | 2008-05-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW92117870A TWI297203B (en) | 2003-06-30 | 2003-06-30 | Microelectronic package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI479639B (en) * | 2011-10-03 | 2015-04-01 | Invensas Corp | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
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2003
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI479639B (en) * | 2011-10-03 | 2015-04-01 | Invensas Corp | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
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