CN110071084A - 一种双面焊接封装产品及其组装方法 - Google Patents

一种双面焊接封装产品及其组装方法 Download PDF

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CN110071084A
CN110071084A CN201910287537.3A CN201910287537A CN110071084A CN 110071084 A CN110071084 A CN 110071084A CN 201910287537 A CN201910287537 A CN 201910287537A CN 110071084 A CN110071084 A CN 110071084A
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chip
plastic packaging
solder joints
metal solder
packaging material
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杨建伟
梁大钟
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Guangdong Style Science And Technology Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本发明涉及一种双面焊接封装产品及其组装方法，所述产品包括芯片、引线框或基板和塑封料，所述芯片上下表面均设有金属焊点，所述芯片下表面焊接在引线框或基板上，所述塑封料用于封装所述芯片和引线框或基板，塑封料上表面设有开口用于露出芯片上表面的金属焊点，所述开口处还设有焊锡料，用于与外部元件进行连接。所述组装方法采用在塑封料上表面进行激光开孔的方式，使芯片上表面的金属焊点露出，然后在开口处印刷焊锡料，并进行回流，使焊锡料与金属焊点熔接，然后与外部元件进行焊接，可以代替传统的金属丝焊接芯片，封装产品具有连接短距离、小体积、低阻值、电信号传输快、低耦合电信号产生等优点，为一些特殊芯片的焊接提供了实现方法。

Description

一种双面焊接封装产品及其组装方法
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种双面焊接封装产品及其组装方法。
背景技术
在传统的半导体封装产品中，芯片焊接是通过金属丝、装片胶、锡膏等来实现与引线框或基板的连接，随着集成电路的高集成化，很多产品要求小体积、低阻值、电信号传输快、低耦合电信号产生，对芯片的连接要求也越来越高，尤其是一些特殊应用的芯片，具有双面焊接功能，其中下表面可以采用锡膏这使传统的效果好的半导体焊接方式，但上表面则无法使用锡膏焊接，只能采用金属丝焊接方式连接，连接距离长，效率低，需要进一步研发新的焊接方法才能更好地与其他材料连接。
发明内容
本发明的目的在于提供一种双面焊接封装产品及其组装方法，实现芯片的双面焊接，封装产品具有小体积、低阻值、距离短、电信号传输快、低耦合电信号产生的优点。
本发明是这样实现的：一种双面焊接封装产品，包括芯片、引线框或基板和塑封料，所述芯片上下表面均设有金属焊点，所述芯片下表面焊接在引线框或基板上，所述塑封料用于封装所述芯片和引线框或基板，所述塑封料上表面设有开口用于露出芯片上表面的金属焊点，所述开口处还设有焊锡料，用于与外部元件进行连接。
其中，所述芯片上表面的塑封料的厚度为100-300μm。
本发明提供的另一种技术方案为：一种上面所述双面焊接封装产品的组装方法，包括以下步骤：
S1:将芯片下表面金属焊点焊接在引线框或基板上；
S2: 用塑封料对芯片和引线框或基板进行塑封；
S3:在塑封料上表面进行激光开口，所述开口位置与芯片上表面的金属焊点相对应，并使金属焊点外露；
S4:在开口处印刷焊锡料，并进行回流，使焊锡料与金属焊点熔接。
4、根据权利要求3所述的组装方法，其特征在于，利用激光对金属焊点处的塑封料进行点烧，直至金属焊点裸露；或者利用金属盖板掩盖封装产品，在金属盖板上设置与金属焊点相对应的孔，进行面烧，直至金属焊点裸露。。
本发明的有益效果为：本发明所述双面焊接封装产品的组装方法采用在塑封料上表面进行激光开孔的方式，使芯片上表面的金属焊点露出，然后在开口处印刷焊锡料，并进行回流，使焊锡料与金属焊点熔接，然后与外部元件进行焊接，可以代替传统的金属丝焊接芯片，封装产品具有连接短距离、小体积、低阻值、电信号传输快、低耦合电信号产生等优点，为一些特殊芯片的焊接，尤其是双面焊接芯片，以及3D封装等高端封装产品实现高质量、高可靠性的封装提供了实现方法。
附图说明
图1是本发明所述组装方法把芯片焊接到引线框的示意图；
图2是本发明所述组装方法把芯片和引线框进行塑封的示意图；
图3是本发明所述组装方法在塑封料上表进行激光开口的示意图；
图4是本发明所述组装方法在开口处印刷焊锡料并回流焊后的示意图。
其中，1、芯片；11、金属焊点；2、引线框；3、塑封料；31、开口；4、焊锡料；5、激光。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
作为本发明所述双面焊接封装产品的实施例，如图4所示，包括芯片1、引线框2（或者是基板）和塑封料3，所述芯片1上下表面均设有金属焊点11（本实施例下表面的金属焊点上还设有锡球），所述芯片1下表面焊接在引线框2上，所述塑封料3用于封装所述芯片1和引线框2，所述塑封料3上表面设有开口31用于露出芯片1上表面的金属焊点11，所述开口31处还设有焊锡料4，用于与外部元件进行连接。
在本实施例中，所述芯片1上表面的塑封料的厚度优选为100-300μm。太薄不易制作，太厚后序的激光开孔会费时费力。
作为本发明所述双面焊接封装产品的组装方法，包括以下步骤：
S1:将芯片1下表面金属焊点11焊接在引线框2上（或者是基板）；
S2: 用塑封料3对芯片1和引线框2进行塑封；
S3:在塑封料3上表面进行激光开口，所述开口31位置与芯片1上表面的金属焊点11相对应，并使金属焊点11外露；
S4:在开口31处印刷焊锡料4，并进行回流，使焊锡料4与金属焊点11熔接。
步骤S1和S2都是传统的常规焊接和塑封方式。在本实施例中，利用激光5对金属焊点11处的塑封料3进行点烧，直至金属焊点11裸露；或者利用金属盖板掩盖封装产品，在金属盖板上设置与金属焊点相对应的孔，进行面烧，直至金属焊点裸露，效率较高，但较浪费能源。
本发明所述双面焊接封装产品的组装方法采用在塑封料3上表面进行激光开孔的方式，使芯片1上表面的金属焊点11露出，然后在开口31处印刷焊锡料4，并进行回流，使焊锡料4与金属焊点11熔接，然后与外部元件进行焊接，可以代替传统的金属丝焊接芯片，封装产品具有连接短距离、小体积、低阻值、电信号传输快、低耦合电信号产生等优点，为一些特殊芯片的焊接，尤其是双面焊接芯片，以及3D封装等高端封装产品实现高质量、高可靠性的封装提供了实现方法。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (4)

1.一种双面焊接封装产品，其特征在于，包括芯片、引线框或基板和塑封料，所述芯片上下表面均设有金属焊点，所述芯片下表面焊接在引线框或基板上，所述塑封料用于封装所述芯片和引线框或基板，所述塑封料上表面设有开口用于露出芯片上表面的金属焊点，所述开口处还设有焊锡料，用于与外部元件进行连接。
2.根据权利要求1所述的双面焊接封装产品，其特征在于，所述芯片上表面的塑封料的厚度为100-300μm。
3.一种权利要求1或2所述双面焊接封装产品的组装方法，其特征在于，包括以下步骤：
S1:将芯片下表面金属焊点焊接在引线框或基板上；
S2:用塑封料对芯片和引线框或基板进行塑封；
S3:在塑封料上表面进行激光开口，所述开口位置与芯片上表面的金属焊点相对应，并使金属焊点外露；
S4:在开口处印刷焊锡料，并进行回流，使焊锡料与金属焊点熔接。
4.根据权利要求3所述的组装方法，其特征在于，利用激光对金属焊点处的塑封料进行点烧，直至金属焊点裸露；或者利用金属盖板掩盖封装产品，在金属盖板上设置与金属焊点相对应的孔，进行面烧，直至金属焊点裸露。
CN201910287537.3A 2019-04-11 2019-04-11 一种双面焊接封装产品及其组装方法 Pending CN110071084A (zh)

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US20150270232A1 (en) * 2014-03-21 2015-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
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US20150270232A1 (en) * 2014-03-21 2015-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
CN104409437A (zh) * 2014-12-04 2015-03-11 江苏长电科技股份有限公司 双面bump芯片包封后重布线的封装结构及其制作方法
CN106960800A (zh) * 2016-01-11 2017-07-18 美光科技公司 封装上封装构件与制作半导体器件的方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114361730A (zh) * 2021-12-28 2022-04-15 湖南海博瑞德电智控制技术有限公司 电芯模组用汇流排、电芯模组及其制造方法

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