CN102810522B - 封装结构和方法 - Google Patents
封装结构和方法 Download PDFInfo
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- CN102810522B CN102810522B CN201210159351.8A CN201210159351A CN102810522B CN 102810522 B CN102810522 B CN 102810522B CN 201210159351 A CN201210159351 A CN 201210159351A CN 102810522 B CN102810522 B CN 102810522B
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- diffusion barrier
- barrier layer
- metal column
- substrate
- potted element
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Abstract
一种封装元件其中没有有源器件。该封装元件包括:基板;通孔,位于基板中;顶部介电层,位于基板上方;以及金属柱,具有位于顶部介电层的顶面上方的顶面。该金属柱电连接到通孔。扩散势垒层位于该金属柱顶面上方。焊帽设置在该扩散势垒层上方。本发明还提供了封装结构和方法。
Description
相关申请的交叉参考
本申请要求于2011年5月30日提交的序列号为61/491,301的美国临时专利申请的权利,并且其标题为“三维集成电路(3DIC)封装结构和方法”,其全部内容以引用的方式并入本文。
技术领域
本发明一般地涉及半导体技术领域,更具体地来说,涉及封装结构和方法。
背景技术
在三维集成电路(3DIC)的形成过程中,具有形成在其中的集成电路的器件管芯与其它的封装元件(诸如中介板、封装基板、器件管芯、印刷电路板(PCBs)等)进行封装。在一些封装件中,封装元件也需要相互接合。例如,器件管芯可以接合至中介板,从而进一步接合至封装基板。可以将具有接合在其上的中介板和器件管芯的封装基板进一步接合至PCB。
可以通过倒装芯片接合来实施封装元件之间的接合,倒装芯片接合可以是金属之间接合或焊料接合。目前正在探讨可靠的接合方法。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种装置,包括:第一封装元件,其中,所述第一封装元件包括:基板;通孔,位于所述基板中;顶部介电层,位于所述基板上方;第一金属柱,所述第一金属柱的顶面位于所述顶部介电层的顶面上方,其中,所述第一金属柱电连接到所述通孔;第一扩散势垒层,位于所述第一金属柱的顶面上方;以及焊帽,位于所述第一扩散势垒层上方。
在该装置中,所述第一封装元件在其中没有有源器件和无源器件中的至少一个。
在该装置中,所述第一扩散势垒层的厚度大于大约2μm。
该装置进一步包括保护层,延伸到所述第一金属柱的侧壁上。
在该装置中,所述第一扩散势垒层没有延伸到所述第一金属柱的侧壁上。
该装置,进一步包括第二封装元件,所述第二封装元件包括:第二金属柱,位于所述第二封装元件的顶面处;以及第二扩散势垒层,位于所述第一金属柱的顶面上方并且电连接至所述焊帽,以及接合到所述焊帽。
在该装置中,所述第一扩散势垒层包括镍。
根据另一方面,提供了一种装置,包括中介板,所述中介板包括:基板;通孔,位于所述基板中;顶部介电层,位于基板上方;第一个金属柱,所述第一金属柱的顶面位于所述顶部介电层的顶面上方;以及第一扩散势垒层,所述第一扩散势垒层的部分位于所述第一金属柱的顶面上方;以及封装元件,接合到所述中介板其中,所述封装元件包括:第二顶部介电层;第二金属柱,越过所述第二顶部介电层延伸;第二扩散势垒层,位于所述第二金属柱的表面上方;以及焊接区域,与所述第一扩散势垒层和所述第二扩散势垒层接触,其中,所述焊接区域延伸到所述第一金属柱的侧壁上。
在该装置中,所述封装元件是器件管芯,所述器件管芯其中包括有源器件。
该装置进一步包括:保护层,延伸到第一金属柱侧壁上,其中,焊接区域与所述保护层接触。
在该装置中,所述焊接区域延伸到所述第一金属柱的侧壁上,并且与所述第一金属柱的侧壁接触。
在该装置中,所述第一扩散势垒层的厚度大于大约2μm。
根据本发明的又一方面,提供了一种装置,包括中介板,所述中介板包括:基板;通孔,位于所述基板中;顶部介电层,位于所述基板上方;铜柱,所述铜柱的顶面位于所述顶部介电层的顶面上方;扩散势垒层,位于所述铜柱的顶面上方并且与所述铜柱的顶面接触,其中,所述扩散势垒层包括非铜金属;以及焊帽,位于所述扩散势垒层上方并且与所述扩散势垒层接触,其中,所述焊帽电连接至所述通孔。
在该装置中,所述基板是硅基板,在所述硅基板的表面处没有形成有源器件。
在该装置中,所述基板是介电基板。
在该装置中,所述扩散势垒层的厚度大于大约2μm。
在该装置中,所述焊帽没有接合至另一封装元件。
在该装置中,所述中介板其中基本上没有有源器件。
在该装置中,所述中介板其中包括无源器件,其中,所述无源器件从基本上由电阻器、电容器、电感器、及其组合所组成的组中进行选择。
该装置进一步包括:电连接件,其中,所述铜柱和所述电连接件设置在所述中介板的相对两面上,并且其中,所述电连接件电连接至所述铜柱。
附图说明
为了更充分地理解实施例及其优点,现在将结合附图所进行的以下描述作为参考,其中:
图1和图2是根据各个实施例的封装元件的横截面图;以及
图3示出了图1和图2中的封装元件的接合。
具体实施方式
在下面详细讨论了本发明实施例的制造和使用。然而,应该理解,本实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅是示例性的,而不限制本发明的范围。
根据各个实施例提供了一种封装件。讨论了实施例的变型例。在整个附图和所描述的实施例中,将相同的参考标号用于指定相同的元件。
图1示出了封装元件100的横截面图。在实施例中,封装元件100是中介板。可选地,封装元件100可以是封装基板。封装元件100可以用来电连接封装元件100的正面和反面。封装元件100可以包括基板110,该基板110可以是半导体基板,如硅基板。可选地,基板110可以由介电材料形成,该介电材料可以是有机介电材料。形成的通孔112穿透基板110。尽管只示出了一个通孔112,但是封装元件100可以包括与通孔112类似的多个通孔。
互连结构114形成在基板110的一面上方。在通篇描述中,衬底具有互连结构114的面被称为正面,以及相反的面被称为背面。互连结构114包括金属线/金属焊盘116和通孔118,该金属线/金属焊盘116和通孔118电连接到通孔112。金属线/金属焊盘116和通孔118形成在介电层120中。在封装元件100的背面上方,可以形成互连结构(没有图示),该互连结构可以包括与互连结构114相似的金属线和通孔。可选地,可以不形成背面互连结构。互连结构114和背面互连结构都是任选的。当基板110是半导体基板时,介电层124可以形成在基板110的背面上方。在封装元件100的背面上方,形成连接件128并且该连接件电连接到通孔112。在一些示例性实施例中,连接件128是焊球。在可选实施例中,连接件128可以是金属焊盘、金属柱、在其上具有焊帽的金属柱等。
封装元件100其中可以不包括有源器件,如晶体管。在一些实施例中,封装元件100是包括无源器件126的无源元件,该无源器件126可以包括电阻器、电容器、和/或电感器等。在可选实施例中,封装元件100在其中不包括有源器件和无源器件。
连接件结构位于正面的顶部上方。连接件结构之一可以包括凸块底部金属化层(UBM)132,该凸块底部金属化层(UBM)132可以由铜种子层和位于铜种子层下方的钛层形成,但是也可以使用其它材料/层。尽管图1示出了UBM132形成在顶部介电层140中,但是除了延伸到顶部介电层140中的部分以外,UBM132还可以包括超出顶部介电层140的顶面延伸的部分。金属柱134形成在UBM132上方并且与UBM132接合。在一些实施例中,金属柱134是由铜形成,因此可选地,下文中称作铜柱134,但是其它金属也可以用于形成金属柱134。金属柱134的顶面位于顶部介电层140的顶面上方。
扩散势垒层136形成在金属柱134的顶面上方,并且例如,该扩散势垒层可以由电镀形成。根据一些实施例,扩散势垒层136由惰性金属形成,该惰性金属可以用作防止铜和焊料相互扩散的势垒。例如,扩散势垒层136可以由镍形成。在一些实施例中,侧壁保护层137形成在金属柱134的侧壁上。在可选实施例中,没有形成侧壁保护层137。侧壁保护层137可以是包括由不同材料所形成的多层的复合层,还可以是化学镀镍化学镀钯浸金(ENEPIG)层,该化学镀镍化学镀钯浸金层包括:镍层、位于镍层上方的钯层以及位于钯层上方的金层。金层可以使用浸渍镀形成。在其它实施例中,保护层137可以由其它成品材料和方法形成,其他成品材料和方法包括,但不限于:化学镀镍浸金(ENIG)、化学镀镍化学镀金(ENEG)、浸锡、浸银等。
扩散势垒层136的厚度T1可以大于约2μm,并且可以用作防止形成金属间化合物(IMC)的有效势垒,该金属间化合物形成在上层焊帽138中的焊料和金属柱134中的铜之间。因此,在封装元件100接合到封装元件200之后所生成的封装件中(图3),如果形成IMC,则该IMC具有最小厚度,并且由于形成IMC所消耗的金属柱134的部分也可以最小化。
焊帽138形成在扩散势垒层236的顶面上方,例如,该焊帽可以由电镀形成。焊帽138可以由共晶焊接材料形成。可选地,焊帽138也可以是无铅焊料。焊帽138可以回流以具有圆形表面。可选地,焊帽138也可以保持不回流,因此可以具有平坦顶面。
图2示出了封装元件200的横截面图。根据一些实施例,封装元件200是器件管芯,该器件管芯可以是图形管芯(graphic die)、存储管芯(memorydie)、核心器件管芯(core device die)等。封装元件200其中可以包括有源器件226,如晶体管,或者可选地,可以包括无源器件(也由装置226表示)并且没有有源器件。封装元件200也可以包括顶部介电层240,该顶部介电层240可以包括诸如聚酰亚胺的聚合物。可以形成UBM232和金属柱234,其中,UBM232可以延伸到顶部介电层240中,从而电连接至下层导电装置,如金属焊盘241,该金属焊盘241可以是铝焊盘或铝铜焊盘。尽管没有示出,但是UMB232可以包括位于顶部介电层240上方并且与顶部介电层240重合的部分。金属柱234形成在UBM232上方并且可以与UBM232接触。金属柱234可以由铜或铜合金形成,但是也可以使用其它类型的金属。还形成了扩散势垒层236和焊帽238。UBM232、金属柱234、扩散势垒层236、以及焊帽238的材料和形成方法可以基本上分别与UBM132、金属柱134、扩散势垒层136、以及焊帽138的材料和形成方法相同。因此,UBM232、金属柱234、扩散势垒层236、以及焊帽238的具体细节可以参考封装元件100中的对应元件。
图3示出了封装元件100和封装元件200的接合。图1中的焊帽138首先与图2中的焊帽238接触,并且实施回流以熔化焊帽138和焊帽238。因此,接合焊帽138和焊帽238以形成焊接区域150。扩散势垒层136对熔融焊料具有良好的润湿能力,并且扩散势垒层136和焊接区域150之间的接合可靠。焊接区域150可以延伸到金属柱134和/或金属柱234的侧壁。
在一些实施例中,在金属柱134(图1)的侧壁上没有形成保护层137,将助溶剂用于清理金属柱134侧壁表面,以便去除表面金属氧化物,并且金属柱134的暴露侧壁对熔融焊料有很好的润湿能力。因此,金属柱134和焊接区域150之间的连接也是可靠的。可选地,在保护层137形成在金属柱134(图1)的侧壁上的实施例中,焊接区域150可以延伸以与保护层137完全接触,该保护层137具有很好的润湿能力。为了使焊接区域150与金属柱134/234的侧壁或保护层137接触,控制焊帽138(图1)和焊帽238(图2)中的焊料的量,从而使得将足够的焊料设置到金属柱134/234的侧壁上。
图3也示出了底部填充物54,该底部填充物54分布在封装元件100和封装元件200之间。底部填充物54可以与介电层140和介电层240以及焊接区域150完全接触。
根据实施例,一种封装元件其中不包括有源器件。该封装元件包括:基板;通孔,位于基板中;顶部介电层,位于基板上方;以及金属柱,具有位于顶部介电层的顶面上方的顶面。该金属柱电连接到通孔。扩散势垒层位于该金属柱的顶面上方。焊帽设置在扩散势垒层上方。
根据其它实施例,一种装置包括接合至封装元件的中介板。该中介板包括:基板;通孔,位于基板中;顶部介电层,位于基板上方;第一金属柱,具有位于顶部介电层的顶面上方的顶面;以及第一扩散势垒层,具有位于第一金属柱的顶面上方的部分。该封装元件包括:第二顶部介电层;第二金属柱,越过第二顶部介电层延伸;第二扩散势垒层,位于第二金属柱的表面上方;以及焊接区域,与第一扩散势垒层和第二扩散势垒层接触。该焊接区域延伸到第一金属柱的侧壁上。
根据又一些实施例,中介板包括:基板;通孔,位于基板中;顶部介电层,位于基板上方,铜柱,具有位于顶部介电层的顶面上方的顶面,以及扩散势垒层,位于铜柱的顶面上方并且与铜柱的顶面接触。该扩散势垒层包括非铜金属。焊帽位于扩散势垒层上方并且与扩散势垒层接触,其中焊帽电连接至通孔。
尽管已经详细描述了实施例及其优势,但应该理解,可以在不背离所附权利要求限定的实施例的主旨和范围的情况下,做各种不同的改变、替换和改变。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员将从本发明很容易地理解,根据本发明可以使用现有的或今后开发的工艺、机器、制造、材料组分、装置、方法或步骤,执行与本文所述的相应实施例基本上相同的功能或者获得基本上相同的结果。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或者步骤。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (20)
1.一种装置,包括:
第一封装元件,其中,所述第一封装元件包括:
基板;
通孔,位于所述基板中;
顶部介电层,位于所述基板上方;
第一金属柱,所述第一金属柱的顶面位于所述顶部介电层的顶面上方,其中,所述第一金属柱电连接到所述通孔;
第一扩散势垒层,位于所述第一金属柱的顶面上方;以及
焊帽,位于所述第一扩散势垒层上方。
2.根据权利要求1所述的装置,其中,所述第一封装元件在其中没有有源器件和无源器件中的至少一个。
3.根据权利要求1所述的装置,其中,所述第一扩散势垒层的厚度大于2μm。
4.根据权利要求1所述的装置,进一步包括保护层,延伸到所述第一金属柱的侧壁上。
5.根据权利要求1所述的装置,其中,所述第一扩散势垒层没有延伸到所述第一金属柱的侧壁上。
6.根据权利要求1所述的装置,进一步包括:
第二封装元件,包括:
第二金属柱,位于所述第二封装元件的顶面处;以及
第二扩散势垒层,位于所述第一金属柱的顶面上方并且电连接至所述焊帽,以及接合到所述焊帽。
7.根据权利要求1所述的装置,其中,所述第一扩散势垒层包括镍。
8.一种装置,包括:
中介板,包括:
基板;
通孔,位于所述基板中;
顶部介电层,位于基板上方;
第一金属柱,所述第一金属柱的顶面位于所述顶部介电层的顶面上方;以及
第一扩散势垒层,所述第一扩散势垒层的部分位于所述第一金属柱的顶面上方;以及
封装元件,接合到所述中介板其中,所述封装元件包括:
第二顶部介电层;
第二金属柱,越过所述第二顶部介电层延伸;
第二扩散势垒层,位于所述第二金属柱的表面上方;以及
焊接区域,与所述第一扩散势垒层和所述第二扩散势垒层接触,其中,所述焊接区域延伸到所述第一金属柱的侧壁上。
9.根据权利要求8所述的装置,其中,所述封装元件是器件管芯,所述器件管芯其中包括有源器件。
10.根据权利要求8所述的装置,进一步包括:保护层,延伸到第一金属柱侧壁上,其中,焊接区域与所述保护层接触。
11.根据权利要求8所述的装置,其中,所述焊接区域延伸到所述第一金属柱的侧壁上,并且与所述第一金属柱的侧壁接触。
12.根据权利要求8所述的装置,其中,所述第一扩散势垒层的厚度大于2μm。
13.一种装置,包括:
中介板,包括:
基板;
通孔,位于所述基板中;
顶部介电层,位于所述基板上方;
铜柱,所述铜柱的顶面位于所述顶部介电层的顶面上方;
扩散势垒层,位于所述铜柱的顶面上方并且与所述铜柱的顶面接触,其中,所述扩散势垒层包括非铜金属;以及
焊帽,位于所述扩散势垒层上方并且与所述扩散势垒层接触,其中,所述焊帽电连接至所述通孔。
14.根据权利要求13所述的装置,其中,所述基板是硅基板,在所述硅基板的表面处没有形成有源器件。
15.根据权利要求13所述的装置,其中,所述基板是介电基板。
16.根据权利要求13所述的装置,其中,所述扩散势垒层的厚度大于2μm。
17.根据权利要求13所述的装置,其中,所述焊帽没有接合至另一封装元件。
18.根据权利要求13所述的装置,其中,所述中介板其中没有有源器件。
19.根据权利要求18所述的装置,其中,所述中介板其中包括无源器件,其中,所述无源器件从由电阻器、电容器、电感器、及其组合所组成的组中进行选择。
20.根据权利要求13所述的装置,进一步包括:电连接件,其中,所述铜柱和所述电连接件设置在所述中介板的相对两面上,并且其中,所述电连接件电连接至所述铜柱。
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Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9142533B2 (en) | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US8610285B2 (en) | 2011-05-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC packaging structures and methods with a metal pillar |
US9425136B2 (en) | 2012-04-17 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US9646923B2 (en) | 2012-04-17 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
US9299674B2 (en) | 2012-04-18 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US9111817B2 (en) | 2012-09-18 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure and method of forming same |
US9123780B2 (en) | 2012-12-19 | 2015-09-01 | Invensas Corporation | Method and structures for heat dissipating interposers |
US9147663B2 (en) | 2013-05-28 | 2015-09-29 | Intel Corporation | Bridge interconnection with layered interconnect structures |
US9159682B2 (en) | 2013-09-08 | 2015-10-13 | Freescale Semiconductor, Inc. | Copper pillar bump and flip chip package using same |
US9053972B1 (en) | 2013-11-21 | 2015-06-09 | Freescale Semiconductor, Inc. | Pillar bump formed using spot-laser |
US9474162B2 (en) | 2014-01-10 | 2016-10-18 | Freescale Semiocnductor, Inc. | Circuit substrate and method of manufacturing same |
TWI576869B (zh) | 2014-01-24 | 2017-04-01 | 精材科技股份有限公司 | 被動元件結構及其製作方法 |
TWI557865B (zh) * | 2014-01-29 | 2016-11-11 | 矽品精密工業股份有限公司 | 堆疊組及其製法與基板結構 |
US9558859B2 (en) * | 2014-02-18 | 2017-01-31 | Rsm Electron Power, Inc. | Multilayer substrate and method for manufacturing the same |
CN105590869A (zh) * | 2014-10-24 | 2016-05-18 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法 |
CN106298706A (zh) * | 2015-05-20 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | 一种晶圆凸块形成方法 |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
US10103069B2 (en) | 2016-04-01 | 2018-10-16 | X-Celeprint Limited | Pressure-activated electrical interconnection by micro-transfer printing |
US10049893B2 (en) * | 2016-05-11 | 2018-08-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor device with a conductive post |
US10222698B2 (en) | 2016-07-28 | 2019-03-05 | X-Celeprint Limited | Chiplets with wicking posts |
US11064609B2 (en) | 2016-08-04 | 2021-07-13 | X Display Company Technology Limited | Printable 3D electronic structure |
TWI723140B (zh) * | 2016-08-10 | 2021-04-01 | 台灣積體電路製造股份有限公司 | 經封裝裝置以及形成經封裝裝置的方法 |
US10692830B2 (en) * | 2017-10-05 | 2020-06-23 | Texas Instruments Incorporated | Multilayers of nickel alloys as diffusion barrier layers |
US10490448B2 (en) * | 2017-12-29 | 2019-11-26 | Texas Instruments Incorporated | Method of using a sacrificial conductive stack to prevent corrosion |
US10985124B2 (en) * | 2018-04-23 | 2021-04-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
CN109148495A (zh) * | 2018-07-02 | 2019-01-04 | 复旦大学 | 一种cmos图像传感器三维封装方法 |
DE102019103355A1 (de) | 2019-02-11 | 2020-08-13 | Infineon Technologies Ag | Halbleitervorrichtung mit einer Kupfersäule-Zwischenverbindungsstruktur |
KR20210068891A (ko) | 2019-12-02 | 2021-06-10 | 삼성전자주식회사 | 인터포저, 및 이를 가지는 반도체 패키지 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1901198A (zh) * | 2005-06-24 | 2007-01-24 | 西门子公司 | 电子组件和用于制造电子组件的方法 |
CN101740417A (zh) * | 2008-11-13 | 2010-06-16 | 台湾积体电路制造股份有限公司 | 可堆叠芯片的制造方法 |
Family Cites Families (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1491483A (en) | 1974-08-08 | 1977-11-09 | Pilkington Brothers Ltd | Glass manufacturing apparatus and process |
US4811082A (en) | 1986-11-12 | 1989-03-07 | International Business Machines Corporation | High performance integrated circuit packaging structure |
US4990462A (en) | 1989-04-12 | 1991-02-05 | Advanced Micro Devices, Inc. | Method for coplanar integration of semiconductor ic devices |
US5075253A (en) | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
FR2667724B1 (fr) | 1990-10-09 | 1992-11-27 | Thomson Csf | Procede de realisation des metallisations d'electrodes d'un transistor. |
JPH06505597A (ja) | 1991-03-04 | 1994-06-23 | モトローラ・インコーポレーテッド | 非導電性電子回路パッケージ用シールド装置 |
JP3078646B2 (ja) | 1992-05-29 | 2000-08-21 | 株式会社東芝 | インジウムバンプの製造方法 |
US5334804A (en) | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
US6835898B2 (en) | 1993-11-16 | 2004-12-28 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
US5380681A (en) | 1994-03-21 | 1995-01-10 | United Microelectronics Corporation | Three-dimensional multichip package and methods of fabricating |
US6388203B1 (en) | 1995-04-04 | 2002-05-14 | Unitive International Limited | Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby |
JPH0997791A (ja) | 1995-09-27 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | バンプ構造、バンプの形成方法、実装接続体 |
US6002177A (en) | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
US5808874A (en) | 1996-05-02 | 1998-09-15 | Tessera, Inc. | Microelectronic connections with liquid conductive elements |
US6051190A (en) | 1997-06-17 | 2000-04-18 | Corning Incorporated | Method and apparatus for transferring and dispensing small volumes of liquid and method for making the apparatus |
JP3654485B2 (ja) | 1997-12-26 | 2005-06-02 | 富士通株式会社 | 半導体装置の製造方法 |
US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
US6213376B1 (en) | 1998-06-17 | 2001-04-10 | International Business Machines Corp. | Stacked chip process carrier |
US6281042B1 (en) | 1998-08-31 | 2001-08-28 | Micron Technology, Inc. | Structure and method for a high performance electronic packaging assembly |
US6271059B1 (en) | 1999-01-04 | 2001-08-07 | International Business Machines Corporation | Chip interconnection structure using stub terminals |
US6461895B1 (en) | 1999-01-05 | 2002-10-08 | Intel Corporation | Process for making active interposer for high performance packaging applications |
US6229216B1 (en) | 1999-01-11 | 2001-05-08 | Intel Corporation | Silicon interposer and multi-chip-module (MCM) with through substrate vias |
JP4131595B2 (ja) | 1999-02-05 | 2008-08-13 | 三洋電機株式会社 | 半導体装置の製造方法 |
US6243272B1 (en) | 1999-06-18 | 2001-06-05 | Intel Corporation | Method and apparatus for interconnecting multiple devices on a circuit board |
US6387793B1 (en) | 2000-03-09 | 2002-05-14 | Hrl Laboratories, Llc | Method for manufacturing precision electroplated solder bumps |
US6578754B1 (en) | 2000-04-27 | 2003-06-17 | Advanpack Solutions Pte. Ltd. | Pillar connections for semiconductor chips and method of manufacture |
US6592019B2 (en) | 2000-04-27 | 2003-07-15 | Advanpack Solutions Pte. Ltd | Pillar connections for semiconductor chips and method of manufacture |
US6528109B1 (en) * | 2000-09-13 | 2003-03-04 | Ford Global Technologies, Inc. | Integrated paint quality control system |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
KR100364635B1 (ko) | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US20030006062A1 (en) * | 2001-07-06 | 2003-01-09 | Stone William M. | Interconnect system and method of fabrication |
KR100394808B1 (ko) | 2001-07-19 | 2003-08-14 | 삼성전자주식회사 | 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법 |
US6656611B2 (en) | 2001-07-20 | 2003-12-02 | Osram Opto Semiconductors Gmbh | Structure-defining material for OLEDs |
US6853076B2 (en) | 2001-09-21 | 2005-02-08 | Intel Corporation | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same |
KR100435813B1 (ko) | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법 |
DE10200399B4 (de) | 2002-01-08 | 2008-03-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung |
US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
US6661085B2 (en) | 2002-02-06 | 2003-12-09 | Intel Corporation | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack |
US6975016B2 (en) | 2002-02-06 | 2005-12-13 | Intel Corporation | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof |
US6622907B2 (en) * | 2002-02-19 | 2003-09-23 | International Business Machines Corporation | Sacrificial seed layer process for forming C4 solder bumps |
US6762076B2 (en) | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
TW550800B (en) | 2002-05-27 | 2003-09-01 | Via Tech Inc | Integrated circuit package without solder mask and method for the same |
US20040007779A1 (en) | 2002-07-15 | 2004-01-15 | Diane Arbuthnot | Wafer-level method for fine-pitch, high aspect ratio chip interconnect |
US6600222B1 (en) | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
US6790748B2 (en) | 2002-12-19 | 2004-09-14 | Intel Corporation | Thinning techniques for wafer-to-wafer vertical stacks |
US6908565B2 (en) | 2002-12-24 | 2005-06-21 | Intel Corporation | Etch thinning techniques for wafer-to-wafer vertical stacks |
US7008867B2 (en) * | 2003-02-21 | 2006-03-07 | Aptos Corporation | Method for forming copper bump antioxidation surface |
US6924551B2 (en) | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US6946384B2 (en) | 2003-06-06 | 2005-09-20 | Intel Corporation | Stacked device underfill and a method of fabrication |
US7320928B2 (en) | 2003-06-20 | 2008-01-22 | Intel Corporation | Method of forming a stacked device filler |
KR100537892B1 (ko) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
US7276801B2 (en) * | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
US7345350B2 (en) | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
KR100621992B1 (ko) | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지 |
JP2005175128A (ja) | 2003-12-10 | 2005-06-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7541275B2 (en) * | 2004-04-21 | 2009-06-02 | Texas Instruments Incorporated | Method for manufacturing an interconnect |
KR100570514B1 (ko) | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
KR100618837B1 (ko) | 2004-06-22 | 2006-09-01 | 삼성전자주식회사 | 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법 |
US7307005B2 (en) | 2004-06-30 | 2007-12-11 | Intel Corporation | Wafer bonding with highly compliant plate having filler material enclosed hollow core |
US7087538B2 (en) | 2004-08-16 | 2006-08-08 | Intel Corporation | Method to fill the gap between coupled wafers |
US7335588B2 (en) * | 2005-04-15 | 2008-02-26 | International Business Machines Corporation | Interconnect structure and method of fabrication of same |
US7391112B2 (en) | 2005-06-01 | 2008-06-24 | Intel Corporation | Capping copper bumps |
US7317256B2 (en) | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
US7557597B2 (en) | 2005-06-03 | 2009-07-07 | International Business Machines Corporation | Stacked chip security |
US7402515B2 (en) | 2005-06-28 | 2008-07-22 | Intel Corporation | Method of forming through-silicon vias with stress buffer collars and resulting devices |
US7432592B2 (en) | 2005-10-13 | 2008-10-07 | Intel Corporation | Integrated micro-channels for 3D through silicon architectures |
US7528494B2 (en) | 2005-11-03 | 2009-05-05 | International Business Machines Corporation | Accessible chip stack and process of manufacturing thereof |
US7410884B2 (en) | 2005-11-21 | 2008-08-12 | Intel Corporation | 3D integrated circuits using thick metal for backside connections and offset bumps |
US7402442B2 (en) | 2005-12-21 | 2008-07-22 | International Business Machines Corporation | Physically highly secure multi-chip assembly |
US7279795B2 (en) | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
US7498119B2 (en) | 2006-01-20 | 2009-03-03 | Palo Alto Research Center Incorporated | Process for forming a feature by undercutting a printed mask |
US7510939B2 (en) | 2006-01-31 | 2009-03-31 | International Business Machines Corporation | Microelectronic structure by selective deposition |
US20080081464A1 (en) * | 2006-09-29 | 2008-04-03 | Tokyo Electron Limited | Method of integrated substrated processing using a hot filament hydrogen radical souce |
TWI419242B (zh) * | 2007-02-05 | 2013-12-11 | Chipmos Technologies Inc | 具有加強物的凸塊結構及其製造方法 |
US7485564B2 (en) * | 2007-02-12 | 2009-02-03 | International Business Machines Corporation | Undercut-free BLM process for Pb-free and Pb-reduced C4 |
US7576435B2 (en) | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
KR101213175B1 (ko) | 2007-08-20 | 2012-12-18 | 삼성전자주식회사 | 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지 |
US8349721B2 (en) * | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
TW201019440A (en) * | 2008-11-03 | 2010-05-16 | Int Semiconductor Tech Ltd | Bumped chip and semiconductor flip-chip device applied from the same |
KR20100060968A (ko) * | 2008-11-28 | 2010-06-07 | 삼성전기주식회사 | 메탈 포스트를 구비한 기판 및 그 제조방법 |
DE102008063401A1 (de) | 2008-12-31 | 2010-07-08 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit einem kosteneffizienten Chipgehäuse, das auf der Grundlage von Metallsäuren angeschlossen ist |
US8159070B2 (en) | 2009-03-31 | 2012-04-17 | Megica Corporation | Chip packages |
US8759949B2 (en) * | 2009-04-30 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside structures having copper pillars |
US8158489B2 (en) * | 2009-06-26 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of TSV backside interconnects by modifying carrier wafers |
US7919406B2 (en) | 2009-07-08 | 2011-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming pillar bump structure having sidewall protection |
US8324738B2 (en) * | 2009-09-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
US8039966B2 (en) * | 2009-09-03 | 2011-10-18 | International Business Machines Corporation | Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects |
TW201113962A (en) * | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Chip having metal pillar structure |
US8847387B2 (en) * | 2009-10-29 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust joint structure for flip-chip bonding |
US9607936B2 (en) * | 2009-10-29 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump joint structures with improved crack resistance |
US8637392B2 (en) * | 2010-02-05 | 2014-01-28 | International Business Machines Corporation | Solder interconnect with non-wettable sidewall pillars and methods of manufacture |
TWM397597U (en) * | 2010-04-15 | 2011-02-01 | Di-Quan Hu | Package structure of integrated circuit |
US8441124B2 (en) | 2010-04-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
US9018758B2 (en) | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
US8922004B2 (en) * | 2010-06-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
US8232193B2 (en) * | 2010-07-08 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming Cu pillar capped by barrier layer |
US8405199B2 (en) | 2010-07-08 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar for semiconductor substrate and method of manufacture |
US9048135B2 (en) * | 2010-07-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper pillar bump with cobalt-containing sidewall protection |
US8546254B2 (en) * | 2010-08-19 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
US8283781B2 (en) * | 2010-09-10 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having pad structure with stress buffer layer |
US8242011B2 (en) * | 2011-01-11 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming metal pillar |
US20120193785A1 (en) * | 2011-02-01 | 2012-08-02 | Megica Corporation | Multichip Packages |
US8664760B2 (en) | 2011-05-30 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector design for packaging integrated circuits |
US8610285B2 (en) | 2011-05-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC packaging structures and methods with a metal pillar |
-
2011
- 2011-11-16 US US13/298,046 patent/US8610285B2/en active Active
-
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- 2012-05-21 CN CN201210159351.8A patent/CN102810522B/zh active Active
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- 2013-10-03 US US14/045,578 patent/US9508666B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1901198A (zh) * | 2005-06-24 | 2007-01-24 | 西门子公司 | 电子组件和用于制造电子组件的方法 |
CN101740417A (zh) * | 2008-11-13 | 2010-06-16 | 台湾积体电路制造股份有限公司 | 可堆叠芯片的制造方法 |
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