CN102254869A - 集成电路装置 - Google Patents
集成电路装置 Download PDFInfo
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- CN102254869A CN102254869A CN2010102546977A CN201010254697A CN102254869A CN 102254869 A CN102254869 A CN 102254869A CN 2010102546977 A CN2010102546977 A CN 2010102546977A CN 201010254697 A CN201010254697 A CN 201010254697A CN 102254869 A CN102254869 A CN 102254869A
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- welding resisting
- resisting layer
- reflow
- workpiece
- solder
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Abstract
本发明一实施例提供一种集成电路装置,包括:一第一工件,包括:一防焊层,位于该第一工件之上,其中该防焊层包括一防焊层开口;以及一接垫,位于该第一工件之上,且位于该防焊层开口之中;一第二工件,包括一不可回焊的金属凸块,位于该第二工件之上;以及一焊料凸块,将该不可回焊的金属凸块接合至该接垫,该焊料凸块的至少一部分位于该防焊层开口之中,且邻接该不可回焊的金属凸块及该接垫,其中该焊料凸块具有一高度,等于该不可回焊的金属凸块与该接垫之间的一距离,且其中该防焊层具有一厚度,大于该焊料凸块的该高度的50%。本发明可造成更均匀的焊料轮廓及较少的焊料破裂。
Description
技术领域
本发明涉及集成电路,且特别涉及倒装芯片接合结构(flip-chip bondstructure)及其制作方法。
背景技术
在制作晶片的过程中,会先在半导体晶片中的半导体基底的表面形成集成电路元件(例如晶体管)。之后,在集成电路元件上形成内连线结构(interconnect structure)。在半导体晶片的表面上形成凸块,且这些凸块电性耦接至集成电路元件。将半导体晶片切割成多个半导体芯片,也就是俗称的裸片(dies)。
在半导体芯片的封装工艺中,半导体芯片时常使用倒装芯片接合而与封装基板相连。焊料用以使半导体芯片中的凸块连结至封装基底中的接垫(bondpads)。在接合两个半导体芯片(或是一个半导体芯片与一个封装基底)时,可以将焊料预先形成在前述两个半导体芯片其中之一的凸块/接垫上、或者是同时形成在前述两个半导体芯片的凸块/接垫上。之后,进行一回焊(re-flow)工艺以使焊料连接半导体芯片。
图1显示一示范性的接合结构,用以接合芯片202与芯片204。焊料210用以将芯片202中的金属凸块212接合至接垫214。假如相隔距离(standoffdistance)D定义为芯片204中的防焊层206与芯片202中介电层208之间的距离,由于芯片202与204的弯曲现象,相隔距离D可能在接合结构与接合结构之间改变。举例来说,在接合之后,接近芯片202、204的边缘的接合结构的相隔距离D可大于接近芯片202、204的中心的接合结构的相隔距离D。因此,难以控制焊料凸块的轮廓。例如,在图1中,焊料210可能被铜凸块212挤到一旁,这种情形经常发生于接近芯片边缘的接合结构,然而,在接近芯片中心的位置则不会出现这种轮廓。焊料凸块的轮廓上的不一致可能会导致凸块断裂(bump crack),因而需被解决。
发明内容
为克服现有技术中的缺陷,本发明一实施例提供一种集成电路装置,包括:一第一工件,包括:一防焊层,位于该第一工件之上,其中该防焊层包括一防焊层开口;以及一接垫,位于该第一工件之上,且位于该防焊层开口之中;一第二工件,包括一不可回焊的金属凸块,位于该第二工件之上;以及一焊料凸块,将该不可回焊的金属凸块接合至该接垫,该焊料凸块的至少一部分位于该防焊层开口之中,且邻接该不可回焊的金属凸块及该接垫,其中该焊料凸块具有一高度,等于该不可回焊的金属凸块与该接垫之间的一距离,且其中该防焊层具有一厚度,大于该焊料凸块的该高度的50%。
本发明一实施例提供一种集成电路装置,包括:一第一工件,包括:一接垫;一防焊层,位于该第一工件之上,其中该防焊层包括一防焊层开口,具有一第一体积;一接垫,位于该第一工件之上,且位于该防焊层开口之中;以及一焊料层,位于该接垫之上,且位于该防焊层开口之中,其中该防焊层具有一第二体积,不大于该防焊层开口的该第一体积。
通过增加防焊层的高度,使防焊层开口的体积增加。因此,当进行两工件间的接合时,回焊的焊料在水平方向上被防焊层所局限,且因而提供高垂直力至工件。焊料的局限可造成更均匀的焊料轮廓及较少的焊料破裂。再者,此局限帮助减小裸片弯曲。
附图说明
图1显示公知的接合结构,接合结构中的焊料被挤压至一旁。
图2显示包含不可回焊的金属凸块的第一工件的剖面图。
图3A及图3B显示包含具有至少一部分位于防焊层开口中的焊料的第二工件的剖面图。
图4-图11显示根据本发明各种实施例的接合结构的剖面图。
其中,附图标记说明如下:
2、100~工件;
10~基底;
12~内连线结构;
14~半导体元件;
28~金属垫;
30~保护层;
32~凸块下金属层;
34~铜凸块;
36~金属表面处理层;
38~不可回焊的金属凸块;
40~焊料帽;
44~底表面;
110~接垫;
116~介电层;
122~金属垫;
123~防焊层;
124~导电缓冲层;
130~焊球;
132~开口;
134~虚线;
142~焊料凸块;
143、144~金属间化合物;
145~顶表面;
146~间隙;
202、204~芯片;
206~防焊层;
208~介电层;
210~焊料;
212~金属凸块;
214~接垫;
D~距离;
H1、H2~高度;
T~厚度;
W1、W2~水平尺寸;
W3~宽度。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是,本发明提供许多可供应用的发明概念,其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式,非用以限制本发明的范围。此外,在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明,不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者,当述及一第一材料层位于一第二材料层上或之上时,包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
根据本发明一实施例,提供了一种新颖的接合结构。将讨论实施例的各种变化。在不同的实施例之间,相似的标号将用以标示相似的元件。
请参照图2,提供一工件(work piece)2,工件2包括基底10。工件2可为一元件裸片(device die),其内含有有源元件(例如晶体管),虽然工件2也可为不具有有源元件于其中的封装基底或中介层(interposer)。在一实施例中,工件2为一元件裸片,基底10可为一半导体基底,例如为一硅基底,虽然,基底可包括其他的半导体材料。可于基底10的表面形成半导体元件14(例如晶体管)。在基底10上形成内连线结构12,内连线结构12包括形成于其中且连接至半导体元件14的金属线路(metal lines)与导电插塞(vias)(未显示)。金属线路及导电插塞可由铜或铜合金形成,且可使用公知的镶嵌工艺而形成。连线结构12可包括众所周知的层间介电层(ILDs)及金属间介电层(IMDs)。
在内连线结构12上形成金属垫28。金属垫28可包括铝、铜、银、金、镍、钨、前述的合金、及/或前述的多层结构。金属垫28例如是通过其下的内连线结构12而电性耦接至半导体元件14。可形成保护层(passivationlayer)30以覆盖金属垫28的边缘部分。在一实施例中,保护层30是由聚酰亚胺(polyimide)或是其他已知的介电材料(例如氮化硅、氧化硅、或其相似物)所构成。
凸块下金属(under bump metallurgy,UBM)层32形成于金属垫28上并电性连接至金属垫28。凸块下金属层32可包括铜层与钛层(未显示)。铜凸块34形成于凸块下金属层32上。在一实施例中,铜凸块34以电镀形成。一示范性的电镀工艺包括:形成一毯覆式凸块下金属层(未显示,其中凸块下金属层32为一部分的毯覆式凸块下金属层);在毯覆式凸块下金属层上形成一掩模(未显示);将掩模图案化以形成一开口:于开口中电镀铜凸块34:以及移除掩模及凸块下金属层的先前被掩模所覆盖的部分。铜凸块34可由纯铜或是铜合金所构成。
金属表面处理层(metal finish)36可例如通过电镀而形成于铜凸块34上。金属表面处理层36可包括多种不同的材料与层,且可用以避免铜凸块34氧化以及铜凸块34与焊料142(图2未显示,请参照图4)之间的扩散作用。在一实施例中,金属表面处理层36是由镍构成,虽然也可添加其他的金属。或者,金属表面处理层36可以是由无电镀镍钯金(electroless nickel electrolesspalladium immersion gold,ENEPIG)所构成,其包括一镍层与镍层上的钯层,且镍层与钯层皆是以无电镀的方式形成。无电镀镍钯金还包括钯层上的金层,且金层的形成方式可为浸镀(immersion plating)。在其他实施例中,金属表面处理层36可以其他已知的表面处理材料与方法而形成,包括但不限于,无电镀镍浸金(electroless nickel immersion gold,ENIG)、直接浸金(directimmersion gold,DIG)、或其相似方法。金属表面处理层36可以仅限于形成在铜凸块34正上方的区域中,而不形成在铜凸块34的侧壁上。或者,金属表面处理层36也可形成在铜凸块34的侧壁上,如虚线所示。在下文中,凸块下金属层32、铜凸块34、以及金属表面处理层36所组成的结构被称为不可回焊的金属凸块38,这是因为他们都不会在后续用以形成焊料142(请参照图4)的回焊过程中融化。焊料帽(solder cap)40可选择性地形成在不可回焊的金属凸块38上且可包括无铅焊料,无铅焊料例如包含锡银、锡银铜、及其相似物,虽然焊料帽40也可由一共晶焊料(eutectic solder material)所构成,其例如包括铅与锡。
图3A及图3B显示工件100,其可为封装基底,虽然其也可为元件裸片、中介层、或其相似物。工件100可包括接垫110。导电连结(electricalconnections)(例如,线路重布层,未显示)可形成于工件100中的介电层116中,且电性耦接至接垫110。
接垫110包括金属垫122,其可由铜(例如,纯或大抵纯铜)、铝、银、及/或前述的合金形成。在一实施例中,为了形成接垫110,先形成金属垫122。接着,形成防焊层(solder resist)123,并将之图案化以形成防焊层开口132(图3A),其中金属垫122通过防焊层开口132而露出。防焊层123可由高分子形成,其也可为光致抗蚀剂层。防焊层123的厚度T可大于约25μm或大于约50μm,且也可介于约25μm与约100μm之间。可接着例如使用无电镀或电镀法于金属垫122上形成导电缓冲层(conductive barrier layer)124,以作为部分的接垫110。导电缓冲层124可由镍形成,虽然可添加其他的金属/材料层,例如钯(palladium)。
于导电缓冲层124上形成焊球130,其中将焊球拿起并放入防焊层开口132之中。接着,将焊球回焊成焊球130。焊球130可由与图2中的焊料帽40大抵相同的材质或选自同族群的材料而形成,虽然焊料帽40与焊球130的材质也可彼此不同。在一实施例中,如图3A所示,焊球130的高度H1低于防焊层123的厚度T。因此,焊球130埋藏于由防焊层123所定义的防焊层开口132之中。虚线134显示防焊层开口132的边界。在另一实施例中,焊球130的高度H1可等于或微大于厚度T。焊球130的体积可等于或小于防焊层开口132的体积。
在如图3B所示的另一实施例中,焊球130的高度H1大于防焊层123的厚度T。因此,焊球130突出于防焊层123的顶表面。为了形成如图3B所示的焊球130,可将一大焊球的一部分放置于防焊层开口132之中。可接着于焊球上涂布助熔剂(flux),随后进行回焊步骤以熔解大焊球,并使用硬平面于回焊期间压缩大焊球直至大焊球冷却并固化成焊球130。
工件2及工件100可通过倒装芯片接合(flip-chip bonding)而连结,如图4所示。进行回焊工艺以熔解焊球130及焊料帽40(图2)如果有的话,因而形成焊料凸块142以将不可回焊的金属凸块38接合至接垫110。由于不可回焊的金属凸块38与焊料凸块142之间的内部扩散(inter-diffusion),可能会形成金属间化合物(inter-metallic compound,IMC)143。相似地,金属间化合物144也形成于焊料凸块142与接垫110之间的界面处。在随后的讨论中,金属间化合物143及144也解释为焊料凸块142的一部分,且不于后续的附图中显示,虽然它们可能存在于每一说明的实施例之中。
在图4中,焊料凸块142的总体积(其为如图3A所示的焊球130的体积与如图2所示的焊料帽40的体积(如果有的话)的总和)小于防焊层开口132的体积(容量)。因此,不可回焊的金属凸块38可延伸进入防焊层开口132。不可回焊的金属凸块38的底表面44也低于防焊层123的顶表面145。焊料凸块142的高度H2因而小于或等于防焊层123的厚度T。在通篇的叙述中,高度H2等于不可回焊的金属凸块38与接垫110之间的距离。
不可回焊的金属凸块38的水平尺寸W1(其可为长度或宽度)可小于相应的防焊层开口132的水平尺寸W2。在一实施例中,水平尺寸W1介于0.7倍的水平尺寸W2与1倍的水平尺寸W2之间。因此,间隙(gap)146可能存在于防焊层开口132之中,并水平间隔于焊料凸块142与防焊层123的相应边缘。间隙146的宽度W3可例如小于约30μm,或小于约20μm。图5A显示一实施例,其类似于显示于图4中的实施例,除了无间隙存在于防焊层开口132,且使焊料凸块142与防焊层123的相应边缘相间隔。在图5B中,不可回焊的金属凸块38的表面与防焊层123的顶表面齐平或大抵齐平。再者,焊料凸块142的总体积可大抵等于防焊层开口123的体积(容量)。
图6及图7显示实施例的各种变化。显示于图6的实施例类似于显示于图4的实施例,除了不可回焊的金属凸块38的水平尺寸W1大抵等于防焊层开口132的相应水平尺寸W2。显示于图7的实施例相似于显示于图5A的实施例。相同地,不可回焊的金属凸块38的水平尺寸38大抵等于防焊层开口132的相应水平尺寸W2。
图8-图11显示实施例的其他变化。在这些实施例中,防焊层123的厚度T小于焊料凸块142的高度H2。然而,防焊层123的厚度T已增加至超过公知接合结构中的防焊层的厚度,其中公知的防焊层的厚度仅约20μm或更少。再者,厚度T增加至高度H2的约50%或更多。再者,在图8中,存在有间隙146而使焊料凸块142与防焊层123的相应边缘水平隔开,其中宽度W3小于约30μm,或小于约20μm。在图9中,防焊层开口132(未显示于图9,请参照图3A)完全被焊料凸块142填充。在图10中,焊料凸块142可向旁边轻微挤压至不可回焊的金属凸块38的侧壁之上。图11显示一实施例,其中焊料凸块142的侧壁大抵垂直地对准于不可回焊的金属凸块38的相应侧壁。
在实施例中,通过增加防焊层123的高度,使防焊层开口132的体积增加(图3A)。因此,当进行两工件间的接合时,回焊的焊料在水平方向上被防焊层123所局限,且因而提供高垂直力至工件。焊料的局限可造成更均匀的焊料轮廓及较少的焊料破裂。再者,此局限帮助减小裸片弯曲(die warpage)。
虽然本发明已以多个优选实施例公开如上,然其并非用以限定本发明,任何所属技术领域中的普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。
Claims (10)
1.一种集成电路装置,包括:
一第一工件,包括:
一防焊层,位于该第一工件之上,其中该防焊层包括一防焊层开口;以及
一接垫,位于该第一工件之上,且位于该防焊层开口之中;
一第二工件,包括一不可回焊的金属凸块,位于该第二工件之上;以及
一焊料凸块,将该不可回焊的金属凸块接合至该接垫,该焊料凸块的至少一部分位于该防焊层开口之中,且邻接该不可回焊的金属凸块及该接垫,其中该焊料凸块具有一高度,等于该不可回焊的金属凸块与该接垫之间的一距离,且其中该防焊层具有一厚度,大于该焊料凸块的该高度的50%。
2.如权利要求1所述的集成电路装置,其中该不可回焊的金属凸块延伸进入该防焊层开口。
3.如权利要求1所述的集成电路装置,其中该不可回焊的金属凸块的一表面与该防焊层的一表面齐平。
4.如权利要求1所述的集成电路装置,其中该不可回焊的金属凸块的一水平尺寸不大于该防焊层开口的相应的一水平尺寸,且大于该防焊层开口的相应的该水平尺寸的70%。
5.如权利要求1所述的集成电路装置,其中该第一工件为一封装基底,而该第二工件为一元件裸片。
6.一种集成电路装置,包括:
一第一工件,包括:
一接垫;
一防焊层,位于该第一工件之上,其中该防焊层包括一防焊层开口,具有一第一体积;
一接垫,位于该第一工件之上,且位于该防焊层开口之中;以及
一焊料层,位于该接垫之上,且位于该防焊层开口之中,其中该防焊层具有一第二体积,不大于该防焊层开口的该第一体积。
7.如权利要求6所述的集成电路装置,还包括一第二工件,包括一不可回焊的金属凸块于该第二工件的一表面,其中该不可回焊的金属凸块接合至该焊料层。
8.如权利要求7所述的集成电路装置,其中该不可回焊的金属凸块延伸进入该防焊层开口之中。
9.如权利要求7所述的集成电路装置,其中该不可回焊的金属凸块与该接垫之间的一距离等于或小于该防焊层的一厚度。
10.如权利要求7所述的集成电路装置,其中该不可回焊的金属凸块与该接垫之间的一距离大于该防焊层的一厚度。
Applications Claiming Priority (2)
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US12/784,335 US20110285013A1 (en) | 2010-05-20 | 2010-05-20 | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists |
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TWI588960B (zh) * | 2014-05-12 | 2017-06-21 | 英凡薩斯公司 | 導電連接、具有此種連接的結構、及製造方法 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN2538067Y (zh) * | 2002-04-24 | 2003-02-26 | 威盛电子股份有限公司 | 覆晶封装基板 |
CN1499589A (zh) * | 2002-11-04 | 2004-05-26 | 矽统科技股份有限公司 | 覆晶封装制程及其装置 |
US20050026413A1 (en) * | 2002-01-07 | 2005-02-03 | Jin-Yuan Lee | Method of fabricating cylindrical bonding structure |
CN101388376A (zh) * | 2007-09-14 | 2009-03-18 | 全懋精密科技股份有限公司 | 半导体封装基板结构 |
CN101496168A (zh) * | 2006-07-31 | 2009-07-29 | 智识投资基金27有限责任公司 | 用于半导体倒装芯片封装的衬底和过程 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4646618B2 (ja) * | 2004-12-20 | 2011-03-09 | イビデン株式会社 | 光路変換部材、多層プリント配線板および光通信用デバイス |
JP5121574B2 (ja) * | 2008-05-28 | 2013-01-16 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
US8153905B2 (en) * | 2009-02-27 | 2012-04-10 | Ibiden Co., Ltd. | Method for manufacturing printed wiring board and printed wiring board |
-
2010
- 2010-05-20 US US12/784,335 patent/US20110285013A1/en not_active Abandoned
- 2010-08-11 CN CN2010102546977A patent/CN102254869A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050026413A1 (en) * | 2002-01-07 | 2005-02-03 | Jin-Yuan Lee | Method of fabricating cylindrical bonding structure |
CN2538067Y (zh) * | 2002-04-24 | 2003-02-26 | 威盛电子股份有限公司 | 覆晶封装基板 |
CN1499589A (zh) * | 2002-11-04 | 2004-05-26 | 矽统科技股份有限公司 | 覆晶封装制程及其装置 |
CN101496168A (zh) * | 2006-07-31 | 2009-07-29 | 智识投资基金27有限责任公司 | 用于半导体倒装芯片封装的衬底和过程 |
CN101388376A (zh) * | 2007-09-14 | 2009-03-18 | 全懋精密科技股份有限公司 | 半导体封装基板结构 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104471680A (zh) * | 2012-07-16 | 2015-03-25 | 美光科技公司 | 垫上柱体互连结构、半导体裸片及包含所述互连结构的裸片组合件及相关方法 |
CN104471680B (zh) * | 2012-07-16 | 2018-02-16 | 美光科技公司 | 垫上柱体互连结构、半导体裸片、裸片组合件及相关方法 |
TWI582870B (zh) * | 2012-09-19 | 2017-05-11 | 德國艾托特克公司 | 製造經塗佈的銅柱 |
TWI588960B (zh) * | 2014-05-12 | 2017-06-21 | 英凡薩斯公司 | 導電連接、具有此種連接的結構、及製造方法 |
CN108476611A (zh) * | 2016-01-08 | 2018-08-31 | 利罗特瑞公司 | 印刷电路表面抛光、使用方法和由此制成的组件 |
CN108476611B (zh) * | 2016-01-08 | 2021-02-19 | 利罗特瑞公司 | 印刷电路表面抛光、使用方法和由此制成的组件 |
CN109755204A (zh) * | 2017-11-06 | 2019-05-14 | 台湾积体电路制造股份有限公司 | 微连接结构及其制造方法 |
CN109755204B (zh) * | 2017-11-06 | 2023-05-16 | 台湾积体电路制造股份有限公司 | 微连接结构及其制造方法 |
CN110691459A (zh) * | 2018-07-05 | 2020-01-14 | 同泰电子科技股份有限公司 | 利用防焊限定开窗形成连接端子的电路板结构 |
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