TWI723140B - 經封裝裝置以及形成經封裝裝置的方法 - Google Patents

經封裝裝置以及形成經封裝裝置的方法 Download PDF

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TWI723140B
TWI723140B TW106107789A TW106107789A TWI723140B TW I723140 B TWI723140 B TW I723140B TW 106107789 A TW106107789 A TW 106107789A TW 106107789 A TW106107789 A TW 106107789A TW I723140 B TWI723140 B TW I723140B
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dielectric layer
layer
hole
fan
conductive
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TW106107789A
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TW201826482A (zh
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普翰屏
李孝文
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台灣積體電路製造股份有限公司
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Priority claimed from US15/360,739 external-priority patent/US10269720B2/en
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明實施例提供一種經封裝裝置，所述經封裝裝置包括一第一介電層、一第二介電層以及一第三介電層。所述第二介電層形成於所述第一介電層之上，包括一裝置基板及從所述第一介電層延伸且穿過所述第二介電層的一通孔。所述第三介電層形成於所述第二介電層之上，包括延伸穿過所述第三介電層的一導電柱，其中所述導電柱電性耦合至所述第二介電層的所述通孔。

Description

經封裝裝置以及形成經封裝裝置的方法
本發明是有關於一種經封裝裝置以及形成經封裝裝置的方法。
自積體電路的發明以來，半導體行業已因各種電子元件(例如，電晶體、二極體、電阻器、電容器等)的集成密度不斷提高而經歷持續快速的發展。很大程度上，集成密度上的這些提高來源自於最小特徵尺寸(minimum feature size)的不斷減小，這使得更多元件能夠集成至一給定晶片區域中。
這些集成上的提高基本上是二維(two-dimensional，2D)性質的，因為集成元件佔據的體積基本上位於半導體晶片的表面上。儘管微影的明顯改善已使得二維積體電路的形成得到相當大的改善，然而，可在二維中實現的密度存在實體限制。這些限制的其中之一是製作這些元件所需要的最小尺寸。此外，當將更多裝置設置於一個晶片中時，需要更複雜的設計。另一限制源自於各裝置之間的內連線的數目及長度會隨著裝置數量的增加而顯著增加。 當內連線的數目及長度增加時，電路阻容延遲(RC delay)及功耗二者均會增大。
三維積體電路(three-dimensional integrated circuit，3DIC)據此而形成，其中可堆疊有兩個晶粒或封裝件，在所述晶粒或封裝件的其中之一中形成有將另一晶粒連接至另一基板的矽穿孔(through-silicon via，TSV)。疊層封裝(Package on Package，PoP)因能夠實現更高密度的電子產品而正成為日益流行的積體電路封裝技術。然而，傳統的疊層封裝一般需要利用混合耦合方法(例如，球柵陣列封裝(ball grid array，BGA)方法與打線接合(wire bonding)方法的組合)來堆疊兩個或更多個晶粒或封裝件。因此，可能對封裝晶粒/封裝件的各種特性(例如，電性接點的數目、電性能、抗撓性(stiffness)等)產生不利影響。
本發明實施例提供一種經封裝裝置以及形成經封裝裝置的方法，其可增加在有限基板面上電性接點的數目及降低所形成的電性連接路徑的阻抗。
本發明實施例的經封裝裝置包括第一介電層、第二介電層及第三介電層。第二介電層形成於所述第一介電層之上，並包括裝置基板及從所述第一介電層延伸且穿過所述第二介電層的通孔。第三介電層形成於所述第二介電層之上，並包括延伸穿過所述第三介電層的導電柱，其中所述導電柱電性耦合至所述第二介電層 的所述通孔。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
100、800:方法
102、104、106、108、110、112、114、116、118、120、122、124、126、612、614、616、618、620、802、804、806、808、810、812:操作
200:載體基板/第一載體基板
202:第一介電層/介電層
204:圖案化掩膜層
205、217:開口
206、212-2、315、319、415、506-1、515、519、916-2、1008:通孔
208、308-1、308-2、408、508-1、508-2、702、752、910、1002:裝置基板
208-1、208-2、208-3、208-4、208-5、208-6、508-3、508-4:電性接點
209:層
210、510-1、914:第二介電層
212:重佈線層/介電層
212-1、212-3、313、317、413、513、517、916-1:導線
213、410、917:介電層
214:焊料接點/球柵陣列封裝焊球
216:第二載體基板/載體基板
218:導電柱/銅柱/嵌置銅柱
218d:深度
218w:寬度
250:封裝件
260、300、400、500、900:扇出型結構
301:子扇出型結構
302、502:第一介電層
303:子扇出型結構/頂部扇出型結構
310-2:介電層/層
312-2、412、512-1、512-2、916:重佈線層
318:嵌置銅柱/銅柱
320、520、420、704、754、906、1004:蓋層
322、522、422:黏合層
414:焊料接點
501、503、505、507、700、750、1000:子扇出型結構
510-2:介電層/第二介電層
518:嵌置銅柱/銅柱
601:第一結構/結構
601-1、603-1:第一部分/介電材料
601-2、603-2:第二部分/導電材料
601B:底表面/表面
603:第二結構/結構
603T:頂表面/表面
702-1、702-2、702-3、702-4:側
706、706-1、706-2、706-3、706-4、706-5、706-6、706-7、706-8、706-9、706-10、706-11、706-12、706-13、706-14、706-15、706-16、706-17、706-18、706-19、706-20、706-21、706-22、706-23、706-24、706-25、706-26、706-27、706-28、706-29、706-30、706-31、706-32、706-33、706-34、706-35、706-36、706-37、706-38、706-39、706-40、706-41、706-42、706-43、706-44、706-45、706-46、706-47、706-48:柱
708、909、1005:管腔
756:突出的結構/蜂巢式柵格
758:六邊形單元/管腔
902:載體基板
904:第一介電層/介電層
907:頂表面
908:突出的結構/通孔
910-1、910-2、910-3、910-4:電性接點/接點
912:晶粒貼合膜
918:球柵陣列封裝焊球/焊料接點
1006:突出的結構
1007:孔
A、B:輪廓線
圖1是根據本發明某些實施例的堆疊有一個或多個扇出型結構的經封裝裝置基板(封裝件)的製作方法的流程圖。
圖2A、圖2B、圖2C、圖2D、圖2E、圖2F、圖2G、圖2H、圖2I、圖2J、及圖2K根據本發明某些實施例說明經封裝裝置基板(封裝件)在各種製作階段的剖視圖。
圖2L根據本發明某些實施例說明堆疊有扇出型結構的經封裝裝置基板(封裝件)的剖視圖。
圖3根據本發明某些實施例說明圖2K所示的示例性扇出型結構的剖視圖。
圖4根據本發明某些實施例說明圖2K所示的另一示例性扇出型結構的剖視圖。
圖5根據本發明某些實施例說明圖2K所示的又一示例性扇出型結構的剖視圖。
圖6A根據本發明某些實施例說明通過混合接合技術而彼此耦合的兩個結構的剖視圖。
圖6R根據本發明某些實施例說明用於混合接合兩個結構的方法的示例性流程圖。
圖7A及圖7B根據本發明某些實施例分別說明兩個蓋(lid)層的示例性佈局的俯視圖。
圖8根據本發明某些實施例說明用於形成包括圖7A或圖7B所示蓋層的子扇出型(fan-out，FO)結構的方法的示例性流程圖。
圖9A、圖9B、圖9C、圖9D、圖9E、及圖9F根據本發明某些實施例說明通過圖8所示方法製作的子扇出型結構在各種製作階段的剖視圖。
圖10根據本發明某些實施例說明另一蓋層的示例性佈局的俯視圖。
所有圖式均為示意性的且並非按比例繪製。
以下公開內容提供用於實作本發明實施例的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複參考編號及/或字母。這種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下」(beneath)、「下面」(below)、「下部的」(lower)、「上方」(above)、「上部的」(upper)等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。裝置可具有其他方位(旋轉90度或處於其他方位)且本文中所用的空間相對性描述語可同樣相應地進行解釋。另外，應理解，當稱一元件「連接至」(connected to)或「耦合至」(coupled to)另一元件時，所述元件可直接連接至或直接耦合至所述另一元件，抑或可存在一個或多個中間元件。
現在參照圖1，根據本發明實施例的各種態樣說明封裝半導體裝置(晶片)的方法100的流程圖。方法100僅為實例，且並不旨在限制本發明實施例。根據所述方法的又一些實施例，可在方法100之前、期間、及之後提供其他操作，且所述操作中的某些操作可被依序替換、去除、或改變。
以下結合用於對封裝半導體晶片/裝置基板的部分在各種製作階段的剖視圖進行說明的圖2A、圖2B、圖2C、圖2D、圖2E、圖2F、圖2G、圖2H、圖2I、圖2J、及圖2K來闡述方法100。所述裝置基板可為在對積體電路或積體電路的一部分進行加工及/或封裝期間製作的中間裝置，所述中間裝置可包括：靜態隨機存取記憶體(static random access memory，SRAM)及/或其他邏輯電路；被動元件，例如電阻器、電容器、及電感器；以及主動元件，例如 p型場效電晶體(p-type FET，PFET)、n型場效電晶體(n-type FET，NFET)、鰭型場效電晶體(FinFET)、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistor，MOSFET)、互補金屬氧化物半導體(complementary metal-oxide semiconductor，CMOS)電晶體、雙極電晶體、高壓電晶體、高頻電晶體、其他記憶體單元及/或其組合。
如圖2A中所示，經封裝裝置的製作方法100開始於操作102並繼續進行至操作104，在操作102中提供載體基板200，在操作104中在載體基板200上形成第一介電層202。在某些實施例中，可以多種方式實現載體基板200。例如，載體基板200可包括晶粒導線架(die lead frame)、印刷電路板(printed circuit board，PCB)、多晶片封裝件基板或其他類型的基板。
仍然參照圖2A，在某些實施例中，第一介電層202是由選自以下的材料所形成：聚醯亞胺、聚苯並惡唑(polybenzoxazole，PBO)、聚苯並惡唑系介電材料、苯環丁烷(benzocyclobutene，BCB)、苯環丁烷系介電材料或其組合。在某些實施例中，儘管對於其他實施例可使用第一介電層202的任何所期望厚度，然而第一介電層202可具有約2微米至10微米(μm)的厚度。如以下進一步詳細論述，所述第一介電層202的形成可用於形成對通孔及/或半導體晶片提供直接電性連接的一個或多個導電柱。如以下進一步詳細論述，由這些材料及厚度形成的第一介電層202可幫助減少翹曲(warpage)、減少熱係數不匹配(thermal coefficient mismatch)及 增加引腳數目等。
再次參照圖1，根據多種實施例，方法100繼續進行至操作106。在操作106中，在第一介電層202上形成圖案化掩膜層204(圖2B)。圖案化掩膜層204定義出開口205，所述開口205用於進一步定義隨後形成的通孔的形狀，所述通孔是通過以導電材料填充開口205而形成。在圖2B所示的說明實施例中，圖案化掩膜層204可包括圖案化光刻膠掩膜、硬掩膜及其組合等。
現在參照圖1及圖2C，方法100繼續進行至操作108，在操作108中通過以導電材料填充開口205(圖2B)且在此後移除圖案化掩膜層204(圖2B)的方式而在第一介電層202上形成一個或多個通孔206。可使用例如以下各種導電材料中的任一種來形成通孔206：例如，銅(Cu)、鎳(Ni)、鉑(Pt)、鋁(Al)、無鉛焊料(例如，SnAg、SnCu、SnAgCu)或其組合。在以下所描述的實施例中，通孔206可包含至少銅。就填充所述開口來說，可使用例如以下各種方式中的任一種：電鍍、物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積(chemical vapor deposition，CVD)、電氣化學沉積(electrochemical deposition，ECD)、分子束磊晶(molecular beam epitaxy，MBE)、原子層沉積(atomic layer deposition，ALD)等。應注意的是，在某些實施例中，例如在圖案化掩膜層及第一介電層的整個表面上沉積共形層的那些實施例(例如，物理氣相沉積及化學氣相沉積)中，可以期望執行蝕刻或平坦化製程(例如，化學機械拋光(chemical mechanical polishing， CMP)製程)，以從圖案化掩膜層204的表面移除過量的導電材料。在以上述材料(例如，銅)填充所述開口之後，可隨後通過例如以下等化學溶液來移除(剝除)圖案化掩膜層204：例如乳酸乙酯、苯甲醚、甲基丁基乙酸酯、乙酸戊酯、甲酚酚醛清漆樹脂(cresol novolak resin)、及重氮光敏化合物(稱作SPR9)的混合物；溶劑(例如，二甲基亞碸(dimethyl sulfoxide，DMSO))、堿(例如，氫氧化鉀KOH或四甲基氫氧化銨(tetramethylammonium hydroxide，TMAH))、表面活性添加劑或其組合的混合物。
現在參照圖1及圖2D，根據多種實施例，方法100繼續進行至操作110，在操作110中，將裝置基板208耦合至第一介電層202並設置於各通孔206之間。裝置基板208可包括可進行內連接而形成一個或多個積體電路的一個或多個微電子裝置/奈米電子裝置，例如：電晶體、電子可複寫唯讀記憶體(electrically programmable read only memory，EPROM)單元、電子抹除式可複寫唯讀記憶體(electrically erasable programmable read only memory，EEPROM)單元、靜態隨機存取記憶體(static random access memory，SRAM)單元、動態隨機存取記憶體(dynamic random access memory，DRAM)單元及其他微電子裝置。裝置基板208慮及一個或多個傳統的或未來開發的微電子裝置/奈米電子裝置。裝置基板208的主體可為絕緣體上矽(silicon-on-insulator，SOI)基板及/或可包含矽、砷化鎵、應變矽、矽鍺、碳化物、金剛石及其他材料。
仍然參照圖2D，在某些實施例中，將裝置基板208接合 至第一介電層202。更具體來說，利用例如晶粒貼合膜(die attach film，DAF)或其他黏合層將裝置基板208的背側(例如，與電性接點208-1至208-6相對的側)設置於第一介電層202上。在圖2D所示的所說明實施例中，層209可包括例如晶粒貼合膜。
現在參照圖1及圖2E，根據多種實施例，方法100繼續進行至操作112，在操作112中，在裝置基板208上形成第二介電層210。在某些實施例中，第二介電層210可包含模製化合物(molding compound)。例如，第二介電層210是由選自以下的材料而形成：環氧樹脂模製化合物(epoxy molding compound，EMC)材料、模製底部填充(molded underfill，MUF)材料、味之素增層膜(ajinomoto build-up film，ABF)材料、味之素增層膜系材料、樹脂材料或其組合。在某些實施例中，可利用以下中的至少一者來形成第二介電層210：物理氣相沉積(PVD)、化學氣相沉積(CVD)、原子層沉積(ALD)、電氣化學沉積(ECD)、分子束磊晶(MBE)或其組合。儘管在其他實施例中可使用具有任何所期望厚度的第二介電層，然而，在某些實施例中，所述第二介電層可具有約100微米~300微米(μm)的厚度。第二介電層的厚度一般是取決於裝置基板的高度。更具體來說，第二介電層的厚度會選擇成比裝置基板的高度厚。可以期望在某些實施例中執行蝕刻或平坦化製程(例如，化學機械拋光(CMP)製程)，以從裝置基板208的電性接點208-1的頂表面及/或通孔206的頂表面移除如上所述的過量的材料，從而暴露出所述頂表面。
現在參照圖1及圖2F，根據多種實施例，方法100繼續進行至操作114，在操作114中，在第二介電層210之上形成重佈線(redistribution line，RDL)層212。根據實施例，形成重佈線層212以對通孔206及裝置基板208提供電性連接及/或在通孔206與裝置基板208之間提供電性連接。如圖2F中所示，可在重佈線層212內形成一個或多個導線(例如，212-1)以對通孔206及裝置基板208提供電性連接及/或在通孔206與裝置基板208之間提供電性連接。在某些實施例中，重佈線層212可包括由導電材料(例如，銅)形成的通孔212-2，以對導線212-1及焊料接點提供電性連接及/或在導線212-1與焊料接點之間提供電性連接，此將在圖2G中進行描述。
仍然參照圖2F，重佈線層212可包括其中形成有導電層(例如，導線212-1、通孔212-2等)的介電層213(例如，保護層)。介電層213可包含例如聚合物材料(例如，環氧樹脂(epoxy)、聚醯亞胺、聚苯並惡唑(PBO)等)或者可由通過例如旋轉塗佈(spin coating)等任何適合的方法而形成的眾所周知的介電材料(例如，旋塗式玻璃(spin-on glass)、氧化矽、氮氧化矽等)形成。在某些實施例中，可通過以下製程中的至少其中之一來形成重佈線層212：如圖2F中所示，首先在第二介電層210之上設置導線212-1以對各通孔206提供期望的連接及/或在各通孔206之間提供期望的連接；接著在導線212-1及第二介電層210之上設置介電層212；隨後在介電層213內形成通孔212-2，以形成重佈線層212。在形成 重佈線層212(操作114)之後，可執行蝕刻或平坦化製程(例如，化學機械拋光(CMP)製程)以移除過量的重佈線層212，從而暴露出通孔212-2的頂表面。
在某些替代實施例中，如圖2G的實施例中所示，除導線212-1及通孔212-2以外，重佈線層212可進一步包括設置於通孔212-2上方的一個或多個導線212-3。依上述製程步驟以形成重佈線層212，可在形成通孔212-2之後形成導線212-3。例如，在介電層213內形成通孔212-2之後，將各導線212-3分別設置於介電層213之上以與相應的通孔212-2對齊。
現在參照圖1及圖2H，根據多種實施例，方法100繼續進行至操作116，在操作116中，在重佈線層212的頂表面上形成一個或多個焊料接點214。如以下參照圖2I進一步詳細論述，可利用任何熟知的技術來形成焊料接點214，以對重佈線層212及另一載體基板或層提供電性連接及/或在重佈線層212與另一載體基板或層之間提供電性連接。儘管在圖2H所示的實施例中，焊料接點214呈球體系形狀(例如，焊球)，然而焊料接點214可形成為適合於在兩個接觸結構或接觸點之間提供電接觸的各種形狀。在某些實施例中，焊料接點214可由金(Au)、銀(Ag)、鎳(Ni)、鎢(W)、鋁(Al)及/或其合金形成。
現在參照圖1及圖21，根據多種實施例，方法100繼續進行至操作118，在操作118中，從第一介電層202移除並解耦第一載體基板200，且將第二載體基板216耦合至焊料接點214。與 第一載體基板200相似，第二載體基板216可包括晶粒導線架、印刷電路板(PCB)、多晶片封裝件基板或其他類型的基板。
現在參照圖1及圖2J，根據多種實施例，方法100繼續進行至操作120，在操作120中在第一介電層202中形成一個或多個開口217。如圖2I中所示，可使開口217與通孔206對齊。所述形成開口217可包括例如以下一個或多個過程：在第一介電層202之上形成圖案化掩膜層，其中所述圖案化掩膜層可包括與開口217對齊的一個或多個開口；利用圖案化掩膜層蝕刻第一介電層202；移除圖案化掩膜層；以及此後執行清潔製程。
現在參照圖1及圖2K，根據多種實施例，方法100繼續進行至操作122，在操作122中，以導電材料填充開口217。填充導電材料是用於在第一介電層202中形成一個或多個導電柱218。儘管，在某些實施例中，用於填充開口217的導電材料為銅，然而在仍處於本發明實施例的範圍內的同時可使用各種導電材料中的任一種。當將銅填充至開口217中時，會形成一個或多個銅柱218，且相應地，如圖2K中所示，方法100繼續進行至操作124，並在操作124中形成封裝件250。
仍然參照圖2K，在封裝件250內形成(即，在封裝件250中嵌置)銅柱218。在某些實施例中，銅柱充當電性接點以將封裝件250直接耦合至附加封裝件/裝置基板/載體基板(在下文中稱作“扇出型(fan-out,FO)結構”)。利用所揭露的方法100形成其中嵌置有銅柱218的封裝件250相對於通過傳統封裝方式(例如， 疊層封裝(PoP)、球柵陣列封裝(BGA)等)而形成的封裝件可提供例如以下多種優點：例如，增加封裝件的引腳(即，電性接點)的數目、降低交流電(alternative current，AC)阻抗等，將在以下進一步詳細論述。
在某些實施例中，可通過以例如以下多種方式中的任一種來填充開口217而形成銅柱：例如，電鍍、物理氣相沉積(PVD)、化學氣相沉積(CVD)、電氣化學沉積(ECD)、分子束磊晶(MBE)、原子層沉積(ALD)等。應注意，在某些實施例中，例如在那些在第一介電層202的整個表面之上沉積共形層(例如，物理氣相沉積及化學氣相沉積)的實施例中，可以期望執行蝕刻或平坦化製程(例如，化學機械拋光(CMP)製程)，以從第一介電層202的表面移除過量的導電材料(即，當前實施例中的銅)。
在某些實施例中，通過將銅填充至第一介電層202的開口217中而形成銅柱218，開口217的深度218d約為2μm~10μm(即，第一介電層202的厚度)且寬度218w約為20μm~200μm。開口217的寬度218w可取決於例如以下多種設計參數：裝置基板208的節距(pitch)大小、裝置基板208與其內連線之間的佈局等。由於可通過一種或多種(光)微影方法來精確地定義開口的大小(例如，寬度218w)，因此，可實現電性接點(即，銅柱218)的更精細尺寸，此進而會增加在在具有有限基板面(real estate)的積體電路晶片上可能設置的電性接點的數目。另外，在某些實施例中，由於用以電性連接裝置基板208的通孔206是由銅形成， 因此，利用銅柱218作為電性接點以對可形成的附加扇出型結構進行堆疊(電性耦合)可降低電性接點的交流電阻抗及/或包括此種電性接點的電性連接路徑的交流電阻抗。
如上所述，所公開的流程圖(從操作102到124)提供具有上述優點的用於形成封裝件250的方法，封裝件250具有能夠使得其他扇出型結構堆疊(電性耦合)至封裝件250的一個或多個嵌置銅柱218。參照圖1及圖2L，根據多種實施例，方法100繼續進行至操作126，在操作126中通過銅柱218而將一個或多個扇出型結構260堆疊至封裝件250上且電性耦合至封裝件250。在某些實施例中，扇出型結構260可實質上相似於封裝件250且可至少部分地利用所公開的方法100來形成。以下將參照圖3、圖4及圖5來分別描述扇出型結構260的多種實施例。在某些實施例中，可通過混合接合技術而將所述各種扇出型結構260耦合至封裝件250。以下將參照圖6A及圖6B進一步詳細論述此種混合接合技術。
圖3根據多種實施例說明可耦合至封裝件250(圖2J)的扇出型結構300的示例性實施例。在圖3所說明的實施例中，扇出型結構300包括兩個子扇出型結構301及303。除子扇出型結構301及303不包括焊料接點(例如，214)及所貼合的載體基板(例如，216)以外，這兩個子扇出型結構實質上相似於封裝件250。此外，子扇出型結構303包括蓋層320。為簡潔起見，將不再對子扇出型結構301及303的與封裝件250相似的組件予以贅述。例 如，子扇出型結構301包括其中形成有嵌置銅柱318的第一介電層302、其中形成有裝置基板308-1及通孔306-1的第二介電層310-1、以及其中形成有導線313及通孔315的重佈線層312-1。子扇出型結構303包括其中形成有裝置基板308-2的介電層310-2(相似於第二介電層210及310-1)以及其中形成有導線317及通孔319的重佈線層312-2。在某些實施例中，若不存在將要耦合至頂部扇出型結構(例如，子扇出型結構303)的附加扇出型結構，則此頂部扇出型結構不需要包括形成於其「介電層」(例如層310-2)內的通孔。但所述頂部扇出型結構可包括沿裝置基板及介電層的底表面形成的蓋層320，其中在所述底表面與蓋層320之間具有黏合層。例如，在圖3中，子扇出型結構303為頂部扇出型結構。如圖3中所示，子扇出型結構303包括蓋層320及形成於裝置基板308-2與蓋層320之間的黏合層322。在某些實施例中，蓋層320可由金屬板(例如，銅板)形成，且黏合層322可包含晶粒貼合膜(DAF)、晶種層、焊料層及/或其他適合的樹脂材料。在某些實施例中，晶種層可由例如鈦(Ti)、鎳(Ni)等材料形成，並且焊料層可由例如錫(Sn)、銀(Ag)、銅(Cu)等材料形成。
仍然參照圖3，子扇出型結構301及303可利用方法100中的具有一個或多個替代操作的至少部分來形成。更具體來說，封裝件250與子扇出型結構301及303可平行地(即，同時)形成，從而可使得將扇出型結構300堆疊(電性耦合)至封裝件250的整個包裝過程加快。例如，重新參照圖1，儘管封裝件250是利用 方法100而形成，然而子扇出型結構301是在同時利用從102到122的操作但省略操作116(即，耦合各焊料接點214)及操作118的部分(即，省略操作118中的“耦合至第二載體基板”)而形成。並且子扇出型結構303也同時利用以下步驟而形成：操作110，在操作110中通過黏合層322而將裝置基板308-2耦合至蓋層320(即，並非耦合至第一介電層(例如，202))；可選步驟，在所述可選步驟中為實現最優化的熱耦合效果而在裝置基板308-2的頂表面之上形成熱介面材料(thermal interface material，TIM)層(例如，熱膠層、熱脂層等)；操作112(即，形成介電層310-2)；以及操作114(即，形成重佈線層312-2)。作為替代性的選擇或者附加的選擇，在某些實施例中，在操作114之後，可在重佈線層312-2的頂表面之上形成一個或多個球柵陣列封裝焊球且所述一或多個球柵陣列封裝焊球分別與相應的通孔319對齊，從而使所述球柵陣列封裝焊球可分別充當電性接點。
具有嵌置銅柱的封裝件/扇出型結構(通過方法100而形成)可為另一將要耦合的扇出型結構提供電性接點(即，銅柱)，所述電性接點可相應地提供如上所述的多種優點。在圖3所示的實施例中，子扇出型結構301可通過將通孔315耦合至封裝件250的嵌置銅柱218而直接(電性)耦合至封裝件250，且相似地，頂部扇出型結構303可通過將通孔319耦合至子扇出型結構301的嵌置銅柱318而電性耦合至子扇出型結構301。在某些替代實施例中，除銅柱318以外，可使用各種電性接點中的任一種將子扇出 型結構301耦合至另一扇出型結構。例如，所述各種電性接點包括焊料柱、球柵陣列封裝焊球(例如，214)等，所述焊料柱由銅(Cu)、錫(Sn)、銀(Ag)、鉍(Bi)、或其組合製成。在某些實施例中，所述各種電性接點可利用鐳射鑽孔(laser-drilling)方法、乾式蝕刻方法、焊料鍍覆方法、微球安裝方法等而形成於第一介電層302上及/或第一介電層302內。
圖4根據多種實施例說明將耦合至封裝件250(圖2J)扇出型結構400的另一示例性實施例。除在某些實施例中扇出型結構400可進一步包括耦合至通孔415的焊料接點414以外，扇出型結構400實質上相似於子扇出型結構303。更具體來說，相似於子扇出型結構303，扇出型結構400包括其中形成有裝置基板408的介電層410(相似於圖3所示的介電層310-2)、其中形成有導線413及通孔415的重佈線層412、蓋層420及黏合層422。焊料接點414可實質上相似於焊料接點214(圖2G至圖2K)。在圖4所說明的實施例中，焊料接點414與形成於重佈線層412內的通孔415對齊，且更具體來說，焊料接點414被形成為將扇出型結構400耦合至封裝件250的銅柱218(圖2J)。也就是說，當扇出型結構400耦合至封裝件250時，焊料接點414與銅柱218可彼此連接從而提供電性導通路徑。
圖5根據多種實施例說明將耦合至封裝件250(圖2J)的扇出型結構500的又一示例性實施例。扇出型結構500包括四個子扇出型結構501、503、505、及507。子扇出型結構501與子 扇出型結構503當組合於一起時實質上相似於圖3所示的子扇出型結構301。子扇出型結構505與子扇出型結構507當組合於一起時實質上相似於圖3所示的子扇出型結構303。更具體來說，子扇出型結構501包括其中形成有導線513及通孔515的重佈線層512-1。子扇出型結構503包括其中形成有嵌置銅柱518的第一介電層502及其中形成有裝置基板508-1及通孔506-1的第二介電層510-1。子扇出型結構505包括其中形成有導線517及通孔519的重佈線層512-2。子扇出型結構507包括其中形成有裝置基板508-2的介電層510-2(相似於310-2)、蓋層520及黏合層522，其中蓋層520形成於黏合層522及第二介電層510-2頂上。不同於圖3所示的實施例，在某些實施例中，這四個子扇出型結構501、503、505、及507可利用如以上參照圖3所闡述的操作的各別組合來形成。如此一來，這四個子扇出型結構501、503、505、及507可同時形成，並且，相應地，將扇出型結構500堆疊至封裝件250的過程可進一步加快。在某些實施例中，子扇出型結構507可通過將裝置基板508-2的電性接點508-4耦合至導線517而電性耦合至子扇出型結構505，子扇出型結構505可通過將通孔519耦合至子扇出型結構503的銅柱518而電性耦合至子扇出型結構503，子扇出型結構503可通過將通孔506-1及/或裝置基板508-1的電性接點508-3耦合至導線513而電性耦合至子扇出型結構501。如此一來，子扇出型結構501、503、505、及507彼此電性耦合。
基於以上論述，可看出本發明實施例提供多種優點。然而， 應理解，本文中未必論述所有優點，且其他實施例可提供不同優點，並且對於所有實施例來說並不需要特定優點。
圖6A根據多種實施例說明將要利用上述混合接合技術進行耦合(即，接合)的兩個示例性結構的剖視圖。如圖所示，第一結構601包括底表面601B且第二結構603包括頂表面603T。此外，第一結構601包括由一種或多種介電材料(例如，用於形成第一介電層202及第二介電層210的材料)所形成的第一部分601-1以及由一種或多種導電材料(例如，銅)所形成的第二部分601-2。相似地，第二結構603包括由一種或多種介電材料(例如，用於形成第一介電層202及第二介電層210的材料)形成的第一部分603-1以及由一種或多種導電材料(例如，銅)形成的第二部分603-2。本文中使用的用語「混合接合技術」意指當兩個表面/結構將要彼此接合時，每一將要接合的表面至少包含彼此不同的第一材料與第二材料。並且當被接合時，所述兩個表面/結構中的相應的第一材料彼此接合，且所述兩個表面/結構中的相應的第二材料彼此接合。
在某些實施例中，再次參照圖3，分別利用混合接合技術，可使得子扇出型結構301接合至封裝件250且可使得子扇出型結構303接合至子扇出型結構301。更具體來說，當子扇出型結構301接合至封裝件250時，通孔315接合至銅柱218且子扇出型結構301的介電層312-2與封裝件250的介電層202彼此接合；當子扇出型結構303接合至子扇出型結構301時，通孔319接合至 銅柱318，且子扇出型結構303的介電層312-2與子扇出型結構301的第一介電層302彼此接合。
圖6B根據多種實施例說明用於執行混合接合技術的方法610的示例性流程圖。由於可在分別包含兩種不同材料的任何兩個結構/表面上執行方法610，因此，為簡潔起見，將結合圖6A所示的示例性結構601及603來提供以下對方法610的論述。在某些實施例中，方法610開始於操作612，在操作612中通過一個或多個清潔製程(例如，RCA清潔製程)及/或一個或多個等電漿製程來處理所述兩個表面601B及603T。方法610繼續進行至操作612，在操作612中使所述兩個結構601與603對齊，以使結構601及603的導電材料(例如，601-2及603-2)分別彼此對齊，這會使結構601及603的介電材料(例如，601-1及603-1)也彼此對齊。此外，在某些實施例中，在操作614期間，將結構601及603二者放置於被預熱至第一升高溫度(例如，約100℃)的腔室中，從而使表面601B及603T活化。方法610接著繼續進行至操作616，在操作616中在將表面601B與表面603T放置成實質上彼此靠近的同時，將腔室加熱至第二升高溫度(例如，約150℃)。如此一來，表面601B與表面603T可發生接觸且介電材料601-1與介電材料603-1可彼此接合。方法610接著繼續進行至操作618，在操作618中將腔室加熱至第三升高溫度(例如，約200℃~250℃)，從而使導電材料601-2與導電材料603-2彼此接合。方法610繼續進行至操作620，在操作620中為了退火(annealing)而將腔 室冷卻。
在某些實施例中，可以多種形狀/配置中的任一種來形成上述蓋層(例如，圖3所示的320、圖4所示的420、圖5所示的520等)。圖7A及圖7B分別說明兩個蓋層的示例性佈局的俯視圖。圖7A及圖7B中的佈局的所述兩個俯視圖均分別以倒置形式示出。如圖7A中所示，子扇出型結構700(或頂部扇出型結構)包括裝置基板702及蓋層704。在某些實施例中，將蓋層704貼合至裝置基板702的底表面(面對裝置基板702的平面的表面)。更具體來說，蓋層704進一步包括環繞裝置基板702且延伸出/突出於所述平面的多個柱706。在某些實施例中，柱706分別由例如(例如，銅)等與蓋層704實質上相似的金屬材料所形成。
在某些實施例中，將所述多個柱706依分別環繞裝置基板702的一個或多個輪廓線(contour)而排列，且此一種輪廓線包括用於在其中實體地設置裝置基板702的管腔(lumen)(例如，708)。在圖7A所示的示例性佈局中，裝置基板702具有方形形狀。如此一來，可相應地將所述多個柱706佈局成方形形狀的輪廓線。應注意，裝置基板702可具有多種形狀(例如，矩形、圓形、三角形等)中的任一種，此可相應地使得所述多個柱706排列成分別具有用於環繞裝置基板702的對應形狀的一個或多個輪廓線。
更具體來說，在其中將柱706佈局成一個或多個方形形狀的輪廓線(圖7A所示的A及B)的實例中，輪廓線「A」是由 第一柱子集(706-1、706-2、706-3、706-4、706-5、706-6、706-7、706-8、706-9、706-10、706-11、706-12、706-13、706-14、706-15、706-16、706-17、706-18、706-19、706-20等)所形成，且輪廓線「B」是由第二柱子集(706-21、706-22、706-23、706-24、706-25、706-26、706-27、706-28、706-29、706-30、706-31、706-32、706-33、706-34、706-35、706-36、706-37、706-38、706-39、706-40、706-41、706-42、706-43、706-44、706-45、706-46、706-47、706-48等)所形成。第一柱子集(即，輪廓線A)可進一步劃分成四個組，其中每一組均被配置成沿裝置基板702的一側對齊。例如，第一組柱(例如，706-1、706-2、706-3、706-4、706-5及706-6)與裝置基板702的側702-1對齊；第二組柱(例如，706-7、706-8、706-9及706-10)與裝置基板702的側702-2對齊；第三組柱(例如，706-11、706-12、706-13、706-14、706-15及706-16)與裝置基板702的側702-3對齊；第四組柱(例如，706-17、706-18、706-19及706-20)與裝置基板702的側702-4對齊。在某些實施例中，第二柱子集(即，輪廓線B)可進一步劃分成四個組，其中每一組均被配置成沿裝置基板702的一側對齊。由於輪廓線B的佈局實質上相似於輪廓線A，因此為清晰起見，不再對輪廓線B予以贅述。
圖7B說明子扇出型結構750的包括裝置基板752及貼合至裝置基板752的底表面的蓋層754的部分。在圖7B所示的實施例中，蓋層754包括被形成為蜂巢式構造的多個突出的結構756。 更具體來說，所述多個突出的結構756被形成為多個六邊形單元(例如，758)的側壁。所述多個六邊形單元中的每一者具有橫截面呈六邊形形狀的三維中空空間，從而使得所述多個突出的結構756形成蜂巢式柵格。在某些實施例中，此一種蜂巢式柵格可包括用於在其中實體地設置裝置基板752的管腔(例如，758)。
應注意，圖7A所示的顯示輪廓(contoured)的柱結構及圖7B所示的蜂巢式結構均僅為用於說明扇出型結構的蓋層所可包括的其他結構的某些實施例的實例。在某些其他實施例中，在仍處於本發明實施例的範圍內的同時，蓋層可包括環繞裝置基板的多種附加結構中的任一種。
現在參照圖8，根據本發明實施例的多種實施例提供用於製作包括具有上述結構(例如，圖7A所示的顯示輪廓的柱結構、圖7B所示的蜂巢式結構等)的蓋層的扇出型結構900的方法800的示例性流程圖。以下結合用於對扇出型結構900的部分在各種製作階段處的剖視圖進行說明的圖9A、圖9B、圖9C、圖9D、圖9E、及圖9F來闡述方法800。
方法800開始於操作802，在操作802中設置載體基板902。更具體來說，如圖9A中所示，以蓋層906至少部分地覆蓋載體基板902，在蓋層906與載體基板902之間形成第一介電層904。在某些實施例中，首先在載體基板902之上形成第一介電層904，且接著在第一介電層904之上形成蓋層906從而覆蓋載體基板902。在某些實施例中，可以多種方式來實現載體基板902。例 如，載體基板902可包括晶粒導線架、印刷電路板(PCB)、多晶片封裝件基板或其他類型的基板。
在某些實施例中，第一介電層904是由選自以下的材料形成：聚醯亞胺、聚苯並惡唑(PBO)、聚苯並惡唑系介電材料、苯環丁烷(BCB)、苯環丁烷系介電材料、或其組合。在某些實施例中，可利用以下中的至少一者來形成第一介電層904：物理氣相沉積、化學氣相沉積、原子層沉積、電氣化學沉積、分子束磊晶、或其組合。在某些實施例中，蓋層906是由金屬材料(例如，銅)而形成為具有約2μm~10μm的厚度。可使用多種方式中的任一種(例如，電鍍方法)在第一介電層904之上形成蓋層906。
方法800繼續進行至操作804，在操作804中如圖9B中所示在蓋層906的頂表面907上形成多個突出的結構908。在某些實施例中，可將所述多個突出的結構908排列成如圖7A中所示的顯示輪廓的柱706及/或如圖7B中所示的蜂巢式柵格756。在某些實施例中，可相似地通過如在圖1所示的方法100中所闡述的操作106至108來形成所述多個突出的結構908。為簡潔起見，在本文中將所述形成突出的結構908簡要闡述為：相似於操作106，在蓋層906之上形成圖案化層(例如，與圖2B所示的204相似的圖案化介電層)，其中所述圖案化層包括分別與突出的結構908中的一者的位置對應的多個開口；以及相似於操作108，以用於形成蓋層906的金屬材料(例如，此實例中的銅)填充所述開口，且接著從蓋層906移除圖案化層。
方法800繼續進行至操作806，在操作806中如圖9C中所示將裝置基板910貼合至蓋層906的頂表面907且設置於由突出的結構908形成的管腔909內。在某些實施例中，通過與如在圖1所示的方法100中所闡述的操作110實質上相似的操作而將裝置基板910貼合至蓋層906。例如：利用例如晶粒貼合膜(DAF)912或其他黏合層將裝置基板910的背側(例如，與電性接點910-1、910-2、910-3、910-4等相對的一側)設置於蓋層906的頂表面907上。在操作806之後，應注意，扇出型結構900的俯視圖可看上去實質上相似於圖7A及圖7B所示的示例性佈局中的任一者。
方法800繼續進行至操作808，在操作808中如圖9D中所示在裝置基板910及突出的結構908之上形成第二介電層914。第二介電層914可包含模製化合物。例如，第二介電層914是由選自以下的材料形成：環氧樹脂模製化合物(EMC)材料、模製底部填充(MUF)材料、味之素增層膜(ABF)材料、味之素增層膜系材料、樹脂材料、或其組合。在某些實施例中，利用以下中的至少一者在裝置基板910及突出的結構908之上形成第二介電層914：物理氣相沉積、化學氣相沉積、原子層沉積、電氣化學沉積、分子束磊晶或其組合。可以期望在某些實施例中執行蝕刻或平坦化製程(例如，化學機械拋光(CMP)製程)，以如上所述從裝置基板910的電性接點(例如，910-1、910-2、910-3、910-4等)的頂表面及/或突出的結構908的頂表面移除過量的材料，從而暴露出所述頂表面。
方法800繼續進行至操作808，在操作808中如圖9E中所示在第二介電層914之上形成重佈線層916。在某些實施例中，重佈線層916包括一個或多個導線916-1以及一個或多個通孔916-2。根據多種實施例，通過電性接點(例如，910-1、910-2、910-3、910-4等)來形成重佈線層916以在通孔908與裝置基板910之間提供電性連接。更具體來說，例如，重佈線層916的導線916-1用以在電性接點910-2與通孔908之間提供電性連接，且電性耦合至導線916-1的通孔916-2用以對一個或多個隨後形成的結構(例如，球柵陣列封裝焊球918)提供電性連接，以下將參照圖9F對此進行進一步詳細闡述。
仍然參照圖9E，重佈線層916可包括介電層917的其中形成有一個或多個導電層(例如，導線916-1、通孔916-2等)的層(例如，保護層)。介電層917可包含例如聚合物材料(例如，環氧樹脂、聚醯亞胺、聚苯並惡唑(PBO)等)或者可由通過例如旋轉塗布等任何適合的方法而形成的眾所周知的介電材料(例如，旋塗玻璃、氧化矽、氮氧化矽等)形成。在某些實施例中，可通過以下步驟中的至少一者來形成重佈線層916：如圖9E中所示，首先在第二介電層914之上設置導線916-1以對通孔908及各接點(910-1、910-2、910-3、910-4等)提供期望的連接及/或在通孔908與各接點(910-1、910-2、910-3、910-4等)之間提供期望的連接；接著在導線916-1及第二介電層914之上設置介電層917；隨後在介電層917內形成通孔916-2，以形成重佈線層916。在形成重佈 線層916之後，可執行蝕刻或平坦化製程(例如，化學機械拋光(CMP)製程)以移除過量的重佈線層916從而暴露出通孔916-2的頂表面。
現在參照圖8及圖9F，根據多種實施例，方法800繼續進行至操作812，在操作812中在重佈線層916之上形成一個或多個焊料接點918(例如，球柵陣列封裝焊球)，且從介電層904及蓋層906移除載體基板902。應注意，圖9F所示的所說明實施例是以倒置方式示出。可利用任何熟知的技術來形成焊料接點918，以對重佈線層916及另一載體基板或層(例如，另一扇出型結構)提供電性連接及/或在重佈線層916與另一載體基板或層(例如，另一扇出型結構)之間提供電性連接。儘管在圖9F所示的所說明實施例中，焊料接點918呈球體系形狀(例如，焊料球或球柵陣列封裝焊球)，然而可將焊料接點918形成為適合於在兩個接觸結構或接觸點之間提供電性接觸的各種形狀。在某些實施例中，焊料接點918可由金(Au)、銀(Ag)、鎳(Ni)、鎢(W)、鋁(Al)及/或其合金形成。
圖10根據多種實施例說明子扇出型結構1000的替代實施例，子扇出型結構1000包括設置於裝置基板1002之下的蓋層1004且蓋層1004進一步包括分別用於在其中設置通孔1008的孔1007的陣列。相似於圖7A所示的子扇出型結構700，裝置基板1002貼合至蓋層1004且設置於由突出的結構1006形成的管腔(例如，1005)內，且突出的結構1006延伸出蓋層1004的平面。 也就是說，突出的結構1006是由與蓋層1004相似的金屬材料(例如，銅)形成。然而，在此具體實施例中，如圖10中所示，突出的結構1006被形成為包括孔1007的陣列，其中孔1007的陣列用以環繞裝置基板1002且所述孔中的每一者被以通孔1008填充。在某些實施例中，突出的結構1006可在通孔1008仍被用於提供電性連接的同時提供最優化的散熱。
所述優點中的其中一者是本發明實施例提供一種新穎的方式來封裝多個裝置基板(即，積體電路晶片)，其是通過在用於經封裝裝置基板的封裝件/扇出型結構中形成嵌置銅柱。如以上所論述，通過將多個裝置基板中的每一者封裝成包括一個或多個嵌置銅柱的封裝件或扇出型結構，所述多個裝置基板可直接堆疊於一起且因此彼此電性耦合。此外，如上所述，利用嵌置銅柱來耦合至另一扇出型結構或封裝件可進而增加在有限基板面上的電性接點的數目，並降低所形成的電性連接路徑的阻抗等。
本發明實施例提供一種經封裝裝置，所述經封裝裝置包括一第一介電層、一第二介電層及一第三介電層。第二介電層形成於所述第一介電層之上，包括裝置基板及從所述第一介電層延伸且穿過所述第二介電層的通孔。第三介電層形成於所述第二介電層之上，包括延伸穿過所述第三介電層的導電柱，其中所述導電柱電性耦合至所述第二介電層的所述通孔。
本發明實施例提供一種經封裝裝置，所述經封裝裝置包括封裝件以及扇出型結構。所述封裝件包括第一焊料接點、第一重 佈線(RDL)層、第一介電層以及第二介電層。第一重佈線(RDL)層形成於所述第一焊料接點之上。第一介電層形成於所述第一重佈線層之上，包括第一裝置基板及從所述第一重佈線層延伸且穿過所述第一介電層的第一通孔。第二介電層形成於所述第一介電層之上，包括延伸穿過所述第二介電層的第一導電柱。所述扇出型結構包括第二重佈線層以及第三介電層。第二重佈線層形成於所述封裝件的所述第二介電層之上。第三介電層形成於所述第二重佈線層之上，包括第二裝置基板，其中所述第二裝置基板通過所述第二重佈線層、所述第一導電柱、所述第一介電層的所述第一通孔、及所述第一重佈線層而電性耦合至所述第一焊料接點。
本發明實施例提供一種形成經封裝裝置的方法。所述方法包括：提供形成於第一載體基板之上的第一介電層；在所述第一介電層之上形成通孔；將裝置基板貼合至所述第一介電層；在所述第一介電層之上形成第二介電層；在所述第二介電層之上形成第一重佈線(RDL)層；形成延伸穿過所述第一介電層的導電柱，其中所述導電柱電性耦合至所述通孔。
根據本發明實施例的經封裝裝置，所述導電柱被配置為所述經封裝裝置的電性接點。
根據本發明實施例的經封裝裝置，所述導電柱及所述第二介電層的所述通孔的材料包含銅。
根據本發明實施例的經封裝裝置，所述第二介電層包含以下中的至少一者：環氧樹脂模製化合物材料、模製底部填充材 料、味之素增層膜材料、味之素增層膜系材料、樹脂材料或其組合。
根據本發明實施例的經封裝裝置，所述第三介電層包含以下中的至少一者：聚醯亞胺、聚苯並惡唑、聚苯並惡唑系介電材料、苯環丁烷、苯環丁烷系介電材料或其組合。
根據本發明實施例的經封裝裝置，所述第一介電層包括導線，所述導線用以電性耦合所述裝置基板與所述第二介電層的所述通孔。
根據本發明實施例的經封裝裝置，所述的經封裝裝置還包括：至少一個焊料接點，設置於所述第一介電層的表面上，所述表面相對於所述第二介電層設置於所述第一介電層的另一表面。
根據本發明實施例的經封裝裝置，所述的經封裝裝置還包括：載體基板，通過所述至少一個焊料接點而耦合至所述經封裝裝置。
根據本發明實施例的經封裝裝置，所述扇出型結構的所述第三介電層還包括從所述第二重佈線層延伸且穿過所述第三介電層的第二通孔。
根據本發明實施例的經封裝裝置，所述扇出型結構還包括設置於所述第三介電層之上的第四介電層，且其中所述第四介電層包括延伸穿過所述第四介電層的第二導電柱。
根據本發明實施例的經封裝裝置，所述第二導電柱用以電性耦合所述第二通孔與所述第二重佈線層。
根據本發明實施例的經封裝裝置，所述第一導電柱及所 述第二導電柱的材料各包含銅。
根據本發明實施例的經封裝裝置，所述扇出型結構還包括被設置於所述第二重佈線層並與所述第三介電層相對的第二焊料接點。
根據本發明實施例的經封裝裝置，所述第二焊料接點用以通過所述第二重佈線層而將所述第二裝置基板電性耦合至所述第一導電柱。
根據本發明實施例的形成所述經封裝裝置的方法，形成所述導電柱的步驟包括：從所述第一介電層移除所述第一載體基板；形成延伸穿過所述第一介電層的開口；以及以銅材料填充所述開口。
根據本發明實施例的形成所述經封裝裝置的方法，所述方法還包括：在所述第一重佈線層之上形成焊料球；以及通過所述焊料球而將第二載體基板耦合至所述第一重佈線層。
根據本發明實施例的形成所述經封裝裝置的方法，所述方法還包括：通過所述導電柱而將包括第二裝置基板的扇出型結構耦合至所述經封裝裝置。
根據本發明實施例的形成所述經封裝裝置的方法，所述扇出型結構還包括第二重佈線層，所述第二重佈線層形成於所述第二裝置基板之上且設置於所述第二裝置基板與所述經封裝裝置的所述第一介電層之間。
雖然本發明已以實施例揭露如上，然其並非用以限定本 發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
202:第一介電層/介電層
206、212-2:通孔
208:裝置基板
209:層
210:第二介電層
212:重佈線層/介電層
212-1:導線
214:焊料接點/球柵陣列封裝焊球
216:第二載體基板/載體基板
218:導電柱/銅柱/嵌置銅柱
250:封裝件
260:扇出型結構

Claims (10)

  1. 一種經封裝裝置，包括：一第一介電層，包含至少一導電線；一第二介電層，形成於所述第一介電層之上，並包括一積體電路裝置基板及從所述第一介電層延伸且穿過所述第二介電層的一通孔；以及一第三介電層，形成於所述第二介電層之上，並包括延伸穿過所述第三介電層的一導電柱，且所述導電柱遠離所述第二介電層的表面與所述第三介電層遠離所述第二介電層的表面共平面，其中所述第二介電層的所述通孔設置於所述第三介電層中的所述導電柱與所述第一介電層中的所述至少一導電線之間並電耦合於所述導電柱與所述至少一導電線，且其中所述第一介電層、所述第二介電層以及所述第三介電層分別包含於單一經封裝裝置中。
  2. 如申請專利範圍第1項所述的經封裝裝置，其中所述導電柱被配置為所述經封裝裝置的電性接點。
  3. 如申請專利範圍第1項所述的經封裝裝置，其中所述至少一導電線用以電耦合所述積體電路裝置基板與所述第二介電層的所述通孔。
  4. 如申請專利範圍第1項所述的經封裝裝置，更包括：至少一個焊料接點，設置於所述第一介電層的表面上，所述表面相對於所述第二介電層設置於所述第一介電層的另一表面。
  5. 如申請專利範圍第4項所述的經封裝裝置，更包括：載體基板，通過所述至少一個焊料接點而耦合至所述經封裝裝置。
  6. 一種經封裝裝置，包括：封裝件，包括：第一焊料接點；第一重佈線層，形成於所述第一焊料接點之上；第一介電層，形成於所述第一重佈線層之上，包括第一裝置基板及從所述第一重佈線層延伸且穿過所述第一介電層的第一通孔；以及第二介電層，形成於所述第一介電層之上，包括延伸穿過整個所述第二介電層的第一導電柱，且所述第一導電柱遠離所述第一介電層的表面與所述第二介電層遠離所述第一介電層的表面共平面；以及扇出型結構，包括：第二重佈線層，形成於所述封裝件的所述第二介電層之上；以及第三介電層，形成於所述第二重佈線層之上，包括第二裝置基板，其中所述第二裝置基板通過所述第二重佈線層、所述第一導電柱、所述第一介電層的所述第一通孔、及所述第一重佈線層而電耦合至所述第一焊料接點。
  7. 一種經封裝裝置，包括：第一焊料接點；第一重佈線層，形成於所述第一焊料接點上；第一介電層，形成於所述第一重佈線層上，並包括從所述第一重佈線層延伸且穿過所述第一介電層的第一通孔；第二介電層，形成於所述第一介電層上，並包括延伸穿過所述第二介電層的第一導電柱，且所述第一導電柱遠離所述第一介電層的表面與所述第二介電層遠離所述第一介電層的表面共平面；第二重佈線層，形成於所述第二介電層上；以及第三介電層，形成於第二重佈線層上，並包括裝置基板，其中所述裝置基板通過所述第二重佈線層、所述第一導電柱、所述第一介電層的所述第一通孔以及所述第一重佈線層而電耦合至所述第一焊料接點。
  8. 一種形成經封裝裝置的方法，包括：提供形成於第一載體基板之上的第一介電層；在所述第一介電層之上形成通孔；將裝置基板貼合至所述第一介電層；在所述第一介電層之上形成第二介電層；在所述第二介電層之上形成第一重佈線層；移除所述第一載體基板之後，形成延伸穿過所述第一介電層的導電柱，其中所述導電柱電耦合至所述通孔。
  9. 一種形成經封裝裝置的方法，包括： 形成第一介電層；在所述第一介電層上形成第二介電層，其中所述第二介電層包含積體電路裝置基板及從所述第一介電層延伸且穿過所述第二介電層的通孔；以及在所述第二介電層上形成第三介電層，其中所述第三介電層包括延伸穿過所述第三介電層的導電柱，且所述導電柱遠離所述第二介電層的表面與所述第三介電層遠離所述第二介電層的表面共平面，其中所述導電柱電耦合至所述第二介電層的所述通孔，且其中所述第一介電層、所述第二介電層與所述第三介電層包含於單一封裝裝置中。
  10. 一種形成經封裝裝置的方法，包括：形成第一介電層；在所述第一介電層中形成第一通孔；在所述第一介電層上形成第二介電層，其中所述第二介電層包含積體電路裝置基板以及從所述第一介電層延伸且穿過所述第二介電層的第二通孔；在所述第二介電層上形成第三介電層，其中所述第三介電層包括延伸穿過所述第三介電層的導電柱，且所述導電柱遠離所述第二介電層的表面與所述第三介電層遠離所述第二介電層的表面共平面，其中所述導電柱電耦合至所述第二通孔，所述第二通孔電耦合至所述第一通孔，且其中所述第一介電層、所述第二介電層與 所述第三介電層包含於單一經封裝裝置中；以及將所述第一通孔電耦合至載體基板。
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