TW201943039A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

Info

Publication number
TW201943039A
TW201943039A TW107127490A TW107127490A TW201943039A TW 201943039 A TW201943039 A TW 201943039A TW 107127490 A TW107127490 A TW 107127490A TW 107127490 A TW107127490 A TW 107127490A TW 201943039 A TW201943039 A TW 201943039A
Authority
TW
Taiwan
Prior art keywords
sealing body
insulating sealing
wire
wafer
wafer stack
Prior art date
Application number
TW107127490A
Other languages
English (en)
Other versions
TWI668825B (zh
Inventor
黃崑永
潘吉良
鄭靖樺
曾斌輝
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Application granted granted Critical
Publication of TWI668825B publication Critical patent/TWI668825B/zh
Publication of TW201943039A publication Critical patent/TW201943039A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8593—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85947—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by mechanical means, e.g. "pull-and-cut", pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1811—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

一種半導體封裝，包括晶片堆疊體、至少一導線、第一絕緣密封體、第二絕緣密封體及重佈線路層，且其製造方法亦被提出。晶片堆疊體包括堆疊於彼此之上的多個半導體晶片。每一半導體晶片具有主動面，主動面具有至少一接合區，且晶片堆疊體暴露出每一至少一接合區。導線對應配置於接合區上。第一絕緣密封體密封接合區及導線。第一絕緣密封體暴露出至少一部分的每一導線。第二絕緣密封體密封晶片堆疊體及第一絕緣密封體。第二絕緣密封體暴露出第一絕緣密封體。重佈線路層配置於第一及第二絕緣密封體上，且電性耦合至導線。

Description

半導體封裝及其製造方法
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種薄型扇出多晶片堆疊體的半導體封裝及其製造方法。
在習知的多晶片堆疊體封裝結構中，多個半導體晶片是逐一向上堆疊於基板上。晶片的主動面朝上，且藉由打線接合形成的完整接合線將晶片電性連接至基板。一般而言，接合線的接合線頭（bonding threads）接合於晶片的接合墊，接合線的線端接合至基板的接點，且接合線的線段是弧形的。然而，使用上述方法所形成的多晶片堆疊體封裝結構對於基板的厚度和弧線的高度有基本需求。換句話說，無法降低多晶片堆疊體封裝結構的總厚度。特別地，在需要長接合線的情況下，在形成密封體的步驟中，容易產生由線偏移（wire sweep）所引起的短路等問題。
此外，一種製造出更薄的多晶片堆疊體封裝結構的方法涉及在形成重佈線路層之前，研磨或減薄模塑化合物。然而，研磨過程會造成模塑化合物殘留於接合線的頂面上，這是不期望發生的現象。這種絕緣殘留物對於接續的製程（例如形成重佈線路層於其上）會產生負面的影響，且更導致產品的電阻及熔斷電流的降低。因此，如何在緩解線偏移問題及消除留在導線頂面上的絕緣殘留物問題的同時，還能夠將半導體封裝小型化，已成為本領域研究人員的一大挑戰。
為了解決上述問題，本發明提供一種半導體封裝及其製造方法，其能夠緩解特定封裝類型中垂直接合線的線偏移的問題，且消除留在接合線頂面上的絕緣殘留物的問題。
本發明的半導體封裝，包括晶片堆疊體、至少一導線、第一絕緣密封體、第二絕緣密封體及重佈線路層。晶片堆疊體包括堆疊於彼此之上的多個半導體晶片。每一半導體晶片具有主動面。主動面具有至少一接合區，且晶片堆疊體暴露出每一至少一接合區。至少一導線對應配置於至少一接合區上。第一絕緣密封體密封至少一接合區及至少一導線。第一絕緣密封體暴露出至少一部分的每一導線。第二絕緣密封體密封晶片堆疊體及第一絕緣密封體。第二絕緣密封體暴露出第一絕緣密封體。重佈線路層配置於第一絕緣密封體及第二絕緣密封體上。重佈線路層電性耦合至至少一導線。
在本發明的一實施例中，上述的第一絕緣密封體的表面與第二絕緣密封體的接觸於重佈線路層的表面共面。
在本發明的一實施例中，上述的晶片堆疊體的頂部半導體晶片具有與至少一接合區接觸的區域，且第二絕緣密封體覆蓋晶片堆疊體的頂部半導體晶片。
在本發明的一實施例中，上述的半導體封裝更包括至少一導電端子。導電端子配置於與第二絕緣密封體相對的重佈線路層上，且電性耦合至重佈線路層。
在本發明的一實施例中，上述的晶片堆疊體的底部半導體晶片遠離重佈線層，且底部半導體晶片具有相對於主動面的背面，底部半導體晶片的背面與第一絕緣密封體的表面及第二絕緣密封體的表面共面。
本發明還提供一種半導體封裝的製造方法。本方法包括至少以下步驟。首先，提供晶片堆疊體。晶片堆疊體包括堆疊於彼此之上的多個半導體晶片，每一半導體晶片具有主動面。主動面具有至少一接合區，且晶片堆疊體暴露出每一至少一接合區。接著，至少一導線對應形成於接合區上。接著，形成第一絕緣密封體，以密封接合區及導線。接著，形成第二絕緣密封體，以密封晶片堆疊體及第一絕緣密封體。第二絕緣密封體暴露出第一絕緣密封體。接著，於第一絕緣密封體及第二絕緣密封體上形成重佈線路層。重佈線路層電性耦合至導線。
在本發明的一實施例中，上述形成至少一導線的步驟包括：藉由打線接合製程，形成至少一導線連接晶片堆疊體及虛置間隔片。
在本發明的一實施例中，上述在形成第二絕緣密封體之後，虛置間隔片密封於第二絕緣密封體。
在本發明的一實施例中，上述在形成第二絕緣密封體之後，減少第一絕緣密封體的厚度及第二絕緣密封體的厚度；在減少第一絕緣密封體的厚度及第二絕緣密封體的厚度之後，第一絕緣密封體的表面與第二絕緣密封體的表面共面，第二絕緣密封體的表面覆蓋晶片堆疊體的頂部半導體晶片的主動面。
在本發明的一實施例中，上述第一絕緣密封體的黏滯係數低於第二絕緣密封體的黏滯係數，形成第一絕緣密封體的步驟包括：配置第一絕緣材料於晶片堆疊體上；藉由施加外部能量固化第一絕緣材料，以形成第一絕緣密封體。
在本發明的一實施例中，上述的製造方法，更包括：於與第二絕緣密封體相對的重佈線路層上，形成至少一導電端子，以電性耦合至重佈線路層。
在本發明的一實施例中，上述在移除臨時載板之後，第一絕緣密封體的表面與底部半導體晶片的背面及第二絕緣密封體的表面共面。
基於上述，本發明能夠實現半導體封裝的小型化，且其整體封裝厚度相當於晶片堆疊體的高度。此外，在形成第二絕緣密封體之前，形成第一絕緣密封體，以密封形成於半導體晶片的主動面上的導線。因此，第一絕緣密封體可以保護導線，以避免線偏移的問題產生。另外，由於第一絕緣密封體的材料特性，第一絕緣密封體的多餘部分可以輕易地被移除，因此可以消除殘留於導線的頂面上的絕緣殘留物的問題。藉此，可以製造出具有較佳穩定性及良率的半導體封裝。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下將參照本實施例之圖式以更全面地闡述本發明。然而，應當指出的是，圖式皆為以示例性的方式繪示本發明的基本結構或實施方式的簡化示意圖。因此，僅繪示出與本發明相關的構件和組合，且圖式中示出的組件並沒有按照實際執行的數量、形狀及尺寸來繪製。某些尺寸比例和其他相關的尺寸比例被誇大或簡化，以提供更清楚的描述。實際執行的數量、形狀及尺寸比例是開放式設計，且詳細的構件佈局可能更複雜。
圖1A至圖1H是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。請參考圖1A，晶片堆疊體110設置於臨時載板50上。舉例來說，晶片堆疊體110包括多個半導體晶片112。每一個半導體晶片112可以藉由拾取放置方法（pick-and-place method）一個接一個地配置。在本實施例中，半導體晶片112可以堆疊於彼此之上（例如，以階梯偏移的方式或交錯堆疊的方式堆疊）。在另一些實施例中，半導體晶片112可以是以交錯、塔狀等的方式堆疊。半導體晶片112的數量可以是大於或等於四。然而，本發明並不限制半導體晶片112的數量。最靠近臨時載板50的半導體晶片112可以被視為底部半導體晶片112B，且最遠離臨時載板50的半導體晶片112可以被視為頂部半導體晶片112T。每一個半導體晶片112具有遠離臨時載板50的主動面1121及相對於主動面1121的背面1122。主動面1121可以具有至少一接合區BR，晶片堆疊體110可以暴露出接合區BR。在一些其它實施例中，多於一個的接合區BR（例如，位於主動面1121的相對兩側）可以被堆疊於其上的半導體晶片112所暴露。接合區BR的配置形式可以取決於晶片堆疊體110的堆疊方式，但本發明不限於此。
在一些實施例中，半導體晶片112為具有記憶體單元的積體電路（integrated circuit，IC）半導體裝置。舉例來說，每一個半導體晶片112可以包括形成於其上的積體電路以及配置於主動面1121的接合區BR上的至少一個電極1123。每一個半導體晶片112的電極1123可以電耦合至位於半導體晶片112內部的積體電路的金屬互連結構（未繪示）。在一個半導體晶片112的接合區BR上的電極1123未被堆疊於其上的另一個半導體晶片112覆蓋，以作為進一步的電性連接。舉例來說，當一個半導體晶片112堆疊於底部半導體晶片112B上時，且堆疊於其上的半導體晶片112覆蓋部份的底部半導體晶片112B的主動面1121。堆疊於其上的半導體晶片112未覆蓋底部半導體晶片112B的電極1123。
在一些實施例中，晶片堆疊體110可以包括形成於每一個半導體晶片112的背面1122上的多個晶粒黏著膜114，以黏著底下的半導體晶片112的主動面1121。底部半導體晶片112的晶粒黏著膜114可以貼附至臨時載板50。臨時載板50可以是晶片支撐系統（wafer support system，WSS）或是面板支撐系統（panel support system，PSS），但本發明不限於此。用於臨時載板50的主體材料可以是矽、玻璃或是其他適宜的材料，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。臨時載板50的形式可以是晶圓或是面板，但本發明不限於此。在一些實施例中，為了在後續製程中提升晶片堆疊體110與臨時載板50的可剝離性，可以在臨時載板50上形成離型層52。舉例來說，離型層52為預製於臨時載板50的表面上的紫外光黏著凝膠。
請再參考圖1A，虛置間隔片（dummy spacer）120配置於晶片堆疊體110的頂部半導體晶片112T的主動面1121上。舉例來說，可以在虛置間隔片120上形成晶粒黏著膜114，以黏附頂部半導體晶片112T的主動面1121。虛置間隔片120暴露出頂部半導體晶片112T的接合區BR及位於接合區BR上的電極1123。舉例來說，虛置間隔片120可以選自於虛置晶片（dummy chip）或是散熱金屬板，因此虛置間隔片120適用於具有良好散熱效果的拾取放置操作。虛置間隔片120的尺寸及厚度可以小於或等於半導體晶片112、112B或112T的單位尺寸和單位厚度。這裡的「虛設晶片」是指具有與半導體晶片相似的形狀或外觀，且不具有形成於其中的積體電路主動元件的半導體基板。在一些實施例中，虛置間隔片120可以不配置於晶片堆疊體110上，並將於後續詳細說明。
請參考圖1B，至少一導線130對應形成於接合區BR上。在一些實施例中，可以在晶片堆疊體110上形成多個導線130。導線130的數量取決於設計需求，於本發明並不加以限制。舉例來說，導線130可以藉由打線接合製程而形成。導線130的材料可以包括金、銅或是其他適宜的導電材料。每一個導線130具有接合線頭131、垂直線段132以及犧牲段133。導線130的接合線頭131接合至半導體晶片112、112T、112B的電極1123。導線130的犧牲段133接合至虛置間隔片120的導電表面。接合線頭131可以藉由垂直線段132一體連接至對應的犧牲段133。在一些實施例中，在形成導線130之後，犧牲段133突出至虛置間隔片120的水平面上。舉例來說，每一個犧牲段133的頂端與晶片堆疊體110的底部之間的距離定義為每一個導線130的導線弧高（wire arc height）H1，並且虛置間隔片120的接合犧牲段133的導電表面與晶片堆疊體110的底部之間的距離定義為虛置間隔片120的水平高度（level height）H2。每一個導線130的導線弧高H1大於虛置間隔片120的水平高度H2。
請參考圖1C，在每一個半導體晶片112的主動面1121的接合區BR上形成第一絕緣密封體140，以密封接合區BR及導線130。在一些實施例中，第一絕緣密封體140至少密封導線130的接合線頭131及垂直線段132。在一些實施例中，第一絕緣密封體140還覆蓋至少一部分的虛置間隔片120。舉例來說，藉由將第一絕緣材料分佈於主動面1121的接合區BR上，以將第一絕緣材料配置於晶片堆疊體110上。第一絕緣材料可以是未具有填充物的絕緣材料、半固化的環氧樹脂或是其他適宜的絕緣材料。接著，對第一絕緣材料施加例如是熱及/或壓力等外部能量，以進行固化製程。在一些實施例中，在固化之後，第一絕緣密封體140可以維持低黏度以促進空隙的移除。舉例來說，在後固化製程之後形成的第一絕緣密封體140在攝氏溫度25度下具有介於10,000至80,000 毫帕斯卡·秒（mPa·s）之間的黏滯係數。藉由上述步驟，第一絕緣密封體140形成為密封導線130且不具有模製缺陷（例如線偏移或空隙）的固化產物。
請參考圖1D，第二絕緣密封體150形成於臨時載板50上，以密封晶片堆疊體110、虛置間隔片120及第一絕緣密封體140。舉例來說，第二絕緣密封體150可以是藉由模塑製程所形成的模塑化合物。第一絕緣密封體140的黏滯係數可以小於第二絕緣密封體150的黏滯係數。在一些實施例中，在形成第二絕緣密封體150之後，第二絕緣密封體150的厚度T1大於導線130的導線弧高H1。在一些實施例中，配置於晶片堆疊體110上的虛置間隔片120可以包括穩定導線130的功能，以減少在形成第一絕緣密封體140及第二絕緣密封體150時產生的線偏移的問題。
請參考圖1E，將第二絕緣密封體150的厚度T1減少至減薄厚度T2。舉例來說，藉由機械研磨製程及/或化學機械研磨（chemical mechanical polishing，CMP）製程或是其他合適的製程，以研磨第二絕緣密封體150。在一些實施例中，在製造過程中，將導線130的犧牲段133及部分覆蓋犧牲段133的第一絕緣密封體140自導線130上移除，以減少第一絕緣密封體140的厚度。第一絕緣密封體140可以暴露出至少一部分的導線130。第二絕緣密封體150可以暴露出第一絕緣密封體140。換句話說，在減少第二絕緣密封體150的厚度之後，第一絕緣密封體140橫向密封導線130的接合線頭131及垂直線段132，且第二絕緣密封體150橫向密封第一絕緣密封體140。
在一些實施例中，虛置間隔片120可以作為研磨深度的緩衝區。換句話說，虛置間隔片120提供間隔功能，以防止在進行研磨的過程中，對於頂部半導體晶片112T的主動面1121（未堆疊或覆蓋）的破壞。舉例來說，可以研磨至少一部分的虛置間隔片120，因此頂部半導體晶片112T的主動面1121不會受到研磨製程的破壞。在一些實施例中，將第二絕緣密封體150研磨至直到暴露出虛置間隔片120的表面120a及導線130的垂直線段132的頂面132a為止。換句話說，在減少第二絕緣密封體150的厚度之後，第二絕緣密封體150的頂面150a可以基本上為平坦的表面。舉例來說，第二絕緣密封體150的頂面150a與虛置間隔片120的表面120a、第一絕緣密封體140的表面140a及導線130的垂直線段132的頂面132a共面。在一些實施例中，在減少第二絕緣密封體150的厚度之後，垂直線段132的高度與對應接合的半導體晶片112的堆疊高度互補。舉例來說，形成於底部半導體晶片112B上的垂直線段132的長度大於形成於頂部半導體晶片112T上的垂直線段132的長度。
請參考圖1F，在減薄第二絕緣密封體150之後，將重佈線路層160形成於第二絕緣密封體150的頂面150a、第一絕緣密封體140及虛置間隔片120上，使得半導體晶片112的主動面1121面向重佈線路層160。換句話說，重佈線路層160電性耦合至被第一絕緣密封體140及第二絕緣密封體150暴露出的部份的導線130，且半導體晶片112的主動面1121面向重佈線路層160。舉例來說，重佈線路層160包括扇出線路161、交替堆疊於扇出線路161上的介電層162以及配置於扇出線路161上的保護層163。在一些實施例中，介電層162的最下層形成於第二絕緣密封體150的頂面150a及虛置間隔片120上。藉此，第二絕緣密封體150與介電層162的最下層密封虛置間隔片120，進而提升抗剝離的阻力。
介電層162的最下層具有多個開口，多個開口暴露出導線130的垂直線段132的至少一部分的頂面132a。扇出線路161的最下層形成於介電層162的開口中及最下層上，以電性耦合至被開口暴露出的導線130的垂直線段132。扇出線路161可以是藉由濺鍍及電鍍形成例如是鈦/銅/銅（Ti/Cu/Cu）或是鈦/銅/銅/鎳/金（Ti/Cu/Cu/Ni/Au）等的多層金屬結構。換句話說，扇出線路161可以包括接合層、種子層及電鍍層的組合。上述步驟可以重覆執行多次，以形成電路設計所需的多層（multi-layered）重佈線路層，但本發明不限於此。在形成扇出線路161的最上層之後，保護層163形成於扇出線路161的最上層上，以用於保護。介電層162及保護層163可以例如是聚酰亞胺（polyimide）或是其他適宜的材料的有機絕緣層。在一些實施例中，保護層163具有多個開口，多個開口暴露出至少一部分的扇出線路161，以作為進一步的電性連接。
請參考圖1G，至少一個導電端子170形成於重佈線路層160的相對於第二絕緣密封體150的表面上。本發明對於導電端子170的數量並不加以限制，只要導電端子170電性耦合至重佈線路層160，以連通晶片堆疊體110與外部電子構件（未繪示）。舉例來說，可以藉由植球製程、電鍍製程或其他適宜的製程，在保護層163的開口中形成導電端子170，以電性耦合至重佈線路層160的扇出線路161的最上層。導電端子170可以包括導電球、導電柱、導電凸塊或是其組合。然而本發明不限於此。導電端子170可以依據設計上的需求而具有其他可能的形式以及形狀。在一些實施例中，可以選擇性地進行焊接製程（soldering process）以及迴焊製程（reflowing process），以提升導電端子170與重佈線路層160之間的附著力。
請參考圖1H，在形成導電端子170之後，移除臨時載板50。舉例來說，在施加紫外光照射至離型層52之後，離型層52將失去黏著力，且可以輕易地從臨時載板50上剝離。在移除臨時載板50之後，底部半導體晶片112B的背面1122與第二絕緣密封體150的相對於頂面150a的背面150b共面。如圖1H所示，半導體封裝100的製造過程基本上已完成。
圖2A至圖2E是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。本實施例的製造方法與圖1A至圖1H中所示的實施例的製造方法相似。圖式中相同或近似的元件標號表示相同或近似的元件，並且為了簡潔起見不再重複其細節。
請參考圖2A，將晶片堆疊體110設置於臨時載板50上。虛置間隔片120可以選擇性地配置於頂部半導體晶片112T上。藉此，圖2A中是以虛線表示虛置間隔片120，以說明虛置間隔片120可以存在或不存在。在虛置間隔片120沒有配置於晶片堆疊體110上的實施例中，半導體晶片112的堆疊數量及晶片堆疊體110的厚度可能會增加。在配置晶片堆疊體110之後，導線230對應形成於接合區BR上。在本實施例中，每一個導線230形成為直垂直接合線（straight vertical wire bond），且具有接合線頭231及與接合線頭231連接為一體的垂直線段232。接合線頭231接合至半導體晶片112、112T及112B的電極1123。在形成導線230之後，從晶片堆疊體110的底部測量的每一個導線230的高度H3大於從晶片堆疊體110的底部測量的頂部半導體晶片112T的水平高度H4。舉例來說，每一個導線230的高度H3與頂部半導體晶片112T的水平高度H4之間的差值可以介於約20μm至約50μm之間。
請參考圖2B，第一絕緣密封體140形成於每一個半導體晶片112的主動面1121的接合區BR上，以密封接合區BR及導線230。在形成第一絕緣密封體140之後，第二絕緣密封體150形成於臨時載板50上，以密封晶片堆疊體110及第一絕緣封裝體140。第一絕緣密封體140和第二絕緣密封體150的形成過程與上述過程類似，並且為了簡潔起見於此省略其細節。在形成第二絕緣密封體150之後，第二絕緣密封體150的厚度T1’可以相較於每一個導線230的高度H3大約10μm至約50μm，以避免在壓縮成型期間接觸導線230。
請參考圖2C，減少第二絕緣密封體150的厚度，以暴露出導線230的頂面232a。第二絕緣密封體150的減薄製程與圖1E中所示的製程相似，為了簡潔起見於此省略其細節。在本實施例中，在虛置間隔片120未配置於頂部半導體晶片112T上的情況下，第一絕緣密封體140覆蓋頂部半導體晶片112T的主動面1211的接合區BR，且第二絕緣密封體150覆蓋連接至頂部半導體晶片112T的接合區BR的主動面1211的區域AR。在減薄製程之後，第二絕緣密封體150的頂面150a與第一絕緣密封體140的表面140a及導線230的頂面232a共面。在虛置間隔片配置於頂部半導體晶片112T的實施例中，作為研磨深度的緩衝區的虛置間隔片可以覆蓋頂部半導體晶片112T的主動面1211，此與圖1E中所示的實施例相似。
請參考圖2D，在減少第二絕緣密封體150的厚度之後，重佈線路層160形成於第二絕緣密封體150的頂面150a及第一絕緣密封體140上，以電性耦合至導線230。在形成重佈線路層160之後，導電端子170形成於重佈線路層160上，以電性耦合至重佈線路層160。重佈線路層160及導電端子170的形成過程與圖1F及圖1G中所示的製程相似，為了簡潔起見於此省略其細節。
請參考圖2E，在形成導電端子170之後，移除臨時載板50。舉例來說，在施加紫外光照射至離型層52之後，離型層52將失去黏著力，且可以輕易地從臨時載板50上剝離。在移除臨時載板50之後，底部半導體晶片112B的背面1122與第二絕緣密封體150的背面150b共面。如圖2E所示，半導體封裝200的製造過程基本上已完成。
圖3A至圖3F是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。本實施例的製造方法與圖1A至圖1H中所示的實施例的製造方法相似。圖式中相同或近似的元件標號表示相同或近似的元件，並且為了簡潔起見不再重複其細節。
請參考圖3A，將晶片堆疊體310設置於臨時載板50上。晶片堆疊體310包括堆疊於彼此之上（例如，以階梯偏移的方式或交錯堆疊的方式堆疊）的頂部半導體晶片312T及底部半導體晶片312B，其與晶片堆疊體110相似。頂部半導體晶片312T及底部半導體晶片312B具有面向遠離對應的臨時載板50的主動面3121。電極3123配置於主動面3121的接合區BR上。半導體晶片的數量可以是等於或大於二，但本發明不限於此。虛置間隔片120配置於頂部半導體晶片312T的主動面3121上，且暴露出頂部半導體晶片312T與底部半導體晶片312B的接合區BR。分別形成導線330，以連接虛置間隔片120與位於頂部半導體晶片312T及底部半導體晶片312B上的電極3123。導線330的形成過程與導線130的形成過程相似，為了簡潔起見於此省略其細節。
請參考圖3B，第一絕緣密封體340配置於虛置間隔片120及晶片堆疊體310上，以密封頂部半導體晶片312T與底部半導體晶片312B的導線330與主動面3121。舉例來說，第一絕緣密封體340在攝氏溫度25度下具有介於10,000至80,000 mPas之間的黏滯係數。第一絕緣密封體340的材料可以包括導線上薄膜（film-over-wire，FOW）材料、底膠、液態環氧模塑化合物或是其他合適的材料。虛設晶粒342（例如，矽間隔壁、基板等）可以用於固定導線上薄膜。
舉例來說，處於半固化狀態的第一絕緣密封體340被用於覆蓋主動面3121的接合區BR，使得導線330可以嵌入第一絕緣密封體340中。在一些實施例中，第一絕緣密封體340可以進一步覆蓋虛置間隔片120，使得連接於虛置間隔片120及晶片堆疊體310之間的導線330完全嵌入第一絕緣密封體340中。為了便於嵌入導線330，可以施加例如是熱及/或壓力的外部能量至第一絕緣密封體340，使得第一絕緣密封體340具有可延展性，而可自主成型地環繞於導線330。接著，移除外部能量，且可以使用包括軟固化製程及/或硬固化製程的固化製程以固化第一絕緣密封體340，但本發明不限於此。因此，在第一絕緣密封體340與虛置間隔片120、晶片堆疊體310及接合於其間的導線330之間將不會形成間隙或是實質上不形成空隙。藉由採用導線上薄膜製程，將導線330嵌入第一絕緣密封體340中，第一絕緣密封體340可以提供導線330額外的支撐力，如此可以保護導線330，以避免線偏移或甚至破損的問題產生。
在一些實施例中，在形成第一絕緣密封體340之後，第一絕緣密封體340完全覆蓋虛置間隔片120的表面及連接至虛置間隔片120的表面的側面。虛置間隔片120暴露出頂部半導體晶片312T的主動面3121，且第一絕緣密封體340完全覆蓋頂部半導體晶片312T的連接至主動面3121的側面。第一絕緣密封體340完全覆蓋底部半導體晶片312B的主動面3121，且第一絕緣密封體340暴露出底部半導體晶片312B的側面。
請參考圖3C，第二絕緣密封體150形成於臨時載板50上，藉由模塑製程以密封晶片堆疊體310、虛置間隔片120及第一絕緣密封體340。在本實施例中的第二絕緣密封體150的形成過程與如圖1D中所示的第二絕緣密封體150的形成過程相似，為了簡潔起見於此省略其細節。
請參考圖3D，藉由機械研磨製程及/或化學機械研磨製程或是其他合適的製程，以減少第二絕緣密封體150的厚度。在一些實施例中，虛設晶粒342、部份的第一絕緣密封體340及部份的導線330亦在相同的製程中被移除。在另一些實施例中，亦研磨部份的虛置間隔片120，使得第一絕緣密封體340僅橫向密封虛置間隔片120，且暴露出虛置間隔片120的表面120a。在減薄製程之後，第二絕緣密封材料150的頂面150a與虛置間隔片120的表面120a、第一絕緣密封材料340的表面340a及導線330的頂面330a共面。若導線330的頂面330a上還存在第一絕緣密封體340的殘留物，可以進行清洗製程以移除第一絕緣密封體340的殘留物。由於第一絕緣密封體340的材料特性，在導線330上不想要的第一絕緣密封體340的殘留物330可以輕易地被移除，使得可以消除留在導線330的頂面330a上的殘留物的問題。
請參考圖3E，在減少第二絕緣密封體150的厚度之後，重佈線路層160形成於第一絕緣密封體340的表面340a及第二絕緣密封體150的頂面150a上，以電性耦合至導線230。重佈線路層160的形成過程與圖1F中所示的製程相似。在本實施例中，在形成保護層163之後，多個端子基座164形成於保護層163的開口中，以電形耦合至扇出線路161的頂面。端子基座164可以包括凸塊底金屬（under-bump metallization，UBM），且可以由例如是鎳、銅或是其他合適的材料所形成。接著，導電端子170形成於端子基座164上，以電性耦合至重佈線路層160。端子基座164可以增強導電端子170與扇出線路161之間的接合。
請參考圖3F，在形成導電端子170之後，藉由剝離離型層52以移除臨時載板50。在移除臨時載板50之後，底部半導體晶片312B的背面3122與第二絕緣密封體150的背面150b共面。如圖3F所示，半導體封裝300的製造過程基本上已完成。
圖4A至圖4B是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。本實施例的製造方法與圖3A至圖3F中所示的製造方法相似。請參考圖4A及圖4B，本實施例與圖3A～圖3F中所示的實施例的差別在於形成第一絕緣密封體440的步驟，第一絕緣密封體440可以配置於臨時載板50，以覆蓋虛置間隔片120及晶片堆疊體310，使得第一絕緣密封體440密封導線330、頂部半導體晶片312T與底部半導體晶片312B的主動面3121及底部半導體晶片312B的至少一側面S。
在形成第一絕緣密封體440之後，接續形成第二絕緣密封體150、重佈線路層160及導電端子170，且其製造過程與圖3C至圖3F中所示的製程相似，為了簡潔起見不再重複其細節。請參考圖4B，其繪示出半導體封裝400。第一絕緣密封體440覆蓋頂部半導體晶片312T與底部半導體晶片312B的接合區BR。在一些實施例中，第一絕緣密封體440可以進一步覆蓋連接至頂部半導體晶片312T與底部半導體晶片312B的接合區BR的側面S。在一些實施例中，第一絕緣密封體440的表面440a與底部半導體晶片312B的背面3122及第二絕緣密封體150的背面150b共面。
綜上所述，本發明的半導體封裝能夠實現半導體封裝的小型化，且其整體封裝厚度相當於晶片堆疊體的高度。更進一步地說，在形成第二絕緣密封體之前，形成第一絕緣密封體，以密封形成於半導體晶片的主動面的接合區上的導線。因此，在形成第二絕緣密封體的製程中，第一絕緣密封體可以保護導線，以避免線偏移的問題產生。另外，由於第一絕緣密封體的材料特性，第一絕緣密封體的多餘部分可以輕易地被移除，因此可以消除殘留於導線的頂面上的絕緣殘留物的問題，進而避免降低重佈線路層的電阻與熔斷電流。藉此，可以製造出具有較佳穩定性及良率的半導體封裝。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
50‧‧‧臨時載板
52‧‧‧離型層
100、200、300、400‧‧‧半導體封裝
110、310‧‧‧晶片堆疊體
112‧‧‧半導體晶片
112T、312T‧‧‧頂部半導體晶片
112B、312B‧‧‧底部半導體晶片
1121、3121‧‧‧主動面
1122、150b、3122‧‧‧背面
1123、3123‧‧‧電極
114‧‧‧晶粒黏著膜
120‧‧‧虛置間隔片
120a、140a、340a、440a‧‧‧表面
130、230、330‧‧‧導線
131、231‧‧‧接合線頭
132、232‧‧‧垂直線段
132a、150a、232a、330a‧‧‧頂面
133‧‧‧犧牲段
140、340、440‧‧‧第一絕緣密封體
150‧‧‧第二絕緣密封體
160‧‧‧重佈線路層
161‧‧‧扇出線路
162‧‧‧介電層
163‧‧‧保護層
164‧‧‧端子基座
170‧‧‧導電端子
342、442‧‧‧虛設晶粒
AR‧‧‧區域
BR‧‧‧接合區
H1‧‧‧導線弧高
H2、H4‧‧‧水平高度
H3‧‧‧高度
T1、T1’‧‧‧厚度
T2‧‧‧減薄厚度
S‧‧‧側面
圖1A至圖1H是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。 圖2A至圖2E是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。 圖3A至圖3F是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。 圖4A至圖4B是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。

Claims (10)

  1. 一種半導體封裝，包括： 晶片堆疊體，包括堆疊於彼此之上的多個半導體晶片，每一所述多個半導體晶片具有主動面，所述主動面具有至少一接合區，且所述晶片堆疊體暴露出每一所述至少一接合區； 至少一導線，對應配置於所述至少一接合區上； 第一絕緣密封體，密封所述至少一接合區及所述至少一導線，所述第一絕緣密封體暴露出至少一部分的每一所述至少一導線； 第二絕緣密封體，密封所述晶片堆疊體及所述第一絕緣密封體，其中所述第二絕緣密封體暴露出所述第一絕緣密封體；以及 重佈線路層，配置於所述第一絕緣密封體及所述第二絕緣密封體上，其中所述重佈線路層電性耦合至所述至少一導線。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述第一絕緣密封體的黏滯係數低於所述第二絕緣密封體的黏滯係數。
  3. 如申請專利範圍第1項所述的半導體封裝，更包括： 虛置間隔片，配置於所述晶片堆疊體與所述重佈線路層之間，且所述第二絕緣密封體橫向密封於所述虛置間隔片，其中所述虛置間隔片暴露出所述至少一接合區。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述虛置間隔片的表面與所述第一絕緣密封體的表面及所述第二絕緣密封體的表面共面。
  5. 如申請專利範圍第1項所述的半導體封裝，其中所述晶片堆疊體中的每一所述多個半導體晶片具有連接至所述主動面的側面，且所述第一絕緣密封體覆蓋每一所述多個半導體晶片的所述側面。
  6. 一種半導體封裝的製造方法，包括： 提供晶片堆疊體，其中所述晶片堆疊體包括堆疊於彼此之上的多個半導體晶片，每一所述多個半導體晶片具有主動面，所述主動面具有至少一接合區，且所述晶片堆疊體暴露出每一所述至少一接合區； 對應形成至少一導線於所述至少一接合區上； 形成第一絕緣密封體，以密封所述至少一接合區及所述至少一導線； 形成第二絕緣密封體，以密封所述晶片堆疊體及所述第一絕緣密封體，其中所述第二絕緣密封體暴露出所述第一絕緣密封體；以及 形成重佈線路層於所述第一絕緣密封體及所述第二絕緣密封體上，其中所述重佈線路層電性耦合至所述至少一導線。
  7. 如申請專利範圍第6項所述的製造方法，更包括： 在形成所述至少一導線之前，將虛置間隔片配置於所述晶片堆疊體的頂部半導體晶片的所述主動面上，其中所述虛置間隔片暴露出所述頂部半導體晶片的所述至少一接合區。
  8. 如申請專利範圍第7項所述的製造方法，其中在形成所述第二絕緣密封體之後，減少所述第一絕緣密封體的厚度及所述第二絕緣密封體的厚度，且在減少所述第一絕緣密封體的厚度及所述第二絕緣密封體的厚度之後，所述虛置間隔片的表面與所述第一絕緣密封體的表面及所述第二絕緣密封體的表面共面。
  9. 如申請專利範圍第6項所述的製造方法，其中所述晶片堆疊體的每一所述多個半導體晶片具有連接至所述至少一接合區的側面，且在形成所述第一絕緣密封體之後，所述第一絕緣密封體覆蓋每一所述多個半導體晶片的所述側面。
  10. 如申請專利範圍第6項所述的製造方法，更包括： 提供臨時載板，其中所述晶片堆疊體配置於所述臨時載板上；以及 在形成所述重佈線路層之後，移除所述臨時載板，其中所述晶片堆疊體的遠離所述重佈線路層的底部半導體晶片具有相對於主動面的背面，且在移除所述臨時載板之後，所述底部半導體晶片的所述背面與所述第二絕緣密封體的表面共面。
TW107127490A 2018-03-27 2018-08-07 半導體封裝及其製造方法 TWI668825B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/936,444 2018-03-27
US15/936,444 US10276545B1 (en) 2018-03-27 2018-03-27 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TWI668825B TWI668825B (zh) 2019-08-11
TW201943039A true TW201943039A (zh) 2019-11-01

Family

ID=66248175

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107127490A TWI668825B (zh) 2018-03-27 2018-08-07 半導體封裝及其製造方法

Country Status (2)

Country Link
US (1) US10276545B1 (zh)
TW (1) TWI668825B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739862A (zh) * 2020-05-14 2020-10-02 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装结构制作方法
US11158608B2 (en) 2019-09-25 2021-10-26 Powertech Technology Inc. Semiconductor package including offset stack of semiconductor dies between first and second redistribution structures, and manufacturing method therefor
TWI763550B (zh) * 2020-12-21 2022-05-01 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI782411B (zh) * 2020-06-19 2022-11-01 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI819491B (zh) * 2021-09-22 2023-10-21 日商鎧俠股份有限公司 半導體裝置及半導體裝置的製造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112017008335T5 (de) * 2017-12-28 2020-09-03 Intel Corporation Multi-Die, Vertikal-Draht-Package-in-Package-Vorrichtung und Verfahren zum Herstellen desselben
KR20210022321A (ko) * 2019-08-20 2021-03-03 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
CN111554669A (zh) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装结构制作方法
CN113871374A (zh) * 2020-06-30 2021-12-31 西部数据技术公司 堆叠的裸芯封装体的斜坡状互连体
KR20230088502A (ko) 2020-11-25 2023-06-19 가부시키가이샤 신가와 반도체 장치의 제조 방법 및 반도체 장치의 제조 장치
CN112992696A (zh) * 2021-05-06 2021-06-18 通富微电子股份有限公司 堆叠芯片的封装方法和封装结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601761B1 (ko) * 2004-07-22 2006-07-19 삼성전자주식회사 이중 성형된 반도체 패키지 제조 방법
CN100449743C (zh) * 2005-09-29 2009-01-07 南茂科技股份有限公司 芯片结构与堆叠式芯片封装结构
TWI415201B (zh) 2007-11-30 2013-11-11 矽品精密工業股份有限公司 多晶片堆疊結構及其製法
KR100855887B1 (ko) * 2008-02-25 2008-09-03 주식회사 메모리앤테스팅 스택형 반도체 패키지 및 그 스택 방법
KR20110138945A (ko) 2010-06-22 2011-12-28 하나 마이크론(주) 적층형 반도체 패키지
KR101800440B1 (ko) * 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
TWI481002B (zh) 2012-06-26 2015-04-11 矽品精密工業股份有限公司 具堆疊結構之封裝件及其製法
US10748873B2 (en) * 2015-09-23 2020-08-18 Intel Corporation Substrates, assembles, and techniques to enable multi-chip flip chip packages
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
KR20180130043A (ko) * 2017-05-25 2018-12-06 에스케이하이닉스 주식회사 칩 스택들을 가지는 반도체 패키지

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11158608B2 (en) 2019-09-25 2021-10-26 Powertech Technology Inc. Semiconductor package including offset stack of semiconductor dies between first and second redistribution structures, and manufacturing method therefor
CN111739862A (zh) * 2020-05-14 2020-10-02 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装结构制作方法
TWI782411B (zh) * 2020-06-19 2022-11-01 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI763550B (zh) * 2020-12-21 2022-05-01 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI819491B (zh) * 2021-09-22 2023-10-21 日商鎧俠股份有限公司 半導體裝置及半導體裝置的製造方法

Also Published As

Publication number Publication date
US10276545B1 (en) 2019-04-30
TWI668825B (zh) 2019-08-11

Similar Documents

Publication Publication Date Title
TWI668825B (zh) 半導體封裝及其製造方法
TWI757526B (zh) 具有橫向偏移堆疊之半導體晶粒之半導體裝置及製造其之方法
TWI714913B (zh) 封裝結構及其製造方法
CN111613612B (zh) 包括嵌入式表面贴装器件的半导体封装件及其形成方法
JP5118942B2 (ja) スルーシリコンビアスタックパッケージ及びその製造方法
TWI600124B (zh) 封裝的半導體元件、層疊封裝元件以及封裝半導體元件的方法
TWI556349B (zh) 半導體裝置的結構及其製造方法
TWI567897B (zh) 薄型扇出式多晶片堆疊封裝構造與製造方法
CN114914208A (zh) 半导体装置封装体及其制造方法
CN107978566A (zh) 堆叠封装结构的制造方法
JP4758678B2 (ja) 半導体装置
TW201913925A (zh) 使用導線接合之混合式添加結構之可堆疊記憶體晶粒
TWI585906B (zh) 超薄封裝上封裝ＰｏＰ之封裝
TW202002189A (zh) 封裝結構及其製造方法
CN215069985U (zh) 三维堆叠的扇出型封装结构
CN111128914A (zh) 一种低翘曲的多芯片封装结构及其制造方法
TW202008531A (zh) 封裝結構
CN110854093A (zh) 一种三维叠层封装结构及其制造方法
TWI620258B (zh) 封裝結構及其製程
TWI441312B (zh) 具有打線結構之三維立體晶片堆疊封裝結構
CN110867385A (zh) 一种封装结构及其制备方法
US10854576B2 (en) Semiconductor device and manufacturing method thereof
CN110660752A (zh) 半导体装置封装体及其制造方法
US11682602B2 (en) Semiconductor device and method of manufacture
CN209804637U (zh) 半导体封装结构