JP4758678B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4758678B2 JP4758678B2 JP2005143402A JP2005143402A JP4758678B2 JP 4758678 B2 JP4758678 B2 JP 4758678B2 JP 2005143402 A JP2005143402 A JP 2005143402A JP 2005143402 A JP2005143402 A JP 2005143402A JP 4758678 B2 JP4758678 B2 JP 4758678B2
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- semiconductor
- semiconductor component
- interposer substrate
- semiconductor device
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
2 半導体部品(第1半導体部品)
2A 半導体チップ(第1半導体チップ)
2B 多層配線層(配線層)
2C 再配線層
3 半導体部品(第2半導体部品)
3A 半導体チップ(第2半導体チップ)
4a アンダーフィル
4b アンダーフィル
5 バンプ電極(第3バンプ)
6 ソルダーレジスト
8a,8b ランド
10 表面保護膜
11 絶縁膜
12 再配線
12a 主導体膜
12b メッキ層
13 表面保護膜
15 メッキ層
18 バンプ電極(第1バンプ)
20 配線基板
20a 開口部
20b ランド
21 樹脂封止部
22 接着シート
23 バンプ電極(第2バンプ)
24 樹脂封止部
28a ソケット
28b 蓋
30 マザーボード
31 放熱シート
32 筐体
BP ボンディングパッド
BW ボンディングワイヤ
Claims (5)
- インタポーザ基板と、
第1の熱膨張係数を備えた第1半導体チップを有し、かつ前記インタポーザ基板に、複数の第1バンプを介して実装された第1半導体部品と、
前記第1の熱膨張係数よりも高い第2の熱膨張係数を備えた配線基板、前記配線基板に搭載された第2半導体チップ、および前記第2半導体チップを封止する樹脂封止部を有し、かつ前記インタポーザ基板に、複数の第2バンプを介して実装された第2半導体部品と、
第3の熱膨張係数を備え、かつ前記インタポーザ基板と前記第1半導体部品との間に介在された第1アンダーフィルと、
前記第3の熱膨張係数よりも高い第4の熱膨張係数を備え、かつ前記インタポーザ基板と前記第2半導体部品との間に介在された第2アンダーフィルと、
を含み、
前記第1半導体部品は、前記配線基板を有していないことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記複数の第2バンプのピッチの方が、前記複数の第1バンプのピッチよりも大きいことを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記複数の第2バンプの高さは、前記複数の第1バンプの高さよりも高いことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1半導体チップにはロジック回路が形成されており、前記第2半導体チップにはメモリ回路が形成されており、
動作時における前記第2半導体チップの発熱量は、動作時における前記第1半導体チップの発熱量よりも高いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記インタポーザ基板は、厚さ方向に沿って互いに反対側になる第1面および第2面を有し、
前記第1半導体部品は、前記インタポーザ基板の前記第1面上に実装され、
前記第2半導体部品は、前記インタポーザ基板の前記第1面上において前記第1半導体部品の隣に実装され、
前記第2半導体部品の実装高さは、前記第1半導体部品の実装高さよりも高く、
前記インタポーザ基板の前記第2面には、複数の第3バンプが接合されていることを特徴とする半導体装置。
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JP2005143402A JP4758678B2 (ja) | 2005-05-17 | 2005-05-17 | 半導体装置 |
KR1020060043619A KR101153693B1 (ko) | 2005-05-17 | 2006-05-16 | 반도체 장치 |
US11/434,745 US7547968B2 (en) | 2005-05-17 | 2006-05-17 | Semiconductor device |
US12/470,562 US7834455B2 (en) | 2005-05-17 | 2009-05-22 | Semiconductor device |
US12/906,775 US8101468B2 (en) | 2005-05-17 | 2010-10-18 | Method of manufacturing a semiconductor device |
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JP2010056162A (ja) * | 2008-08-26 | 2010-03-11 | Fujitsu Ltd | 半導体装置および回路基板組立体 |
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KR102491103B1 (ko) * | 2018-02-06 | 2023-01-20 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
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US7547968B2 (en) | 2009-06-16 |
JP2006324271A (ja) | 2006-11-30 |
US8101468B2 (en) | 2012-01-24 |
KR20060119769A (ko) | 2006-11-24 |
US7834455B2 (en) | 2010-11-16 |
US20060264022A1 (en) | 2006-11-23 |
US20090230551A1 (en) | 2009-09-17 |
US20110033983A1 (en) | 2011-02-10 |
KR101153693B1 (ko) | 2012-06-18 |
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