CN103151341B - 系统级封装结构 - Google Patents

系统级封装结构 Download PDF

Info

Publication number
CN103151341B
CN103151341B CN201310079332.9A CN201310079332A CN103151341B CN 103151341 B CN103151341 B CN 103151341B CN 201310079332 A CN201310079332 A CN 201310079332A CN 103151341 B CN103151341 B CN 103151341B
Authority
CN
China
Prior art keywords
keyset
packaging
chip
vertical
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310079332.9A
Other languages
English (en)
Other versions
CN103151341A (zh
Inventor
王志
庞诚
于大全
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN201310079332.9A priority Critical patent/CN103151341B/zh
Publication of CN103151341A publication Critical patent/CN103151341A/zh
Application granted granted Critical
Publication of CN103151341B publication Critical patent/CN103151341B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本发明涉及一种系统级封装结构,包括封装基板及堆叠在封装基板正面的转接板,在转接板上堆叠至少一个第一芯片;其特征是:在所述转接板的一侧设置缺口,在该缺口处设置至少一个第二芯片,第二芯片和转接板均置于封装基板的正面。在所述转接板的缺口边缘设置电磁屏蔽结构,电磁屏蔽结构包括若干个垂直通孔和设置在垂直通孔底部的金属垫,在垂直通孔中填充金属,垂直通孔之间由位于转接板正面和背面的正面金属连线和背面金属连线相连接。本发明所述的系统级封装结构,采用特殊形状的转接板解决某些芯片或元器件难以集成于转接板之上的问题,达到了封装小型化的目的。

Description

系统级封装结构
技术领域
本发明涉及一种系统级封装结构,属于三维集成电路应用技术领域。
背景技术
随着人们对电子产品小型化、系统化、多功能等方向的持续追求,超大规模集成电路特征尺寸在不断缩小。但是,当IC的特征尺寸即将达到物理极限时,人们不得不去寻求新技术、新设计、新材料来“超越摩尔”。以2.5D、3D为代表的系统级封装技术就是人们在“超越摩尔”之路上的一个里程碑。3D封装是采用硅通孔技术以垂直短线方式取代传统的芯片互连线方法(无需打线绑定);2.5D封装是指堆叠硅片互联技术。
系统级封装技术(system in package,SIP)是将一个系统或子系统的全部或大部份电子功能配置在整合型基板内,而芯片以2D、3D的方式接合到整合型基板的封装方式。SIP不仅可以组装多个芯片,还可以作为一个专门的处理器、DRAM(动态随机存取存储器)、快闪存储器与被动元件结合电阻器和电容器、连接器、天线等,全部安装在同一基板上。
利用转接板进行系统集成的2.5DIC是系统级封装技术中的先进代表。2.5DIC既是3DIC的前导技术,又可以以独立的形式与其他先进的系统级封装技术长期共存。2.5DIC是将不同的芯片置于转接板上,通过该转接板进行扇出与芯片间互联,以达到提高系统内部带宽、解决热应力失配等封装中常见的一些问题。
但是,现阶段由于转接板的自身局限和组装工艺的限制,仍然有一些芯片或元器件难以集成于转接板之上。利用传统结构的转接板进行系统集成就不可避免的将这些芯片置于转接板之外,封装基板之上,这无疑增加了整个封装系统的面积,不符合系统小型化的趋势。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种系统级封装结构,采用特殊形状的转接板解决某些芯片或元器件难以集成于转接板之上的问题,达到了封装小型化的目的。
按照本发明提供的技术方案,一种系统级封装结构,包括封装基板及堆叠在封装基板正面的转接板,在转接板上堆叠至少一个第一芯片;其特征是:在所述转接板的一侧设置缺口,在该缺口处设置至少一个第二芯片,第二芯片和转接板均置于封装基板的正面。
作为本发明的进一步改进,在所述转接板的缺口边缘设置电磁屏蔽结构,电磁屏蔽结构包括若干个垂直通孔和设置在垂直通孔底部的金属垫,在垂直通孔中填充金属,垂直通孔之间由位于转接板正面和背面的正面金属连线和背面金属连线相连接。
所述缺口的形状为直线形、弧形或直角状。
所述垂直通孔中填充的金属为铜、钨、钛、铝或上述一种或多种的合金;所述正面金属连线、背面金属连线和金属垫的材料为铜、钨、钛、铝或上述一种或多种的合金。
所述转接板通过第一焊球堆叠在封装基板的正面;所述电磁屏蔽结构通过金属垫与第一焊球电连接。
所述电磁屏蔽结构通过第一焊球与封装基板背面的接地焊球电连接。
所述第一芯片通过第二焊球堆叠在转接板上。
所述封装基板为有机基板、陶瓷基板或金属基板。
所述转接板的材料为硅或者玻璃。
本发明所述的系统级封装结构,采用特殊形状的转接板解决某些芯片或元器件难以集成于转接板之上的问题,达到了封装小型化的目的;另一方面本发明具有用于减小芯片间干扰的电磁屏蔽结构。
附图说明
图1为本发明的结构示意图。
图2为图1的俯视图。
图3为所述转接板缺口呈弧形的封装结构的示意图。
图4为所述转接板缺口呈直角形的封装结构的示意图。
图5为具有电磁屏蔽结构的封装结构的示意图。
图6为图5的侧视图。
具体实施方式
下面结合具体附图对本发明作进一步说明。
如图1~图6所示:所述系统级封装结构包括第一芯片1、第二芯片2、转接板5、封装基板6、缺口7、电磁屏蔽结构10、垂直通孔11、正面金属连线12、背面金属连线13、金属垫14、第一焊球15、第二焊球17等。
如图1所示,本发明包括封装基板6及通过第一焊球15堆叠在封装基板6正面的转接板5,在转接板5上通过第二焊球17堆叠至少一个第一芯片1,转接板5的一侧设置缺口7,在该缺口7处设置至少一个第二芯片2,第二芯片2和转接板5均置于封装基板6的正面;
如图5所示,在所述转接板5的缺口7边缘设置电磁屏蔽结构10,电磁屏蔽结构10包括若干个垂直通孔11和设置在垂直通孔11底部的金属垫14,在垂直通孔11中填充金属,填充的金属为铜、钨、钛、铝或上述一种或多种的合金,垂直通孔11之间由位于转接板5正面和背面的正面金属连线12和背面金属连线13相连接;所述正面金属连线12、背面金属连线13和金属垫14的材料为铜、钨、钛、铝或上述一种或多种的合金;
如图6所示,所述电磁屏蔽结构10通过金属垫14与第一焊球15电连接,最终电磁屏蔽结构10通过第一焊球15与封装基板6背面的接地焊球电连接;所述第一焊球15和第二焊球17为C4焊球或其他焊球,第一焊球15和第二焊球17也可以由其他电学互联方式代替;
如图2、图3、图4所示,所述缺口7的形状为直线形、弧形或直角状,也可以是其他形状的缺口;所述缺口7可以采用等离子刻蚀技术、激光刻蚀技术得到,也要以通过其他技术得到;
所述封装基板6采用有机基板、陶瓷基板或金属基板;
所述转接板5的材料为硅或者玻璃;
所述第一芯片1一般为存储器芯片、逻辑芯片等,也可以是一般芯片;所述第二芯片2为不易置于转接板上的芯片,也可以是一般芯片;
所述电磁屏蔽结构10的垂直通孔11之间的间距可以根据辐射电磁波的波长或其他电磁屏蔽要求来决定,一般为工艺能力所能达到的最小间距,一般为几微米至几百微米;该间距越小,对高频电磁波的屏蔽效果越好。

Claims (8)

1.一种系统级封装结构,包括封装基板(6)及堆叠在封装基板(6)正面的转接板(5),在转接板(5)上堆叠至少一个第一芯片(1);其特征是:在所述转接板(5)的一侧设置缺口(7),在该缺口(7)处设置至少一个第二芯片(2),第二芯片(2)和转接板(5)均置于封装基板(6)的正面;
在所述转接板(5)的缺口(7)边缘设置电磁屏蔽结构(10),电磁屏蔽结构(10)包括若干个垂直通孔(11)和设置在垂直通孔(11)底部的金属垫(14),在垂直通孔(11)中填充金属,垂直通孔(11)之间由位于转接板(5)正面和背面的正面金属连线(12)和背面金属连线(13)相连接。
2.如权利要求1所述的系统级封装结构,其特征是:所述缺口(7)的形状为直线形、弧形或直角状。
3.如权利要求1所述的系统级封装结构,其特征是:所述垂直通孔(11)中填充的金属为铜、钨、钛、铝或上述一种或多种的合金;所述正面金属连线(12)、背面金属连线(13)和金属垫(14)的材料为铜、钨、钛、铝或上述一种或多种的合金。
4.如权利要求1所述的系统级封装结构,其特征是:所述转接板(5)通过第一焊球(15)堆叠在封装基板(6)的正面;所述电磁屏蔽结构(10)通过金属垫(14)与第一焊球(15)电连接。
5.如权利要求4所述的系统级封装结构,其特征是:所述电磁屏蔽结构(10)通过第一焊球(15)与封装基板(6)背面的接地焊球电连接。
6.如权利要求1所述的系统级封装结构,其特征是:所述第一芯片(1)通过第二焊球(17)堆叠在转接板(5)上。
7.如权利要求1所述的系统级封装结构,其特征是:所述封装基板(6)为有机基板、陶瓷基板或金属基板。
8.如权利要求1所述的系统级封装结构,其特征是:所述转接板(5)的材料为硅或者玻璃。
CN201310079332.9A 2013-03-13 2013-03-13 系统级封装结构 Active CN103151341B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310079332.9A CN103151341B (zh) 2013-03-13 2013-03-13 系统级封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310079332.9A CN103151341B (zh) 2013-03-13 2013-03-13 系统级封装结构

Publications (2)

Publication Number Publication Date
CN103151341A CN103151341A (zh) 2013-06-12
CN103151341B true CN103151341B (zh) 2015-05-13

Family

ID=48549319

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310079332.9A Active CN103151341B (zh) 2013-03-13 2013-03-13 系统级封装结构

Country Status (1)

Country Link
CN (1) CN103151341B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910315B (zh) * 2017-11-10 2020-09-25 深圳市盛路物联通讯技术有限公司 芯片封装
CN115810618A (zh) * 2021-09-13 2023-03-17 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
CN114242685A (zh) * 2021-12-01 2022-03-25 展讯通信(上海)有限公司 双面封装组件及其形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102164258A (zh) * 2009-12-25 2011-08-24 索尼公司 电路基板层叠模块及电子设备
CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4758678B2 (ja) * 2005-05-17 2011-08-31 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102164258A (zh) * 2009-12-25 2011-08-24 索尼公司 电路基板层叠模块及电子设备
CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装

Also Published As

Publication number Publication date
CN103151341A (zh) 2013-06-12

Similar Documents

Publication Publication Date Title
CN103137609B (zh) 带有电磁屏蔽结构的集成电路封装结构
US20200168572A1 (en) Semiconductor package assembly having a conductive electromagnetic shield layer
US8159052B2 (en) Apparatus and method for a chip assembly including a frequency extending device
US8946900B2 (en) X-line routing for dense multi-chip-package interconnects
US9029928B2 (en) Semiconductor device comprising a passive component of capacitors and process for fabrication
US20140021591A1 (en) Emi shielding semiconductor element and semiconductor stack structure
CN103688353B (zh) 微电子器件、层叠管芯封装及包含层叠管芯封装的计算系统、制造层叠管芯封装中的多通道通信路径的方法以及实现层叠管芯封装的部件之间的电通信的方法
KR20160067961A (ko) 패키징된 다이용 세라믹 상의 안테나
US20130320513A1 (en) Semiconductor package and fabrication method thereof
CN108701680B (zh) 带有使用金属层和通孔的电磁干扰屏蔽的半导体封装
CN110663113A (zh) 经屏蔽的扇出型封装半导体装置及制造方法
KR102620867B1 (ko) 브리지 다이를 포함한 반도체 패키지
JP2010199286A (ja) 半導体装置
US9907180B2 (en) Multilayer electronic device and manufacturing method therefor
TWI541976B (zh) 三維積體電路封裝
CN103151341B (zh) 系统级封装结构
US9530714B2 (en) Low-profile chip package with modified heat spreader
US20130087896A1 (en) Stacking-type semiconductor package structure
US9019032B2 (en) EBG structure, semiconductor device, and printed circuit board
US20150228602A1 (en) Semicondcutor chip and semionducot module
US9275876B2 (en) Stiffener with embedded passive components
US20090273074A1 (en) Bond wire loop for high speed noise isolation
US10056528B1 (en) Interposer structures, semiconductor assembly and methods for forming interposer structures
CN101150123B (zh) 具有电磁屏蔽罩盖的半导体封装结构
KR20170138644A (ko) Pop 구조의 반도체 어셈블리 및 이를 포함하는 전자 장치

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: JIANGSU CAS INTERNET-OF-THING TECHNOLOGY VENTURE C

Free format text: FORMER OWNER: JIANGSU INTERNET OF THINGS RESEARCH + DEVELOMENT CO., LTD.

Effective date: 20130829

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20130829

Address after: 214135 Jiangsu New District of Wuxi City Linghu Road No. 200 China Sensor Network International Innovation Park building C

Applicant after: Jiangsu CAS Internet-Of-Thing Technology Venture Capital Co., Ltd.

Address before: 214135 Jiangsu New District of Wuxi City Linghu Road No. 200 China Sensor Network International Innovation Park building C

Applicant before: Jiangsu Internet of Things Research & Develoment Co., Ltd.

ASS Succession or assignment of patent right

Owner name: NATIONAL CENTER FOR ADVANCED PACKAGING

Free format text: FORMER OWNER: JIANGSU CAS INTERNET-OF-THING TECHNOLOGY VENTURE CAPITAL CO., LTD.

Effective date: 20140409

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20140409

Address after: 214135 Jiangsu Province, Wuxi City Linghu Wuxi national hi tech Industrial Development Zone, Road No. 200 Chinese Sensor Network International Innovation Park building D1

Applicant after: National Center for Advanced Packaging Co., Ltd.

Address before: 214135 Jiangsu New District of Wuxi City Linghu Road No. 200 China Sensor Network International Innovation Park building C

Applicant before: Jiangsu CAS Internet-Of-Thing Technology Venture Capital Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170818

Address after: 200331 room 155-2, ginkgo Road, Shanghai, Putuo District, China, 4

Patentee after: Shanghai State Intellectual Property Services Co., Ltd.

Address before: 214135 Jiangsu Province, Wuxi City Linghu Wuxi national hi tech Industrial Development Zone, Road No. 200 Chinese Sensor Network International Innovation Park building D1

Patentee before: National Center for Advanced Packaging Co., Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20191119

Address after: 214028 Jiangsu New District of Wuxi City Linghu Road No. 200 Chinese Sensor Network International Innovation Park building D1

Patentee after: National Center for Advanced Packaging Co., Ltd.

Address before: 200331 room 155-2, ginkgo Road, Shanghai, Putuo District, China, 4

Patentee before: Shanghai State Intellectual Property Services Co., Ltd.