CN110663113A - 经屏蔽的扇出型封装半导体装置及制造方法 - Google Patents

经屏蔽的扇出型封装半导体装置及制造方法 Download PDF

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CN110663113A
CN110663113A CN201880033776.XA CN201880033776A CN110663113A CN 110663113 A CN110663113 A CN 110663113A CN 201880033776 A CN201880033776 A CN 201880033776A CN 110663113 A CN110663113 A CN 110663113A
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conductive
semiconductor die
redistribution structure
encapsulant
electrically coupled
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渡边住友
草薙京叶
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明技术的若干方面涉及具有集成式屏蔽件以防止受到电磁干扰的扇出型封装半导体装置及此类装置的制造方法。所述屏蔽件可通过在重布结构上形成导电壁并将导电盖安置到包封物的上部表面上而建构成。所述导电壁与所述导电盖彼此电连接。通过直接在所述重布结构上形成所述导电壁并将所述导电盖单独地安置到所述包封物的上部表面上，可使用高效且有成本效益的晶片级或面板级处理技术容易地形成电磁屏蔽件。因此，根据本发明技术的半导体装置的若干实施例屏蔽半导体裸片的集成电路免受电磁干扰。

Description

经屏蔽的扇出型封装半导体装置及制造方法
技术领域
本发明技术大体上涉及半导体装置。具体地说，本发明技术的若干实施例涉及具有集成式屏蔽件以防止受到电磁干扰的扇出型封装半导体装置及此类装置的制造方法。
背景技术
微电子装置大体上具有半导体裸片(即，芯片)，其包含具有高密度的极小组件的集成电路。通常，裸片包含电耦合到集成电路的极小接合垫阵列。接合垫为外部电触点，供应电压、信号等通过所述接合垫发射到集成电路并从集成电路进行发射。在形成裸片之后，“封装”裸片以将接合垫耦合到可较容易地耦合到各种电力供应线、信号线及接地线的较大电端子阵列。用于封装裸片的常规过程包含将裸片上的接合垫电耦合到插入件衬底的导线、球垫或其它类型的电端子阵列。接着包封裸片以防止裸片受到环境因素(例如，水分、微粒、静电及物理冲击)的影响。
不同类型的半导体裸片可具有广泛不同的接合垫布置，且仍应与类似的外部装置兼容。因此，现有封装技术可包含将重布层附接到半导体裸片。重布层包含将裸片的接合垫与重布层的接合垫连接的线及/或通孔。重布层包含布置成与外部装置的电端子配合的导线、球垫或其它类型的电端子阵列。
一种挑战为电磁干扰会损害高性能半导体装置的操作。结果，可能需要屏蔽半导体裸片的集成电路免受电磁干扰。然而，预成型铜盖及其它形式的外部屏蔽件是昂贵的且可能并不实用。类似地，将完全嵌入于包封物内的预成型铜屏蔽件并入半导体装置的封装中也是昂贵的。
附图说明
参考下图可更好地理解本发明技术的许多方面。图中的组件不一定按比例绘制。实际上，重点是清楚地说明本发明技术的原理。
图1A为根据本发明技术的实施例的封装半导体装置的横截面图。
图1B为图1A的封装半导体装置的顶部平面图，其中为了清楚起见切除了各种层。
图2A到2H为根据本发明技术的实施例的用于形成封装半导体装置的方法的各个阶段的横截面图。
图3A为根据本发明技术的实施例的封装半导体装置的横截面图。
图3B为图3A的封装半导体装置的顶部平面图，其中为了清楚起见切除了各种层。
图4为根据本发明技术的实施例的封装半导体装置的横截面图。
图5为根据本发明技术的实施例的封装半导体装置的横截面图。
图6为根据本发明技术的实施例的封装半导体装置的横截面图。
图7为根据本发明技术的实施例的封装半导体装置的横截面图。
图8为根据本发明技术的实施例的封装半导体装置的横截面图。
图9为包含根据本发明技术的实施例配置的半导体装置的系统的示意图。
为了易于参考，贯穿本发明，相同附图标记用以识别类似或相似的组件或特征，但使用相同附图标记并不暗示所述部分应被理解为相同。实际上，在本文中所描述的许多实例中，相同编号的部分在结构及/或功能方面相异。此外，相同着色可用以指示横截面中的可能在组成上类似的材料，但使用相同着色并不暗示材料应被理解为相同。
另外，在以下描述中，论述了众多特定细节以提供对本发明技术的实施例的透彻且启发性描述。然而，相关领域的技术人员将认识到，可在并无特定细节中的一或多个的情况下实践本发明。在其它情况下，并不示出或并不详细描述常常与半导体装置相关联的熟知结构或操作，以免混淆技术的其它方面。一般来说，应理解，除了本文中所公开的那些特定实施例之外的各种其它装置、系统及方法可在本发明技术的范围内。
如本文中所使用，鉴于诸图中示出的定向，术语“竖直”、“横向”、“上部”及“下部”可指半导体裸片组合件中的特征的相对方向或位置。例如，“上部”或“最上部”可指比另一特征更接近页面的顶部定位的特征。然而，这些术语应广泛地理解为包含具有其它定向的半导体装置，所述定向例如倒置或倾斜定向，其中顶部/底部、上面/下面、上方/下方、向上/向下，及左侧/右侧可取决于定向而互换。
具体实施方式
下文描述半导体装置的若干实施例的特定细节。本发明技术的若干实施例的一个方面为通过在重布结构上形成导电壁，并在包封物的上部表面上安置导电盖来建构屏蔽结构。导电壁与导电盖彼此电连接。通过直接在重布结构上形成导电壁并将导电盖单独地安置到包封物的上部表面上，可使用高效且有成本效益的晶片级或面板级处理技术容易地形成电磁屏蔽件。因此，根据本发明技术的半导体装置的若干实施例屏蔽半导体裸片的集成电路免受电磁干扰。
根据本发明技术的若干实施例的封装半导体装置包含重布结构及半导体裸片。重布结构具有第一侧、第二侧及具有从第一侧到第二侧的厚度的介电形成物。重布结构还可包含第一侧处的裸片触点、第一侧处的至少一个屏蔽件触点及第二侧处的球垫。半导体裸片安装到重布结构的第一侧，且半导体裸片具有外周界。封装半导体装置可进一步包含导电壁、包封物及导电盖。导电壁在重布结构的第一侧上且与半导体裸片的外周界侧向间隔开。导电壁电耦合到屏蔽件触点，且导电壁围绕半导体裸片的外周界的至少一部分延伸。包封物覆盖半导体裸片的至少一部分且相对于半导体裸片的外周界侧向朝外延伸。导电盖附接到包封物且电耦合到导电壁。导电壁及导电盖形成被配置成防止半导体裸片受到电磁干扰的屏蔽结构。
图1A为根据本发明技术的实施例的封装半导体装置100(“装置100”)的横截面图，且图1B为图1A的装置100的顶部平面图，其中为了清楚起见切除了各种层。参考图1A，装置100包含半导体裸片110、支撑半导体裸片110的重布结构(RDS)120，及覆盖半导体裸片110的至少一部分且跨越RDS 120的表面侧向延伸的包封物140。装置100进一步包含导电壁160及电耦合到导电壁160的导电盖170。导电壁160电耦合到接地触点，使得导电壁160及导电盖170共同界定被配置成防止半导体裸片110受到电磁干扰的屏蔽结构。
半导体裸片110可包含半导体材料、导电材料及介电材料，其布置成形成集成电路或组件、数据存储元件、处理组件及/或在半导体衬底上制造的其它特征。例如，半导体裸片110可包含集成式存储器电路及/或逻辑电路，所述电路可包含各种类型的半导体组件及功能特征，例如动态随机存取存储器(DRAM)、静态随机存取记忆体(SRAM)、快闪存储器、其它形式的集成电路存储器、处理电路、成像组件及/或其它半导体特征。半导体裸片110可进一步包含电耦合到集成电路的接合垫112及附接到接合垫112的导电凸块114。在一些实施例中，装置100可包含可彼此相同(例如，制造成具有相同设计及规范的存储器裸片)或不同(例如，不同类型的存储器裸片或控制器、逻辑及/或存储器裸片的组合)的多个半导体裸片。
RDS 120具有第一侧121、第二侧122及具有从第一侧121到第二侧122的厚度的介电形成物124。RDS 120进一步包含第一侧121处的裸片触点125、第一侧121处的至少一个屏蔽件触点126、第二侧122处的球垫127，及将球垫127电耦合到裸片触点125及屏蔽件触点126的导电线128。在所说明的实施例中，裸片触点125及对应球垫127可在对应导电线128的相对端处。类似地，屏蔽件触点126及对应球垫127可在对应导电线128的相对端处。在图1A中说明的实施例中，半导体裸片110的个别接合垫112经由导电凸块114电耦合到裸片触点125中的对应一个。
包封物140具有覆盖半导体裸片110的至少一部分的在导电壁160内的第一部分142，及在导电壁160外部的第二部分144。包封物140的第一部分142可相对于半导体裸片的外周界116侧向朝外延伸到导电壁160的内表面161。第一部分142可包含完全覆盖半导体裸片110的背侧118的上部表面143，且包封物140的第一部分142也可填充半导体裸片110与RDS 120之间的间隙。替代地，半导体裸片110与RDS 120之间的间隙可由底部填充材料填充。包封物140的第二部分144可从导电壁160的外表面162侧向朝外延伸。包封物140的第二部分144可具有与包封物140的第一部分142的上部表面143共面的上部表面145。包封物140的第一部分142及第二部分144可由相同材料制成，或替代地，第一部分142与第二部分144可为不同材料。
包封物140可为使用喷嘴或其它类型的沉积技术沉积到RDS 120上的密封树脂。替代地，可使用注射模制或其它模制技术将包封物140模制到RDS 120上及半导体裸片110周围。
导电壁160可为形成于RDS 120的第一侧121上的侧壁，使得导电壁160的至少一部分接触RDS 120的屏蔽件触点126中的一或多个。一起参考图1A及1B，可通过沉积银、焊料、铜或其它合适的导电材料来形成导电壁160，使得导电壁160围绕半导体裸片110的外周界116的至少一部分延伸。参考图1B，导电壁160可完全围绕半导体裸片110的周界116延伸，但在其它实施例中，导电壁160可具有由间隙彼此分离的离散分段。例如，导电壁160可具有每一分段从外周界116的对应侧侧向朝外间隔开的四个分段，或在其它实施例中，导电壁160可具有两个L形分段等。导电壁160可具有与包封物140的上部表面143共面的顶部表面163，及电耦合到屏蔽件触点126中的一或多个的底部表面164。导电壁160的底部表面164可搁置在屏蔽件触点126及/或介电形成物124的上部表面上。在任一情况下，导电壁160电耦合到RDS 120的第二侧122上的焊球130或其它电连接件。
导电盖170可通过导电粘附剂172附接到包封物140的上部表面143及导电壁160的顶部表面163。导电盖170可完全覆盖导电壁160内的区域。例如，导电盖170可覆盖包封物140的第一部分142(包含包封物140的在半导体裸片110的背侧118上面的部分)，及导电壁160的顶部表面163的至少一部分。在其它实施例中，导电盖170可具有开口、槽、通道或其它类型的空隙，使得导电盖170并不完全覆盖导电壁160内的区域。导电盖170可为经预成型且使用导电粘附剂172附接到包封物140的第一部分142及导电壁160的铜面板。在其它实施例中，导电盖170可为以其它方式安置于包封物140及导电壁160上的一或多层导电材料。
在操作中，导电壁160及导电盖170可经由RDS 120的第二侧122上的对应焊球130电耦合到接地。导电壁160及导电盖170一起形成被配置成屏蔽半导体裸片110免受电磁干扰的屏蔽结构。本发明技术的实施例的一个优点在于，可在晶片级或面板级处形成屏蔽结构，这是因为可使用用于晶片级或面板级处理的已知技术将用于个别封装装置100的个别导电壁160形成为用于若干不同装置。类似地，导电盖170可使用已知晶片级或面板级处理技术安装到对应装置100。结果，预期本发明技术能有效地生产经屏蔽的封装半导体装置。
图2A到2H为说明用于使用晶片级或面板级制造技术形成图1A的装置100的实施例的方法的各个阶段的横截面图。更确切地说，完整装置100说明为形成于中间且两个额外装置的部分说明为形成于完整装置的左侧及右侧。尽管图2A到2H中仅示出单个完整装置100，但将了解，可使用晶片级或面板级处理同时封装多个装置。
图2A示出在(a)RDS 120已形成且附接到载体200，及(b)导电壁160已形成于RDS120的第一侧121上之后的方法阶段。载体200为后续处理阶段提供机械支撑，且可为由例如硅、绝缘体上硅、化合物半导体(例如，氮化镓)、玻璃或其它合适材料形成的临时载体。在一些实施例中，载体200覆盖有释放层210，使得在已从释放层210去除封装装置之后可重新使用载体200。释放层210防止RDS 120与载体200直接接触，以防止RDS 120受到污染或物理损害。释放层210可为一次性薄膜(例如，环氧类材料的层压薄膜)或其它合适的材料。在一些实施例中，释放层210为便于在后续阶段去除的激光敏感或光敏材料。
导电壁160可通过将导电材料安置于RDS 120的第一侧121上而形成。导电材料的至少一部分接触屏蔽件触点126中的至少一个。在一个实施例中，首先将基座220沉积在RDS120的第一侧121上且在基座220中形成开口222。接着跨越RDS 120的第一侧121将导电材料沉积于开口222中以形成导电壁160。导电壁160的导电材料可为导电膏，例如银膏或焊膏。导电膏可任选地经回焊，使得经回焊膏的表面张力致使导电材料保持于开口222内且远离RDS 120的第一表面121突出。在其它实施例中，可通过将导电材料三维印刷到RDS 120的第一表面121上及屏蔽件触点126上面来形成导电壁160。在再额外实施例中，可通过电镀、化学镀、气相沉积技术及/或其它金属化技术来形成导电壁。
图2B到2E说明在半导体裸片110已安装到RDS 120及包封物140已安置于半导体裸片110上面之后的后续阶段。更确切地说，图2B说明将半导体裸片110安裝到RDS120的第一侧121，使得半导体裸片110的接合垫112经由导电凸块114电耦合到RDS 120的裸片垫125。图2C说明在包封物140的材料已安置于半导体裸片110及导电壁160上面之后的方法。可使用注射模制技术、其它模制技术，或通过使用围绕晶片或面板的周界的挡板跨越RDS 120的前侧121流动包封物140的材料来安置包封物140。包封物140可经配置以完全覆盖导电壁160以及半导体裸片110。在所说明的实施例中，包封物140也可填充半导体裸片110与RDS120的第一表面121之间的间隙，或可由单独的底部填充材料来填充间隙。图2D说明在包封物140已充分固化以提供半导体裸片110的结构完整性及已去除载体200之后的方法。
图2E说明在包封物140的上部表面143及导电线160的顶部表面163已形成之后的方法。上部表面143及顶部表面163可通过磨削、化学机械抛光、蚀刻或其它用于去除包封物140的上部部分及导电壁160的导电材料的上部部分的合适技术来形成。在所说明的实施例中，图2D中示出的包封物140的材料的上部部分及导电壁160的上部部分已经研磨，以形成导电壁160的暴露顶部表面163，而留下包封物140的在半导体裸片110的背侧118上面的一部分。结果，包封物140的上部表面143与导电壁160的顶部表面163彼此共面。在其它实施例中，包封物140的上部表面143及导电线160的顶部表面163的高度可与半导体裸片110的背侧118共面。在此方法阶段处形成导电壁160的顶部表面163进一步(a)在导电壁160之间的定位半导体裸片110的区域中形成包封物140的第一部分142，及(b)在导电壁160之间的定位切割道“L”之区域中形成包封物140的第二部分144。
图2F说明在导电盖170已附接到包封物140的上部表面143及导电壁160的顶部表面163之后的方法阶段。可使用导电粘附剂172将导电盖170附接到导电壁160的顶部表面163。在所说明的实施例中，导电盖170也附接到在半导体裸片110上面的包封物140的第一部分142的上部表面143。在包封物140的上部表面143与半导体裸片110的背侧118共面的实施例中，导电盖170可直接附接到半导体裸片110的背侧118以增强来自半导体裸片110的热耗散。导电盖170及其所附接到的对应导电壁160一起形成用于防止半导体裸片110受到电磁干扰的屏蔽结构。
图2G说明在焊球130已沉积在RDS 120的球垫127上之后的阶段。图2H说明通过沿着切割道“L”切穿包封物140的第二部分144来形成个别装置100。
图3A为根据本发明技术的实施例的封装半导体装置300(“装置300”)的横截面图，且图3B为图3A的装置300的顶部平面图，其中为了清楚起见切除了各种层。参考图3A，装置300包含通过电镀或其它金属化技术形成的导电壁360。在此实例中，半导体裸片110附接到RDS 120，且在形成导电壁360之前将包封物140的材料安置于半导体裸片110及RDS 120上面。在已安置包封物140之后，形成穿过包封物140的开口，使得穿过包封物140的开口与屏蔽件触点126对准。接着可使用屏蔽件触点126将导电材料镀覆到开口中。例如，可使用溅镀或化学气相沉积技术将铜或其它合适导电材料的晶种层沉积到开口中，且接着可使用电镀或化学镀技术将铜或另一合适的导电材料镀覆到开口中。
图3B说明导电壁360具有四个单独分段的实施例，其中每一分段与半导体裸片110的对应边缘间隔开。替代地，其它实施例可包含在两个笔直分段之间具有导电材料拐角362(以虚线示出)的两个L形分段。将了解，相比图1B及3B中所示的那些间隙，导电壁在个别分段之间可具有更少或更多的间隙。
图4为根据本发明技术的实施例的封装半导体装置400(“装置400”)的横截面图。除了装置400包含多级重布结构(RDS)420，所述多级RDS包含介电形成物424及多个导电层之外，装置400类似于上文所描述的装置100。RDS 420例如具有包含裸片触点425及屏蔽件触点126的第一导电级，及包含屏蔽组件460及球垫427的第二导电级。在图4中说明的实施例中，屏蔽组件460电耦合到第一导电级处的导电线428，使得屏蔽组件460、半导体裸片110的接合垫112(例如，最左边接合垫112)、导电壁160与导电盖170都彼此电耦合。结果，屏蔽组件460、导电壁160及导电盖170一起形成防止半导体裸片110受到电磁干扰的屏蔽结构。
图5为根据本发明技术的实施例的封装半导体装置500(“装置500”)的横截面图。装置500类似于装置400，但与附接到包封物140及导电壁160的预成型导电面板相对，装置500包含形成于包封物140的上部表面143及导电壁160的顶部表面163上的导电盖570。例如，可通过使用电镀、化学镀、气相沉积或其它用于沉积金属的合适技术沉积铜或其它合适的导电材料来将导电盖570形成于包封物140及导电壁160上。因此，此实施例消除了对预成型金属盖及粘附剂的需要。
图6到8分别为具有多个半导体裸片的封装半导体装置600、700及800的横截面图。图1A到8中的相似附图标记指代类似或甚至相同的组件。装置600、700及800中的每一个包含至少第一半导体裸片110a及第二半导体裸片110b(统称为“第一及第二裸片110a-b”)。第一及第二裸片110a-b可彼此相同或其可为不同类型的裸片。例如，第一及第二裸片110a-b可为相同或类似类型的存储器裸片，或第一半导体裸片110a可为存储器裸片而第二半导体裸片110b可为逻辑裸片或处理器裸片。
参考图6，半导体装置600(“装置600”)具有如上文关于装置100所描述的RDS 120、导电壁160及顶盖170。在此实施例中，第一及第二裸片110a-b两者都处于包封物140的共用部分中。如同装置100，导电盖170及导电壁160电耦合在一起，且形成防止第一及第二裸片110a-b受到电磁干扰的屏蔽件。
参考图7，半导体装置700(“装置700”)具有在装置700的外周界附近的导电壁160，及将导电壁160内的包封物140的第一部分划分成第一区段742a及第二区段742b的内导电分区760。装置700还包含多级RDS 720，其包含屏蔽组件770。内导电分区760可电耦合到屏蔽组件770，且屏蔽组件770中的至少一个可电耦合到导电壁160及顶盖170。因而，内导电分区760、屏蔽组件770、导电壁160及顶盖170可围绕第一及第二裸片110a-b中的每一个形成屏蔽结构，以防止第一及第二裸片110a-b受到电磁干扰。
参考图8，半导体装置800(“装置800”)类似于装置700但仅完全屏蔽第一半导体裸片110a。更确切地说，导电壁160仅围绕第一半导体裸片110a而非装置800的完整外周界部分延伸。第二半导体裸片110b的一侧未被屏蔽。
上文参考图1A到8描述的半导体装置中的任一个可并入到大量更大及/或更复杂系统中的任一个中，所述系统的代表性实例为图9中示意性地示出的系统990。系统990可包含半导体裸片组合件900、电源992、驱动器994、处理器996及/或其它子系统或组件998。半导体裸片组合件900可包含特征大体上类似于上文所描述的半导体装置的那些特征的半导体装置。所得系统990可执行广泛多种功能中的任一种，例如存储器存储、数据处理及/或其它合适的功能。因此，代表性系统990可包含但不限于手持式装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及器具。系统990的组件可容纳于单个单元中或分布在多个互连的单元上面(例如，通过通信网络)。系统990的组件还可包含远程装置及广泛多种计算机可读媒体中的任一种。
从上文将了解，本文中已经出于说明的目的描述了本发明的特定实施例，但可在不偏离本发明范围的情况下进行各种修改。因此，本发明不受除所附权利要求书之外的限制。

Claims (20)

1.一种封装半导体装置，其包括：
重布结构，其具有第一侧、第二侧、具有从所述第一侧到所述第二侧的厚度的介电形成物、在所述重布结构的所述第一侧处的裸片触点、在所述重布结构的所述第一侧处的至少一个屏蔽件触点，及在所述重布结构的所述第二侧处的球垫；
半导体裸片，其安装在所述重布结构的所述第一侧上，其中所述半导体裸片具有外周界；
导电壁，其在所述重布结构的所述第一侧上、与所述半导体裸片的所述外周界侧向间隔开，其中所述导电壁电耦合到所述屏蔽件触点，且围绕所述半导体裸片的所述外周界的至少一部分延伸；
包封物，其覆盖所述半导体裸片的至少一部分且相对于所述半导体裸片的所述外周界侧向朝外延伸；及
导电盖，其附接到所述包封物且电耦合到所述导电壁，使得所述导电壁及所述导电盖形成被配置成防止所述半导体裸片受到电磁干扰的屏蔽件。
2.根据权利要求1所述的装置，其中：
所述导电壁具有在所述重布结构的所述第一侧处的底部表面、与所述重布结构的所述第一侧间隔开的顶部表面、面朝所述半导体裸片的内表面及背对所述半导体裸片的外表面；
所述包封物具有第一部分及第二部分，其中所述第一部分具有与所述导电壁的所述顶部表面共面的上部表面且所述第一部分在所述半导体裸片与所述导电壁的所述内表面之间侧向地延伸，且其中所述第二部分从所述导电壁的所述外表面侧向朝外延伸；且
所述导电盖直接附接到所述导电壁的所述顶部表面及所述包封物的所述上部表面。
3.根据权利要求2所述的装置，其中所述重布结构为多级重布结构，其进一步包括嵌入所述第一侧与所述第二侧之间的所述介电形成物中的屏蔽组件，其中所述屏蔽组件在所述半导体裸片下方且电耦合到所述导电壁及所述导电盖。
4.根据权利要求2所述的装置，其中所述导电盖包括金属板。
5.根据权利要求2所述的装置，其中所述导电盖包括沉积在所述导电壁的所述顶部表面及所述包封物的所述上部表面上的至少一个金属层。
6.根据权利要求1所述的装置，其进一步包括：
第二半导体裸片，其在与所述第一半导体裸片侧向间隔开的位置处附接到所述重布结构的所述第一侧；及
导电内分区，其形成于所述重布结构的所述第一侧上且电耦合到所述屏蔽件触点，其中所述导电内分区在所述第一半导体裸片与所述第二半导体裸片之间。
7.根据权利要求6所述的装置，其中所述包封物具有第一部分及第二部分，所述第一部分在所述导电壁内，所述第二部分从所述导电壁侧向朝外延伸，且所述导电内分区将所述包封物的所述第一部分划分成至少部分地覆盖所述第一半导体裸片的第一区段，及至少部分地覆盖所述第二半导体裸片的第二区段。
8.一种封装半导体装置，其包括：
重布结构，其具有第一侧、第二侧、具有从所述第一侧到所述第二侧的厚度的介电形成物、在所述重布结构的所述第一侧处的裸片触点、在所述重布结构的所述第一侧处的至少一个屏蔽件触点，及在所述重布结构的所述第二侧处的球垫；
半导体裸片，其安装在所述重布结构的所述第一侧上，其中所述半导体裸片包含外周界；
导电屏蔽结构，其具有在所述重布结构的所述第一侧上的导电侧壁及电耦合到所述侧壁的导电盖，其中所述侧壁电耦合到所述屏蔽件触点；
包封物，其具有第一部分及第二部分，所述第一部分具有在所述半导体裸片上面的上部表面，且所述第一部分相对于所述半导体裸片的所述外周界侧向朝外延伸到所述导电屏蔽结构的所述侧壁，所述第二部分从所述导电屏蔽结构的所述侧壁侧向朝外延伸，且所述导电盖附接到所述第一部分的所述上部表面。
9.根据权利要求8所述的装置，其中所述包封物的所述第一部分及所述第二部分材料相同。
10.根据权利要求8所述的装置，其中所述重布结构为多级重布结构，其进一步包括嵌入所述第一侧与所述第二侧之间的所述介电形成物中的屏蔽组件，其中所述屏蔽组件在所述半导体裸片下方且电耦合到所述侧壁及所述导电盖。
11.根据权利要求8所述的装置，其中所述导电盖包括金属板。
12.根据权利要求8所述的装置，其中所述导电盖包括沉积在所述侧壁的顶部表面及所述包封物的所述上部表面上的至少一个金属层。
13.根据权利要求8所述的装置，其进一步包括：
第二半导体裸片，其在与所述第一半导体裸片侧向间隔开的位置处附接到所述重布结构的所述第一侧；及
导电内分区，其形成于所述重布结构的所述第一侧上且电耦合到所述屏蔽件触点，其中所述导电内分区在所述第一半导体裸片与所述第二半导体裸片之间。
14.根据权利要求13所述的装置，其中所述包封物的所述第一部分在所述侧壁内，所述包封物的所述第二部分从所述侧壁侧向朝外延伸，且所述导电内分区将所述包封物的所述第一部分划分成至少部分地覆盖所述第一半导体裸片的第一区段，及至少部分地覆盖所述第二半导体裸片的第二区段。
15.一种封装半导体装置的方法，其包括：
将半导体裸片电耦合到重布结构的第一侧处的裸片触点，其中所述裸片触点电耦合到所述重布结构的第二侧处的球垫；
在所述重布结构的所述第一侧上形成导电壁，其中所述导电壁电耦合到所述重布结构的所述第一侧处的至少一个屏蔽件触点，且其中所述屏蔽件触点电耦合到所述重布结构的所述第二侧处的球垫；
将包封物沉积在所述半导体裸片上面，其中所述包封物具有上部表面；及
将导电盖安置到所述包封物的所述上部表面上，其中所述导电盖电耦合到所述导电壁。
16.根据权利要求15所述的方法，其中：
沉积所述包封物包括用所述包封物覆盖所述半导体裸片的背侧；且
所述方法进一步包括去除所述包封物的一部分及所述导电壁的一部分，以在所述半导体裸片上面形成所述包封物上的所述上部表面及所述导电壁上的顶部表面。
17.根据权利要求16所述的方法，其中去除所述包封物的一部分及所述导电壁的一部分包括磨削所述包封物的上部部分及所述导电壁的上部部分，且其中所述包封物的所述上部表面与所述导电壁的所述顶部表面共面。
18.根据权利要求16所述的方法，其中将所述导电盖安置到所述包封物的所述上部表面上包括将金属板粘附到所述包封物的所述上部表面及所述导电壁的所述顶部表面。
19.根据权利要求16所述的方法，其中将所述导电盖安置到所述包封物的所述上部表面上包括将至少一层导电材料沉积到所述包封物的所述表面上，且直接沉积到所述导电壁的所述顶部表面上。
20.根据权利要求16所述的方法，其中所述重布结构包括多级屏蔽结构，且其中所述方法进一步包括在所述多级屏蔽结构中形成电耦合到所述导电壁及所述导电盖的屏蔽组件。
CN201880033776.XA 2017-07-28 2018-06-27 经屏蔽的扇出型封装半导体装置及制造方法 Pending CN110663113A (zh)

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US20220013421A1 (en) 2022-01-13
US20190035706A1 (en) 2019-01-31
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US11742252B2 (en) 2023-08-29

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