CN102315200A - 一种芯片封装结构、封装方法及电子设备 - Google Patents

一种芯片封装结构、封装方法及电子设备 Download PDF

Info

Publication number
CN102315200A
CN102315200A CN201110258811A CN201110258811A CN102315200A CN 102315200 A CN102315200 A CN 102315200A CN 201110258811 A CN201110258811 A CN 201110258811A CN 201110258811 A CN201110258811 A CN 201110258811A CN 102315200 A CN102315200 A CN 102315200A
Authority
CN
China
Prior art keywords
chip
radome
pad
pcb board
packaging structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201110258811A
Other languages
English (en)
Inventor
赵龙
李春澍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Device Co Ltd
Original Assignee
Huawei Device Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Device Co Ltd filed Critical Huawei Device Co Ltd
Priority to CN201110258811A priority Critical patent/CN102315200A/zh
Publication of CN102315200A publication Critical patent/CN102315200A/zh
Priority to PCT/CN2012/080683 priority patent/WO2013029533A1/zh
Priority to EP14166650.3A priority patent/EP2763169A1/en
Priority to EP12799503.3A priority patent/EP2602819A4/en
Priority to US13/722,270 priority patent/US20130113088A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种芯片封装结构、封装方法及电子设备,涉及芯片封装领域,用以解决芯片封装结构中导电漆形成的屏蔽膜容易脱落的问题。所述芯片封装结构,包括:印刷电路板PCB板;屏蔽罩;所述屏蔽罩固定扣置在所述PCB板的零件面上;待屏蔽芯片;所述待屏蔽芯片设置在所述PCB板的零件面上,位于所述屏蔽罩之内,且所述待屏蔽芯片的管脚与所述PCB板上的第一焊盘相连接;所述待屏蔽芯片与所述屏蔽罩不接触。本发明提供的方案可以应用于芯片的封装。

Description

一种芯片封装结构、封装方法及电子设备
技术领域
本发明涉及芯片封装领域,尤其涉及一种芯片封装结构、封装方法及电子设备。
背景技术
在高密度封装技术中,芯片可能受到来自外界电磁信号的干扰,从而造成芯片的性能下降甚至损坏,并连带造成该芯片所在的设备引发故障。
目前已经出现具有屏蔽功能的芯片封装结构,该芯片封装结构通常采用在塑封后的芯片表面喷涂导电漆的方式,以屏蔽外界电磁信号的干扰。但这种芯片封装结构中由导电漆形成的屏蔽膜容易脱落,从而导致这种芯片封装结构的抗干扰能力降低,也就造成了其屏蔽功能的不理想。
发明内容
本发明的实施例提供一种芯片封装结构、封装方法及电子设备,用以解决芯片封装结构中导电漆形成的屏蔽膜容易脱落的问题。
为解决上述问题,本发明的实施例采用如下技术方案:
一方面,提供一种芯片封装结构,包括:
印刷电路板PCB板;
屏蔽罩;所述屏蔽罩固定扣置在所述PCB板的零件面上;
待屏蔽芯片;所述待屏蔽芯片设置在所述PCB板的零件面上,位于所述屏蔽罩内,且所述待屏蔽芯片的管脚与所述PCB板上的第一焊盘相连接;
所述待屏蔽芯片与所述屏蔽罩不接触。
另一方面,提供一种芯片封装方法,包括:
在印刷电路板PCB板上设计第一焊盘、第二焊盘;
在所述PCB板的零件面上,采用芯片键合工艺将待屏蔽芯片的管脚与所述第一焊盘连接;
在所述PCB板的零件面上设置屏蔽罩,将所述屏蔽罩与所述第二焊盘固定连接,且所述屏蔽罩与所述待屏蔽芯片不接触。
又一方面,提供一种电子设备,包括:上述的芯片封装结构。
本发明实施例提供的一种芯片封装结构、封装方法及电子设备,其中所述芯片封装结构包括:PCB板,固定扣置在PCB板的零件面上的屏蔽罩,以及待屏蔽芯片;其中,待屏蔽芯片设置在PCB板的零件面上,位于屏蔽罩之内,且待屏蔽芯片的管脚与所述PCB板上的第一焊盘相连接,这样就可以将待屏蔽芯片的管脚通过PCB板的第一焊盘导出;同时,待屏蔽芯片与屏蔽罩不接触,这样屏蔽罩就不会干扰待屏蔽芯片工作。与现有技术相比,本发明实施例提供的芯片封装结构中屏蔽罩固定扣置在PCB板上,这种芯片封装结构中的屏蔽罩不易脱落,进而能够提高芯片封装结构的抗干扰能力。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的芯片封装结构的剖面图;
图2为本发明实施例提供的芯片封装结构的俯视图;
图3为本发明实施例提供的一种芯片封装方法流程图;
图4为本发明实施例提供的另一芯片封装方法流程图。
附图标记:
100-芯片封装结构;11-PCB板,12-屏蔽罩,121-导电体,122-金属片,13-待屏蔽芯片,14-绝缘物,15-第二焊盘,16-第一焊盘,17-导线。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供的芯片封装结构100,如图1所示,包括PCB板(Printed Circuit Board,印刷电路板)11,屏蔽罩12,待屏蔽芯片13。其中,屏蔽罩12固定扣置在PCB板11的零件面即图1中A面上,待屏蔽芯片13设置在PCB板11的零件面上,位于所述屏蔽罩12之内,且待屏蔽芯片13的管脚与PCB板11上的第一焊盘16相连接;待屏蔽芯片13与屏蔽罩12不接触。
本实施例中的待屏蔽芯片可以是需要与外界电磁波隔离的裸芯片、已封装芯片、喷涂导电漆的芯片或芯片组等。
所述屏蔽罩可以是任意能够屏蔽外界电磁波的罩体,可以使位于该屏蔽罩内的待屏蔽芯片与外界电磁波隔离;同时,该屏蔽罩固定扣置在PCB板的零件面上,且固定的方式可以是任意将屏蔽罩固定在PCB板上的方式,这样就使得芯片封装结构中的屏蔽罩不易脱落,进而可以提高芯片封装结构抗干扰能力。
特别地,所述第一焊盘一方面可以固定连接待屏蔽芯片的管脚,另一方面还可以将PCB板零件面的待屏蔽芯片的管脚引至非零件面。
进一步地,屏蔽罩12包括:金属片122,以及接触并支撑金属片122的导电体121。此时,所述屏蔽罩12固定扣置在所述PCB板11的零件面上具体可以为:屏蔽罩12的导电体121焊接在PCB板11的零件面上的第二焊盘15上。在本实施例中,屏蔽罩的金属片不仅起到防止待屏蔽芯片受外界电磁干扰的作用,还起到良好的散热作用;与现有技术相比,不需要依靠PCB板散热,从而可以避免对PCB板上的其他电路产生影响。
需要说明的是,焊盘形状可以有多种,可以是有圆形、方形、椭圆形、矩形、八边形等,其具体形状由其所承载的元件形状决定。在本实施例中,第一焊盘的形状由管脚形状决定,第二焊盘的形状由导电体形状决定。
优选的,所述导电体121为表面裸露的导电体,具体可以为金属线或焊球。进一步优选的,所述导电体接地;导电体接地的方式可以是将导电体连接至待屏蔽芯片的接地管脚,也可以由第二焊盘将导电体引出接地,当然不排除其他方式将导电体接地,以使得屏蔽罩可以更好的屏蔽外界电磁信号的干扰。
进一步的,屏蔽罩12和设置有待屏蔽芯片13的PCB板11之间填充有绝缘物14。优选的,绝缘物可以为塑胶。该绝缘物不仅可以使得屏蔽罩和待屏蔽芯片之间不接触,从而使得屏蔽罩不会干扰待屏蔽芯片工作;另外,该绝缘物还可以起到屏蔽罩与PCB板之间的支撑作用,以使得芯片封装结构更加牢固。
进一步的,所述待屏蔽芯片13的管脚与所述PCB板11上的第一焊盘16相连接包括:所述待屏蔽芯片13的管脚与导线17的一端相焊接,且导线17的另一端与所述PCB板11上的第一焊盘16相焊接。这种连接方式是采用传统的芯片键合工艺,其中,所述导线可以使用传统工艺中使用的金线或铝线。当然,待屏蔽芯片的管脚与第一焊盘连接方式不限于通过导线连接,示例的,也可以根据待屏蔽芯片的管脚位置设置好相应的第一焊盘位置,将待屏蔽芯片的管脚直接焊接在第一焊盘上。
更进一步的,若所述芯片封装结构还需要封装,则上述芯片封装结构还包括:封装外壳;所述封装外壳上设置有与所述待屏蔽芯片的管脚对应的第三焊盘;所述第三焊盘与第一焊盘连接,以便将与该第三焊盘对应的待屏蔽芯片的管脚引出。需要说明的是该设置有第三焊盘的封装外壳在图示中并未标示,但本领域技术人员可以根据现有的封装工艺理解本发明所描述的芯片封装结构。
图2为本发明实施例提供的芯片封装结构的俯视图,通过图2可以进一步看清本发明实施例提供的芯片封装结构100的各个部分的位置关系,需要说明的是图2中未标识金属片、金属片与PCB板之间的绝缘物等。参考图2所示,并结合上述对芯片封装结构的描述,可以清楚了解待屏蔽芯片13位于PCB板11上,在PCB板的四周设置有导电体121,待屏蔽芯片13的管脚与导线17的一端相焊接,导线17的另一端与PCB板11上的第一焊盘16相焊接。
本发明实施例还提供了芯片封装方法,如图3所示,并结合图1,该封装方法具体包括以下步骤:
S301、在印刷电路板PCB板11上设计第一焊盘16、第二焊盘15;
S302、在PCB板11的零件面上,采用芯片键合工艺将待屏蔽芯片13的管脚与第一焊盘16连接;
S303、在PCB板11的零件面上设置屏蔽罩12,将屏蔽罩12与第二焊盘15固定连接,且屏蔽罩12与待屏蔽芯片13不接触。
本发明实施例提供的芯片封装方法,通过在PCB板上固定扣置在PCB板的零件面上的屏蔽罩,使得位于屏蔽罩之内的待屏蔽芯片可以免受外界电磁波的干扰;并且由于屏蔽罩固定扣置在PCB板上,使得这种芯片封装结构中的屏蔽罩不易脱落;同时,待屏蔽芯片与屏蔽罩不接触,这样屏蔽罩就不会干扰待屏蔽芯片工作。
进一步的,S303具体可以包括:
首先,在所述PCB板11的零件面上的第二焊盘15焊接导电体121;
然后,在所述PCB板11的零件面上注塑,并且塑胶平面高于待屏蔽芯片13、低于导电体121;
最后,在塑胶未完全固化之前,将金属板置于所述PCB板11的导电体121之上,并压合使得金属板122紧贴塑胶,且与导电体良好接触;塑胶固化后,金属板与塑胶粘合。
由于上述的注塑过程中,塑胶呈液态,其自身处于一定温度,在该温度下导电体会在一定程度软化;在塑胶未完全固化之前,将金属板压合在导电体之上就可以使得两者良好接触,另外,由于塑胶未完全固化,将金属板压合至紧贴塑胶,就可以使得塑胶固化后,金属板与塑胶粘合;这就能够保证金属板不会轻易剥落,也保证了制作完成的芯片封装结构的牢固性。
更进一步的,如果芯片封装结构还需要封装,则本发明提供的芯片封装结构的制作方法,如图4所示,还可以包括:
S304、通过封装工艺将设置有屏蔽罩的芯片封装结构封装在封装外壳中,由封装外壳上的第三焊盘将待屏蔽芯片的管脚引出。
具体的,可以利用导线将第一焊盘与第三焊盘连接,从而将所述待屏蔽芯片的管脚引出,完成封装。
该封装工艺可以参考现有技术中的封装工艺,例如BGA(英文全称为Ball Grid Array,球栅阵列结构)封装、QFN(Quad Flat No-leadPackage,方形扁平无引脚封装)等封装工艺。由于封装工艺是本领域技术人员所了解的,故在此就不再赘述。
需要说明的是,图3或图4所示的芯片封装方法可以作为参考应用于实际芯片封装结构的制造过程中,但封装方法的顺序不限于图3或图4所示的顺序。
另外,本发明实施例还提供了一种电子设备,包括:上述任一芯片封装结构。该电子设备可以是移动终端,当然也可以使用芯片的任何一种电子设备。
下面,以手机为例进行详述。
手机硬件主要包括:显示屏、上盖(前盖)、下盖(后盖)、电池盖、扬声器麦克风和主板等,其中主板又包括射频芯片、基带芯片、电源管理芯片、Flash存储芯片(闪速存储芯片),这些主板上的芯片的引脚与手机的天线、显示屏、扬声器麦克风等外围设备连接,就实现了手机的基本功能。
所述射频芯片、基带芯片、电源管理芯片、Flash存储芯片中的任一个或多个(两个以上)都可以采用本发明实施例提供的芯片封装构造,以使得该手机中需要封装的芯片不易受外界电磁波影响,抗干扰能力强。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

1.一种芯片封装结构,其特征在于,包括:
印刷电路板PCB板;
屏蔽罩;所述屏蔽罩固定扣置在所述PCB板的零件面上;
待屏蔽芯片;所述待屏蔽芯片设置在所述PCB板的零件面上,位于所述屏蔽罩内,且所述待屏蔽芯片的管脚与所述PCB板上的第一焊盘相连接;
所述待屏蔽芯片与所述屏蔽罩不接触。
2.根据权利要求1所述的芯片封装结构,其特征在于,所述屏蔽罩包括:金属片,以及接触并支撑该金属片的导电体;
所述屏蔽罩固定扣置在所述PCB板的零件面上包括:
所述屏蔽罩的导电体焊接在所述PCB板的零件面上的第二焊盘上。
3.根据权利要求2所述的芯片封装结构,其特征在于,所述导电体为金属线或焊球。
4.根据权利要求2所述的芯片封装结构,其特征在于,所述导电体接地。
5.根据权利要求1-4任一项权利要求所述的芯片封装结构,其特征在于,所述待屏蔽芯片的管脚与所述PCB板上的第一焊盘相连接包括:
所述待屏蔽芯片的管脚与导线的一端相焊接,且导线的另一端与所述PCB板上的第一焊盘相焊接。
6.根据权利要求1~5任一项权利要求所述的芯片封装结构,其特征在于,所述待屏蔽芯片与所述屏蔽罩不接触包括:
所述屏蔽罩和设置有待屏蔽芯片的PCB板之间填充有绝缘物。
7.根据权利要求6所述的芯片封装结构,其特征在于,所述绝缘物为塑胶。
8.根据权利要求1~7任一项权利要求所述的芯片封装结构,其特征在于,还包括:封装外壳;所述封装外壳上设置有与所述待屏蔽芯片的管脚对应的第三焊盘;
所述第三焊盘与第一焊盘连接,以便将与该第三焊盘对应的待屏蔽芯片的管脚引出。
9.一种芯片封装方法,其特征在于,包括:
在印刷电路板PCB板上设计第一焊盘、第二焊盘;
在所述PCB板的零件面上,采用芯片键合工艺将待屏蔽芯片的管脚与所述第一焊盘连接;
在所述PCB板的零件面上设置屏蔽罩,将所述屏蔽罩与所述第二焊盘固定连接,且所述屏蔽罩与所述待屏蔽芯片不接触。
10.根据权利要求9所述的芯片封装方法,其特征在于,所述在所述PCB板的零件面上设置屏蔽罩,将屏蔽罩与所述第二焊盘固定连接,且所述屏蔽罩与所述待屏蔽芯片不接触包括:
在所述PCB板的零件面上的第二焊盘焊接导电体;
在所述PCB板的零件面上注塑,并且塑胶平面高于待屏蔽芯片、低于导电体;
在塑胶未完全固化之前,将金属板置于所述PCB板的导电体之上,并压合使得金属板紧贴塑胶,且与导电体良好接触;塑胶固化后,金属板与塑胶粘合。
11.根据权利要求9或10所述的芯片封装方法,其特征在于,还包括:
通过封装工艺将设置有屏蔽罩的芯片封装在封装外壳中,由封装外壳上的第三焊盘将待屏蔽芯片的管脚引出。
12.一种电子设备,其特征在于,包括:权利要求1~8任一项所述的芯片封装结构。
CN201110258811A 2011-09-02 2011-09-02 一种芯片封装结构、封装方法及电子设备 Pending CN102315200A (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201110258811A CN102315200A (zh) 2011-09-02 2011-09-02 一种芯片封装结构、封装方法及电子设备
PCT/CN2012/080683 WO2013029533A1 (zh) 2011-09-02 2012-08-29 一种芯片封装结构、封装方法及电子设备
EP14166650.3A EP2763169A1 (en) 2011-09-02 2012-08-29 Chip packaging structure and method for electromagnetic shielding
EP12799503.3A EP2602819A4 (en) 2011-09-02 2012-08-29 CHIP PACKING STRUCTURE AND PACKAGING METHOD AND ELECTRONIC DEVICE
US13/722,270 US20130113088A1 (en) 2011-09-02 2012-12-20 Chip packaging structure, chip packaging method, and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110258811A CN102315200A (zh) 2011-09-02 2011-09-02 一种芯片封装结构、封装方法及电子设备

Publications (1)

Publication Number Publication Date
CN102315200A true CN102315200A (zh) 2012-01-11

Family

ID=45428209

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110258811A Pending CN102315200A (zh) 2011-09-02 2011-09-02 一种芯片封装结构、封装方法及电子设备

Country Status (4)

Country Link
US (1) US20130113088A1 (zh)
EP (2) EP2602819A4 (zh)
CN (1) CN102315200A (zh)
WO (1) WO2013029533A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104218034A (zh) * 2013-06-04 2014-12-17 三星电机株式会社 半导体封装
CN107481997A (zh) * 2017-09-05 2017-12-15 中国电子科技集团公司第二十九研究所 一种双层堆叠气密封装结构及方法
CN105792504B (zh) * 2016-03-01 2018-09-28 中国电子科技集团公司第五十四研究所 一种具有屏蔽措施的pcb空穴埋置装置及制备工艺
CN110663113A (zh) * 2017-07-28 2020-01-07 美光科技公司 经屏蔽的扇出型封装半导体装置及制造方法
CN110978751A (zh) * 2019-12-27 2020-04-10 青岛歌尔微电子研究院有限公司 一种刷锡膏模具及锡膏印刷工艺
CN114498198A (zh) * 2022-02-28 2022-05-13 苏州浪潮智能科技有限公司 一种信号引脚集装置
CN114664673A (zh) * 2022-05-25 2022-06-24 武汉敏声新技术有限公司 一种射频模组封装结构及方法
CN116963385A (zh) * 2023-09-21 2023-10-27 荣耀终端有限公司 电路板组件和终端设备

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9192057B2 (en) 2012-12-26 2015-11-17 Apple Inc. Electromagnetic interference shielding structures
US10224290B2 (en) * 2015-12-24 2019-03-05 Intel Corporation Electromagnetically shielded electronic devices and related systems and methods
CN107768323B (zh) * 2017-11-24 2023-12-05 安徽芯动联科微系统股份有限公司 抗高过载电子器件封装管壳
CN112768421B (zh) * 2020-12-14 2022-06-10 苏州浪潮智能科技有限公司 一种芯片装置、pcb板及电子设备
CN117289411A (zh) * 2023-10-09 2023-12-26 四川泰瑞创通讯技术股份有限公司 优化emi屏蔽性能的光电转换器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101322245A (zh) * 2006-09-15 2008-12-10 香港应用科技研究院有限公司 具有emi屏蔽的电子元件封装
JP2010205869A (ja) * 2009-03-03 2010-09-16 Sae Magnetics (Hk) Ltd 電子回路モジュールの製造方法
CN102150260A (zh) * 2008-09-10 2011-08-10 瑞萨电子株式会社 半导体器件及其制造方法
JP2011171436A (ja) * 2010-02-17 2011-09-01 Tdk Corp 電子部品内蔵モジュール及び電子部品内蔵モジュールの製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535719B2 (en) * 1999-08-04 2009-05-19 Super Talent Electronics, Inc. Single chip USB packages with contact-pins cover
JP2001244508A (ja) * 2000-02-25 2001-09-07 Bunkyo So 表面実装ledのパッケージおよびその製造方法
DE10127009A1 (de) * 2001-06-05 2002-12-12 Infineon Technologies Ag Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform
US20020190353A1 (en) * 2001-06-19 2002-12-19 Jyh-Sheng Pan Plastic package structure for communication component
JP3632960B2 (ja) * 2001-11-27 2005-03-30 京セラ株式会社 半導体装置
JP2003249607A (ja) * 2002-02-26 2003-09-05 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
TW200411871A (en) * 2002-12-30 2004-07-01 Advanced Semiconductor Eng Thermal-enhance package and manufacturing method thereof
WO2004077560A1 (ja) * 2003-02-26 2004-09-10 Ibiden Co., Ltd. 多層プリント配線板
DE10350239A1 (de) * 2003-10-27 2005-06-16 Infineon Technologies Ag Halbleiterbauteil mit Gehäusekunststoffmasse, Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung desselben
CN101401206B (zh) * 2006-03-29 2011-04-13 京瓷株式会社 电路组件和无线通信设备、以及电路组件的制造方法
CN101150123B (zh) * 2007-10-31 2010-06-02 日月光半导体制造股份有限公司 具有电磁屏蔽罩盖的半导体封装结构
US20090315156A1 (en) * 2008-06-20 2009-12-24 Harper Peter R Packaged integrated circuit having conformal electromagnetic shields and methods to form the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101322245A (zh) * 2006-09-15 2008-12-10 香港应用科技研究院有限公司 具有emi屏蔽的电子元件封装
CN102150260A (zh) * 2008-09-10 2011-08-10 瑞萨电子株式会社 半导体器件及其制造方法
JP2010205869A (ja) * 2009-03-03 2010-09-16 Sae Magnetics (Hk) Ltd 電子回路モジュールの製造方法
JP2011171436A (ja) * 2010-02-17 2011-09-01 Tdk Corp 電子部品内蔵モジュール及び電子部品内蔵モジュールの製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104218034A (zh) * 2013-06-04 2014-12-17 三星电机株式会社 半导体封装
CN105792504B (zh) * 2016-03-01 2018-09-28 中国电子科技集团公司第五十四研究所 一种具有屏蔽措施的pcb空穴埋置装置及制备工艺
CN110663113A (zh) * 2017-07-28 2020-01-07 美光科技公司 经屏蔽的扇出型封装半导体装置及制造方法
US11158554B2 (en) 2017-07-28 2021-10-26 Micron Technology, Inc. Shielded fan-out packaged semiconductor device and method of manufacturing
US11742252B2 (en) 2017-07-28 2023-08-29 Micron Technology, Inc. Shielded fan-out packaged semiconductor device and method of manufacturing
CN107481997A (zh) * 2017-09-05 2017-12-15 中国电子科技集团公司第二十九研究所 一种双层堆叠气密封装结构及方法
CN110978751A (zh) * 2019-12-27 2020-04-10 青岛歌尔微电子研究院有限公司 一种刷锡膏模具及锡膏印刷工艺
CN114498198A (zh) * 2022-02-28 2022-05-13 苏州浪潮智能科技有限公司 一种信号引脚集装置
CN114498198B (zh) * 2022-02-28 2023-07-25 苏州浪潮智能科技有限公司 一种信号引脚集装置
CN114664673A (zh) * 2022-05-25 2022-06-24 武汉敏声新技术有限公司 一种射频模组封装结构及方法
CN116963385A (zh) * 2023-09-21 2023-10-27 荣耀终端有限公司 电路板组件和终端设备
CN116963385B (zh) * 2023-09-21 2023-11-24 荣耀终端有限公司 电路板组件和终端设备

Also Published As

Publication number Publication date
EP2602819A1 (en) 2013-06-12
EP2602819A4 (en) 2013-06-26
WO2013029533A1 (zh) 2013-03-07
US20130113088A1 (en) 2013-05-09
EP2763169A1 (en) 2014-08-06

Similar Documents

Publication Publication Date Title
CN102315200A (zh) 一种芯片封装结构、封装方法及电子设备
US7928538B2 (en) Package-level electromagnetic interference shielding
US9001528B2 (en) Shielded electronic components and method of manufacturing the same
US20110019370A1 (en) Flexible circuit module
CN104067389A (zh) 包括电磁吸收和屏蔽的半导体装置
CN102237342A (zh) 一种无线通讯模块产品
TWI594390B (zh) 半導體封裝件及其製法
CN102215448B (zh) 可屏蔽电磁干扰的硅麦克风封装方法、封装体及电子装置
CN101800215A (zh) 无线通讯模组封装构造
CN100511614C (zh) 多芯片堆叠的封装方法及其封装结构
US20110159643A1 (en) Fabrication method of semiconductor package structure
US11239179B2 (en) Semiconductor package and fabrication method thereof
US20130015544A1 (en) Semiconductor package and method of manufacturing the same
CN103617991A (zh) 半导体封装电磁屏蔽结构及制作方法
CN103579201B (zh) 采用导电封装材料的半导体器件电磁屏蔽结构及制作方法
CN101971486A (zh) 半导体器件和具备该半导体器件的通信设备以及电子设备
CN113035826B (zh) 封装模组、封装模组的制作方法及电子设备
CN101286500B (zh) 半导体模块及便携设备
TW201318143A (zh) 積體電路裝置及裝配積體電路裝置的方法
CN110113926B (zh) 一种屏蔽结构及终端
KR20080074468A (ko) 초음파를 이용한 반도체 칩의 표면실장방법
CN102111955B (zh) Pcb板连接结构及连接方法
TWI509873B (zh) 具有天線的封裝結構及其製作方法
US20190297758A1 (en) Electromagnetic shielding cap, an electrical system and a method for forming an electromagnetic shielding cap
CN215644968U (zh) 一种毫米波天线模组及通信设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20120111