CN104067389A - 包括电磁吸收和屏蔽的半导体装置 - Google Patents

包括电磁吸收和屏蔽的半导体装置 Download PDF

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Publication number
CN104067389A
CN104067389A CN201280053715.2A CN201280053715A CN104067389A CN 104067389 A CN104067389 A CN 104067389A CN 201280053715 A CN201280053715 A CN 201280053715A CN 104067389 A CN104067389 A CN 104067389A
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China
Prior art keywords
absorbing material
layer
substrate
moulding compound
rfi
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CN201280053715.2A
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CN104067389B (zh
Inventor
黄大成
白晔
钱开友
邱进添
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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Abstract

公开了一种半导体装置，该半导体装置包括用于吸收EMI和/或RFI的材料。该装置包括：衬底(202)；一个或更多个半导体裸芯(224、225)；以及围绕所述一个或更多个半导体裸芯(224、225)的模塑料。用于吸收EMI和/或RFI的所述材料可设置在所述衬底(202)上的阻焊膜层(210)内或上。该装置还包括围绕所述模塑料并且与衬底上的EMI/RFI吸收材料相接触的EMI/RFI吸收材料，以将所述一个或更多个半导体裸芯(224、225)完全包覆在EMI/RFI吸收材料中。

Description

包括电磁吸收和屏蔽的半导体装置
技术领域
本发明的实施例涉及半导体装置。
背景技术
对便携式消费电子产品需求的迅猛增长推进了对高容量存储装置的需求。如闪存卡的非易失性半导体存储装置开始被广泛地使用以满足对数字信息存储和交换的日益增长的需求。这类存储装置的便携性、多功能性和朴实耐用的设计，连同其高可靠性和大容量，已使得他们可理想地用于多种多样的电子设备，包括例如数码相机、数字音乐播放器、视频游戏控制器、PDA和移动电话。
虽然已知多种多样的封装结构，但闪存卡通常可被制为系统级封装(SiP)或多芯片模块(MCM)，其中多个裸芯以堆叠式结构安装在衬底上。现有技术的图1和图2中示出了常规半导体封装20(无模塑料)的边视图。典型的封装包括安装至衬底26的多个半导体裸芯22、24。尽管未在图1和图2中示出，该半导体裸芯可在裸芯的上表面上形成有裸芯焊盘。衬底26可形成有夹在上导电层和下导电层之间的电绝缘核。该上和/或下导电层可被刻蚀以形成包括电导线和接触垫(contact pad)的电导图案。焊线30被焊接在半导体裸芯22、24的裸芯焊盘和衬底26的接触垫之间，以将半导体裸芯电连接至衬底。衬底上的该电导线因此提供裸芯和主设备之间的电通路。一旦裸芯和衬底之间形成电连接，该组件就典型地被包裹在模塑料中以提供保护性封装。
已知的是使用偏移式结构(现有技术的图1)或堆叠式结构(现有技术的图2)将半导体裸芯互相叠放起来。在图1的偏移式结构中，各裸芯有偏移地堆叠，以使得下方的下一个裸芯的焊盘露出。该偏移需要衬底上的较大覆盖区，而衬底上的空间非常宝贵。在图2的堆叠式结构中，两个或更多个半导体裸芯以一个直接位于另一个之上的方式堆叠，从而相较于偏移式结构，占据衬底上的覆盖区较小。然而，在堆叠式结构中，必须在相邻的半导体裸芯之间提供用于焊线30的空间。除了焊线30本身的高度之外，还必须在焊线上方留出额外的空间，因为一个裸芯的焊线30与上方的下一个裸芯的焊线如接触可能导致电短路。如图2所示，因此已知的是提供电介质隔离层34来为焊线30提供足够的空间以将焊线30焊接至下方裸芯24上的裸芯焊盘。
因为电子组件变得更小且工作频率更高，由电磁干扰(EMI)和射频干扰(RFI)造成的噪音和串扰变得更令人担忧。EMI是电磁辐射的感应现象，电磁辐射是由携载快速变化的信号的电路发射的，作为其对其它电路的正常操作的伴生物，电磁辐射产生不期望的信号(干扰或噪声)。RFI是射频电磁辐射从一个电路到另一个电路的传输，其也造成了不期望的干扰或噪声。
一些半导体封装已尝试在半导体封装级屏蔽EMI和RFI辐射的传输和接收。虽然防止了干扰，但这些常规方案存在其它缺陷，这些缺陷使得在不期望的封装级包含这类特征。由此，通常在使用半导体封装的主设备级进行屏蔽。主设备级方案典型地涉及提供围绕接收或安装半导体封装的空间的金属屏蔽。代替屏蔽，还已知的是吸收EMI和RFI。然而，常规的吸收式方案还未能令人满意地解决半导体封装中的EMI和/或RFI问题。
附图说明
图1和图2是现有技术中两种常规半导体封装设计的边视图，其中省略了模塑料。
图3是示出了根据本公开的半导体装置的装配的流程图。
图4是根据本公开的实施方式的衬底的俯视图。
图5是根据本公开的实施方式的衬底的边视图。
图6是根据本公开的实施方式的衬底的俯视图。
图7是根据本公开的实施方式的包括具有EMI/RFI吸收体的阻焊膜的衬底的边视图。
图8是根据本公开的替换性实施方式的包括设置在阻焊膜层上的EMI/RFI吸收层的衬底的边视图。
图9是根据本公开的实施方式的包括EMI/RFI吸收阻焊膜层的衬底的俯视图。
图10是根据本公开的实施方式的包括半导体裸芯和接地管脚的衬底的边视图。
图11是根据本公开的实施方式的包括半导体裸芯和接地管脚的衬底的俯视图。
图12是在第一包封工艺过程中被包封的、包括半导体裸芯和接地管脚的衬底的边视图。
图13是在第一包封工艺过程中被包封的、包括半导体裸芯和接地管脚的衬底的俯视图。
图14是根据本公开的半导体装置在施加了EMI/RFI吸收和屏蔽层之后的边视图。
图15是根据本公开的半导体装置在施加了EMI/RFI吸收和屏蔽层之后的俯视图。
图16是根据本公开的半导体装置在第二包封工艺之后的边视图。
图17是根据本公开的半导体装置在第二包封工艺之后的俯视图。
图18是根据本公开的包括用于附着至主设备印刷电路板的焊球的半导体装置的边视图。
具体实施方式
下面将参照图3到图18描述各实施方式，其涉及包括电磁干扰(EMI)和射频干扰(RFI)的屏蔽和吸收的半导体封装。应理解，本发明能够以不同的形式实施并且不应被视为限于在本文中列举的实施方式。提供这些实施方式是为了使本公开更加透彻和完整，并且能够充分地向本领域技术人员传达本发明。事实上，本发明旨在覆盖这些实施方式的替换、修改和等同方案，并且这些方案都包含在由随附权利要求书所限定的本发明的范围和精神内。此外，在下面关于本发明的具体描述中，为了提供对本发明的透彻理解，示出了许多特定细节，但是，本领域技术人员应该清楚，本发明可无需这些具体细节而实施。
本文可能使用的术语“顶(顶部)”、“底(底部)”、“上(上部)”、“下(下部)”仅用于便利和例示的目的，并不意味着限制本发明的描述，因为参照对象的位置可能发生变化。
现在将参照图3的流程图以及图4至图18的俯视图和边视图来解释本技术的实施方式。图4是包括多个衬底202的衬底面板201的俯视图。面板201允许同时批量地将衬底202加工成多个半导体装置200以实现规模经济。所示出的衬底面板201上的衬底202的行和列数仅为示例性的，在其它实施方式中衬底202的行和/或列数可发生变化。
在图5和图6的边视图和俯视图中示出了单个衬底202的示例。该衬底202可为各种不同的芯片载体介质，包括印刷电路板(PCB)、引线框或卷带式自动接合(TAB)带。如果衬底202是PCB，该衬底可由各种导电层204形成，每层由电介质核203分隔。为了简明起见，图7、8、10、12、14、16和18的边视图示出了由一对导电层环绕的单核203，但这些附图中的衬底202可与图5中的衬底202相同。图5中所示的衬底中的层数仅为示例性的，其它实施方式中可能有更多或更少的层。
核203可由各种电介质材料形成，诸如，例如聚酰亚胺叠层、包括FR4和FR5的环氧树脂、双马来酰亚胺三嗪(bismaleimide triazine(BT))等。尽管对于本发明而言不很严格，但该核可具有介于40μm至200μm之间的厚度，在替换性实施方式中该核的厚度可在该范围之外变化。在替换性实施方式中，该核可为陶瓷或有机物。如下方将解释的，可额外添加EMI/RFI吸收体或者包含EMI/RFI吸收体作为核203的一部分。
环绕该核203的导电层204可由铜或铜合金、镀过的铜或镀过的铜合金、镀了铜的钢或其它金属以及已知的用在衬底面板上的材料形成。该导电层可具有约10μm-25μm的厚度，但在替换性实施方式中该导电层的厚度可在该范围之外变化。如下将解释的，其中一个导电层，例如层204a，可被用作接地平面。
在步骤100中，衬底202被钻孔以在衬底202中限定通孔205。提供通孔205(其中一些在附图中被标号)以在衬底202的不同层之间交流信号。所示出的通孔205的数量和位置仅为示例性的，该衬底可包括比附图中示出的多得多的通孔205，并且这些通孔的位置可不同于附图中所示出的。如下将解释的，通孔205包括用于将衬底的顶表面上的接地管脚耦合至接地平面204a以及衬底的底表面上的接地垫上的一个或更多个通孔205a。
接下来可在步骤104中在设置在一个(多个)核203上的一个或更多个导电层204中形成电导图案。顶部和底部导电层204中的电导图案可通过各种方法形成，包括例如丝网印刷法和光刻法。图6的顶层中示出了电导图案的一个示例。应理解，其余的导电层中的一个或更多个导电层也可具有限定在其内的电导图案。
衬底202的层204中的一个(多个)电导图案可包括电迹线206和接触垫208(其中一些在附图中标记出)。所示出的电迹线206和接触垫208是示例性的，衬底202可包括比附图中示出的更多的电迹线和/或接触垫，并且它们可以以不同于附图中所示的方式布置。可在电导图案中设置其它结构，例如用于测试半导体装置200的运行的测试管脚。在衬底202的不同导电层204中的电导图案可通过各种已知工艺形成，包括例如各种丝网印刷工艺或光刻工艺。
仍然参照图1，接下来可在步骤108中在自动光学检查系统(AOI)中检查衬底202。一旦检查后，可在步骤112中将阻焊膜层210施加于衬底202的上和/或下表面。该阻焊膜层可具有多种功能。在一个示例中，该(一个或多个)阻焊膜层由聚合物形成，该聚合物为电导图案的铜迹线提供保护性涂层并防止焊料流出到暴露的焊盘和测试管脚之外，从而防止短路。
此外，根据本技术的实施方式，可将EMI/RFI吸收体212添加到阻焊膜材料中以用于吸收半导体装置200内辐射的以及从外部源辐射到半导体装置200上的EMI和RFI。在某些实施方式中，在将阻焊膜层210施加到衬底202上之前，在步骤110中将该EMI/RFI吸收体212形成为阻焊膜的一部分。然而，如下将参照图8解释的，可在将阻焊膜210施加于衬底202之后，将该EMI/RFI吸收体212作为分隔层设置到阻焊膜上。
将该EMI/RFI吸收体212添加到阻焊膜上，以通过将EMI/RFI转换为热能而削弱它。在一个示例中，该EMI/RFI吸收体212可包括磁性颗粒，比如铁氧体。然而，在其它实施方式中，该吸收体212可为多种多样的其它材料和成分，包括例如碳化硅、碳纳米管、二氧化镁、羰基铁粉末、铁硅铝粉末(SENDUST：一种包含85％的铁、9.5％的硅和5.5％的铝的合金)、硅化铁、磁性合金、磁性薄片和粉末、其它金属以及这些材料的组合。该吸收体212还可包含或可不包含导热材料，比如例如氮化铝、氮化硼、铁、金属氧化物及其组合。由于吸收体212形成为施加于电导图案之上的阻焊膜的一部分，在某些实施方式中，该吸收体212是电绝缘体。
在某些实施方式中，EMI/FRI吸收体212可与用于阻焊膜210中的其它材料混合在一起。在这类实施方式中，吸收体212可占阻焊膜的体积的20％-40％。在常规阻焊膜中的提供的一种成分是硫酸钡。在某些实施方式中，吸收体212可部分地或全部替换阻焊膜中的硫酸钡。如果EMI/RFI吸收体212是铁氧体，该吸收体可包含长度达约30μm的铁氧体条，但在其它实施方式中，该铁氧体条可能更长。这些条可彼此对齐(通常彼此平行)，或它们可相对于彼此随机取向。
在其它实施方式中，在将阻焊膜施加于衬底之前，EMI/RFI吸收体212可作为分隔层施加于阻焊膜210(以使得阻焊膜与吸收体的组合被一起施加于衬底)。在这类实施方式中，在施加阻焊膜层210之前，吸收体212可悬浮在比如环氧树脂或硅树脂的弹性体中，然后被施加于阻焊膜材料。
如果该阻焊膜是包含吸收体212的液体，该阻焊膜可被印刷到衬底上。如果该阻焊膜是干膜(包括被并入阻焊膜中的吸收体或包括作为分隔层被施加于阻焊膜的吸收体)，该阻焊膜可被层压到衬底上。
在某些实施方式中，吸收体212有效地吸收约100MHz-10GHz的频率范围内的EMI/RFI，其例如为在半导体装置200内辐射的频率。应理解，吸收体212可被用于吸收位于该范围之上或之下的频率的EMI/RFI。改变吸收体中使用的颗粒的类型、尺寸、密度以及阻焊膜层210的厚度，将改变由吸收体212吸收的效率和频率范围。
在某些实施方式中，该阻焊膜层210可在10μm和40μm之间，但其可比其它实施方式中的厚度更厚或更薄。如果阻焊膜层210既施加于衬底202的上表面又施加于衬底202的下表面，该EMI/RFI吸收体212可设置在上阻焊膜层210中、下阻焊膜层210中或这两者中。
如上所指示的，代替阻焊膜层210或除阻焊膜层210之外，EMI/RFI吸收体212可施加在衬底的其它位置中。例如，图8示出了一个示例，其中EMI/RFI吸收体212的层214可施加于衬底的上和/或下表面上的阻焊膜层210之上。在这类实施方式中，吸收体212可作为液体层214通过如印刷而被施加于衬底202。可替换地，吸收体212可悬浮在层214中的诸如环氧树脂或硅树脂的弹性体中，然后在施加该阻焊膜层210之后被层压到阻焊膜材料上。
在其它实施方式中，不同于被并入阻焊膜层210内和/或阻焊膜层210上或除阻焊膜层210之外，该EMI/RFI吸收体可被并入衬底202的核203内。在一个这样的示例中，该EMI/RFI吸收体212可占核203的体积的50％-70％，虽然在核203内的该吸收体可比在其它实施方式中的更多或更少。
在阻焊膜层形成后，在步骤114中，顶层和底层上的电导图案的露出部分(包括例如接触垫208)可以以已知的电镀、非电镀或薄膜沉积工艺镀有Ni/Au层等。
在步骤116中，可在自动检查工艺(AVI)中检查和测试衬底202，并且在步骤120中，该衬底可经受最终视觉检查(FVI)以核查电气操作以及污染物、划痕和变色情况。
假设该衬底202通过了检查，接下来可在步骤122中将一个或更多个半导体裸芯固定到衬底202的顶表面上，如图10和11的边视图和俯视图所示。然后可在步骤126中将该一个或更多个半导体裸芯引线健合到衬底202上。在例示的示例中，半导体装置200包括一对存储器裸芯224和一个控制器裸芯225。该存储器裸芯224可例如为闪存芯片(NOR/NAND)，但也可设想其它类型的存储器裸芯。应理解，可提供单个存储器裸芯224，也可提供两个以上的存储器裸芯。控制器裸芯225可例如为ASIC。
焊线226可连接在裸芯224、225上的裸芯焊盘230和衬底202上的接触垫208之间。仅示出并标示了其中一些裸芯焊盘230和焊线226。虽然在附图中裸芯焊盘230被示出为沿着裸芯224、225的单侧，但应理解，该裸芯焊盘230和焊线226可从裸芯224、225的多侧出发而到与衬底202的多个边缘相邻的接触垫208。
尽管未示出，还可将一个或更多个无源元件固定并电耦合至衬底202。该一个或更多个无源元件可被安装在衬底202上并电耦合至电导图案，例如通过以已知的表面安装方式和回流焊接工艺连接至接触垫。无源元件可包括例如一个或更多个电容器、电阻器和/或电感器，但也可设想其它元件。
在安装半导体裸芯224、225和/或形成焊线226之前或之后，还可在步骤124中将接地管脚228固定至衬底。该接地管脚可例如被焊接到衬底202的顶表面上的接触垫上，并通过比如例如通孔205a的通孔连接至接地平面204a。该接地管脚可由电导体形成，比如例如铝，并且可为从衬底向上延伸的管脚的形状。在其它实施方式中，该接地管脚228可由从衬底202的表面向上延伸的柔性弹簧或夹子替代。如下将解释的，该接地管脚228与成品的半导体装置200中的EMI/RFI屏蔽的接触，从而将该屏蔽接地。
在步骤128中，该半导体装置200可经受等离子清洗工艺以移除微粒并改进表面的可湿润性，从而允许用于保护半导体裸芯和焊线的模塑料的更好的流动特性。
在已将裸芯224安装并引线健合至衬底以及将接地管脚228固定后，可在第一包封步骤(步骤130)中将裸芯224、225、焊线226和部分接地管脚228包封到模塑料240中，如图12和13中的边视图和俯视图所示。在某些实施方式中，该模塑料240可使用已知例如来自日本的Nitto Denko Corp.(日本日东电工)的环氧树脂、由转移模塑法形成。
在其它实施方式中，代替转移模塑法，该模塑料240包封可由自由流动薄(FFT)压制成型工艺形成。这种FFT压制成型工艺是已知的并且在例如日本京都Towa Corporation的Matsutani,H.在2009年Microelectronics andPackaging Conference(微电子与封装会议)中发表的名称为“CompressionMolding Solutions For Various High End Package And Cost Savings ForStandard Package Applications的出版物中有描述，该出版物以引用方式整体并入本文。一般来说，FFT压制机使用的是将衬底的面板浸没在包含熔融树脂的模具中的技术。
无论包封工艺的类型如何，留下接地夹228的顶部穿过模塑料而伸出。该模塑料240可覆盖所有半导体裸芯224、225和整个衬底202。可替换地，该模塑料240可以施加为不同的结构，以便留下衬底202的位于屏蔽环外围内的部分不被模塑料包覆。
现在参照步骤134以及附图14和15的边视图和俯视图，在第一包封工艺之后，可将一层或更多层覆盖材料244沉积到模塑料240上。在某些实施方式中，该覆盖材料244包括两个分开的层。第一层244a可为EMI/RFI吸收体，诸如根据如上所述的吸收体212的任何实施方式。
该第一层244a可施加于模塑料的所有表面之上，并且向下与阻焊膜层210接触，由此完全将半导体裸芯224、225和半导体装置200内的其它元件包覆在EMI/RFI吸收体212内。在其它实施方式中，吸收层224a可仅施加于模塑料240的顶表面，而不施加于模塑料的向下延伸至衬底202的侧面上。该层244a可被印刷或层压到模塑料240上。在某些实施方式中，该第一层224a可具有在模塑料上的几微米至几百微米的厚度。该厚度可比在其它实施方式中的更大或更小。
第二材料层224可为EMI/RFI屏蔽层244b。如果吸收层244a吸收EMI/RFI并将其转化为热能，该屏蔽层244b可反射EMI/RFI。该屏蔽层244b可为电导体，诸如例如铜。该屏蔽层244b可仅由镀到吸收层244a上的铜组成，或可为铜上的镀镍膜(nickel-flash)。可使用其它导电镀层材料。对于镀层，首先可在非电镀工艺中将镍或铜镀为籽晶层。该非电镀的镍或非电镀的铜镀层提供种子层，如PCB行业已知的。该种子层镀层用作电极，以允许随后的铜或其它金属的更快的电镀。第二层244b可具有几纳米至几百微米的厚度，部分取决于沉积工艺。在其它实施方式中，该层244b可比这更薄或更厚。
设计该接地管脚228的尺寸从而使其位于屏蔽层244b内。由此，该屏蔽层244b接至衬底202的接地平面204a。
由于具有层244a，该屏蔽层244b可被镀到吸收层244a和/或模塑料240的所有表面上。可替换地，该屏蔽层244b可被设置在模塑料240的顶表面上(与吸收层244a一起)，并且不被设置在模塑料240的向下延伸至衬底202的侧面上。
层244a、224b可都仅设置在模塑料240的顶部上，或可都向下延伸至衬底。可替换地，吸收层244a可设置在模塑料240的顶部和向下延伸至衬底的侧面上，但屏蔽层244b可仅设置在顶表面上且不设置在侧面上。作为另一个替换方案，屏蔽层244b可设置在模塑料240的顶部和向下延伸至衬底的侧面上，但吸收层244a可仅设置在顶表面上且不设置在侧面上。在所示出的实施方式中，吸收层244a被设置在模塑料240上，并且屏蔽层244b被设置在吸收层244a上。在替换性实施方式中，层244a、244b的位置可互换以使得屏蔽层244b被设置在模塑料240上而吸收层244a被设置在屏蔽层244b上。
衬底202中/上的吸收材料212与材料244的层244a、244b一起减少了半导体装置200的EMI和/或RFI。在一个示例中，吸收材料212和材料244可将100MHz-10GHz范围内的频率的干扰减少15dB。应理解，在其它实施方式中，可减少的该频率范围内的干扰可更多或更少。
现在参照图16和17的边视图和俯视图，在覆盖步骤之后，可在步骤136中执行第二包封工艺。这一步骤可施加模塑料248以完全包覆半导体装置200上的覆盖材料244。该模塑料248可为与模塑料240相同的任何材料，并且可以通过与用于施加模塑料240相同的任何工艺施加。在其它实施方式中，模塑料248不必与模塑料240相同，包括例如FFT压制模塑。虽然步骤136中的第二包封工艺是有利的，但其在其它实施方式中可省略，使覆盖材料244成为装置200的外表面。
在步骤140中，可将焊球252施加于半导体装置200的底表面上的接触垫218，如图18的边视图所示。该焊球允许装置200被表面安装至主设备中的PCB(未示出)。接触垫218包括接地垫218a，其每一个可接收一个焊球252a。接地管脚228可通过通孔205a、接地垫218a和焊球252a连接至PCB上的接地位置。
在其它实施方式中，包括焊球252a的焊球252可省略。例如，半导体装置200可为平面网格阵列(LGA)封装，其可被可移动地插入主设备的操作位置。在这类封装中，装置200的底表面上的接触垫218可为接触指。这些接触指中的一个或更多个可为接地指，其被设计与主设备中的接地连接件匹配。在该实施方式中，接地管脚228可以电耦合至这类接地指。
在施加了该焊球之后，或，在省略了焊球的情况下在该第二包封步骤之后，可在步骤144中将半导体装置200从面板201中分割出从而形成加工完的半导体装置200。可通过各种切割方法中的任意一种来分割每个装置200，包括锯切、水射流切割、激光切割、水导激光切割、干介质切割和金刚石涂层线切割。虽然直线切口将限定大致矩形或方形形状的装置200，但应理解，在本发明的其它实施方式中，装置200可具有除矩形和方形之外的形状。
一旦切割出多个装置200，可在步骤148中对各装置进行测试以确定封装体是否正常工作。如本领域已知的，这类测试可包括电测试、老化测试以及其它测试。在步骤150中，各装置可以可选地被包封在盖子(lid)内。
总的来说，在一个实施方式中，本技术涉及一种半导体装置，包括：衬底，该衬底包括电介质核、电介质核上的导电层和导电层上的阻焊膜层；该衬底包括用于吸收EMI和RFI中的至少之一的吸收材料；以及固定至该衬底的一个或更多个半导体裸芯。
在另一个实施方式中，本技术涉及一种半导体装置，包括：衬底；该衬底上的阻焊膜层，该阻焊膜层包括用于吸收EMI和RFI中的至少之一的第一吸收材料；固定并电连接至该衬底的一个或更多个半导体裸芯；包封至少该一个或更多个半导体裸芯的模塑料；以及设置在该模塑料上的层，该层包括用于吸收EMI和RFI中的至少之一的第二吸收材料。
在又一个实施方式中，本技术涉及一种半导体装置，包括：衬底；该衬底上的阻焊膜层，该阻焊膜层包括用于吸收EMI和RFI中的至少之一的第一吸收材料；固定并电连接至该衬底的一个或更多个半导体裸芯；包封至少该一个或更多个半导体裸芯的模塑料；以及设置在该模塑料上的第一层和第二层，该第一层包括用于吸收EMI和RFI中的至少之一的第二吸收材料，并且该第二层包括用于为半导体装置屏蔽EMI和RFI中的至少之一的导电材料。
在再一个实施方式中，本技术涉及一种为半导体装置屏蔽EMI和RFI中的至少之一的方法，包括步骤：(a)将一个或更多个半导体裸芯安装在衬底上；(b)将该衬底上的该一个或更多个半导体裸芯包封在模塑料中；以及(c)将该一个或更多个半导体裸芯完全包封在吸收材料的一层或多层中，该吸收材料吸收EMI和RFI中的至少之一。
本发明的前述详细说明是出于例示和说明的目的而进行的。无意于穷举或将本发明限制于在此公开的精确形式。基于上述教导，可能存在许多修改和变形。所描述的实施方式是为了更好地解释本发明的原理及其实际应用从而使本领域其它技术人员能够最好地以各种实施方式利用本发明而选择的，并且可根据具体使用而设想出适用的各种修改。本发明的范围由随附于此的权利要求书限定。

Claims (30)

1.一种半导体装置，包括：
衬底，该衬底包括：电介质核，所述电介质核上的导电层，以及所述导电层上的阻焊膜层，所述衬底包括吸收材料，所述吸收材料用于吸收电磁干扰(EMI)和射频干扰(RFI)中的至少之一；以及
固定至所述衬底的一个或更多个半导体裸芯。
2.如权利要求1所述的半导体装置，其中所述吸收材料被设置为所述阻焊膜的一部分。
3.如权利要求2所述的半导体装置，其中所述吸收材料作为所述阻焊膜的一部分而被混合在所述阻焊膜中。
4.如权利要求2所述的半导体装置，其中在所述阻焊膜被施加于所述衬底之前，所述吸收材料以层形式被设置在所述阻焊膜上。
5.如权利要求1所述的半导体装置，其中在所述阻焊膜被施加于所述衬底之后，所述吸收材料以层的形式被设置在所述阻焊膜上。
6.如权利要求1所述的半导体装置，其中所述吸收材料被设置为所述电介质核的一部分。
7.一种半导体装置，包括：
衬底；
所述衬底上的阻焊膜层，所述阻焊膜层包括第一吸收材料，所述第一吸收材料用于吸收电磁干扰(EMI)和射频干扰(RFI)中的至少之一；
固定并电连接至所述衬底的一个或更多个半导体裸芯；
包封至少所述一个或更多个半导体裸芯的模塑料；以及
设置在所述模塑料上的层，所述层包括第二吸收材料，所述第二吸收材料用于吸收EMI和RFI中的至少之一。
8.如权利要求7所述的半导体装置，其中所述第一吸收材料和第二吸收材料具有相同的成分。
9.如权利要求7所述的半导体装置，其中所述第二吸收材料设置在所述模塑料的顶表面上以及所述模塑料的向下延伸并与所述衬底上的所述阻焊膜层相接触的侧面上，所述第一吸收材料和第二吸收材料完全包覆所述一个或更多个半导体裸芯。
10.如权利要求7所述的半导体装置，其中所述第二吸收材料设置在所述模塑料的顶表面上，并且不设置在所述模塑料的延伸至与所述阻焊膜层相接触的侧面上。
11.如权利要求7所述的半导体装置，还包括围绕所述模塑料上的所述层的第二模塑料。
12.如权利要求7所述的半导体装置，其中所述第一吸收材料和第二吸收材料中的至少之一是铁氧体。
13.如权利要求7所述的半导体装置，其中所述第一吸收材料和第二吸收材料中的至少之一是碳化硅、碳纳米管、二氧化镁、羰基铁粉末、铝硅铁粉、硅化铁、磁性合金和磁性薄片及粉末中的一种。
14.如权利要求7所述的半导体装置，其中所述第一吸收材料作为所述阻焊膜的一部分被混合在所述阻焊膜中。
15.如权利要求7所述的半导体装置，其中在所述阻焊膜被施加于所述衬底之前，所述第一吸收材料以层的形式被设置所述阻焊膜上。
16.一种半导体装置，包括：
衬底；
所述衬底上的阻焊膜层，所述阻焊膜层包括第一吸收材料，所述第一吸收材料用于吸收电磁干扰(EMI)和射频干扰(RFI)中的至少之一；
固定并电连接至所述衬底的一个或更多个半导体裸芯；
包封至少所述一个或更多个半导体裸芯的模塑料；以及
设置在所述模塑料上的第一层和第二层，所述第一层包括第二吸收材料，所述第二吸收材料用于吸收EMI和RFI中的至少之一，并且所述第二层包括导电材料，所述导电材料用于为所述半导体装置屏蔽EMI和RFI中的至少之一。
17.如权利要求16所述的半导体装置，还包括接地管脚，所述接地管脚连接至所述衬底中的接地平面并连接至所述第二层。
18.如权利要求16所述的半导体装置，其中所述第一吸收材料和第二吸收材料具有相同的成分。
19.如权利要求16所述的半导体装置，其中所述第二吸收材料的第一层设置在所述模塑料的顶表面上以及所述模塑料的向下延伸并与所述衬底上的阻焊膜层相接触的侧面上，所述第一吸收材料和第二吸收材料完全包覆所述一个或更多个半导体裸芯。
20.如权利要求16所述的半导体装置，其中所述第二吸收材料的第一层设置在所述模塑料的顶表面上，并且不设置在所述模塑料的延伸至与所述阻焊膜层相接触的侧面上。
21.如权利要求16所述的半导体装置，其中所述第二吸收材料的第一层设置在所述模塑料上，并且所述导电材料的第二层设置在吸收材料的第一层上。
22.如权利要求16所述的半导体装置，其中所述导电材料的第二层设置在所述模塑料上，并且所述第二吸收材料的第一层设置在导电材料的所述第二层上。
23.一种为半导体装置屏蔽电磁干扰(EMI)和射频干扰(RFI)中的至少之一的方法，包括步骤：
(a)将一个或更多个半导体裸芯安装在衬底上；
(b)将所述衬底上的所述一个或更多个半导体裸芯包封在模塑料中；以及
(c)将所述一个或更多个半导体裸芯完全包封在吸收材料的一层或多层中，所述吸收材料吸收EMI和RFI中的至少之一。
24.如权利要求23所述的方法，其中所述步骤(c)包括：在所述衬底上提供用于吸收EMI和RFI中的至少之一的吸收材料的层。
25.如权利要求23所述的方法，其中所述步骤(c)包括：在设置在所述衬底上的阻焊膜层中提供用于吸收EMI和RFI中的至少之一的吸收材料的层。
26.如权利要求23所述的方法，其中所述步骤(c)包括：在所述模塑料上提供用于吸收EMI和RFI中的至少之一的吸收材料的层。
27.如权利要求23所述的方法，还包括步骤(d)：在所述模塑料上提供电导屏蔽层，用于为所述半导体装置屏蔽EMI和RFI中的至少之一。
28.如权利要求27所述的方法，还包括步骤(e)：将所述电导屏蔽层接地至所述衬底。
29.如权利要求28所述的方法，其中所述步骤(e)包括步骤：用安装在所述衬底上并且延伸至与所述电导屏蔽层相接触的接地管脚，将所述电导屏蔽层接地至所述衬底。
30.如权利要求23所述的方法，其中所述步骤(c)还包括步骤：将吸收材料的层施加于所述模塑料之上；所述方法还包括步骤(f)：在所述步骤(b)和(c)之后执行第二包封步骤，以围绕吸收材料的所述层施加模塑料。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107207950A (zh) * 2015-02-06 2017-09-26 莱尔德技术股份有限公司 具有碳化硅的导热电磁干扰(emi)吸收剂
CN107236337A (zh) * 2017-08-02 2017-10-10 合肥东恒锐电子科技有限公司 一种电子产品用耐高温防辐射涂料
CN108289369A (zh) * 2017-01-09 2018-07-17 莱尔德技术股份有限公司 具有介电间隔件的吸收器组件以及相应的组装方法
CN109559640A (zh) * 2018-12-05 2019-04-02 京东方科技集团股份有限公司 一种显示模组及其制作方法和显示装置

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11599003B2 (en) 2011-09-30 2023-03-07 View, Inc. Fabrication of electrochromic devices
US9007674B2 (en) 2011-09-30 2015-04-14 View, Inc. Defect-mitigation layers in electrochromic devices
US11732527B2 (en) 2009-12-22 2023-08-22 View, Inc. Wirelessly powered and powering electrochromic windows
US11630366B2 (en) 2009-12-22 2023-04-18 View, Inc. Window antennas for emitting radio frequency signals
US11342791B2 (en) 2009-12-22 2022-05-24 View, Inc. Wirelessly powered and powering electrochromic windows
US11205926B2 (en) 2009-12-22 2021-12-21 View, Inc. Window antennas for emitting radio frequency signals
US20130271813A1 (en) 2012-04-17 2013-10-17 View, Inc. Controller for optically-switchable windows
US10802371B2 (en) 2011-12-12 2020-10-13 View, Inc. Thin-film devices and fabrication
US11300848B2 (en) 2015-10-06 2022-04-12 View, Inc. Controllers for optically-switchable devices
US8952503B2 (en) * 2013-01-29 2015-02-10 International Business Machines Corporation Organic module EMI shielding structures and methods
KR102143653B1 (ko) * 2013-12-31 2020-08-11 에스케이하이닉스 주식회사 전자기 간섭 차폐부를 갖는 반도체 패키지 및 제조방법
EP3114640B1 (en) 2014-03-05 2022-11-02 View, Inc. Monitoring sites containing switchable optical devices and controllers
US11114742B2 (en) 2014-11-25 2021-09-07 View, Inc. Window antennas
CN107112620B (zh) 2014-11-25 2019-12-31 唯景公司 窗天线
WO2016126449A1 (en) * 2015-02-06 2016-08-11 Laird Technologies, Inc. Thermally-conductive electromagnetic interference (emi) absorbers with silicon carbide
US9461001B1 (en) * 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
US9859728B2 (en) 2015-09-01 2018-01-02 Dell Products, Lp System for securing a wireless power pad
US10110042B2 (en) 2015-09-01 2018-10-23 Dell Products, Lp Cart for wirelessly recharging mobile computing devices
US9954388B2 (en) 2015-09-01 2018-04-24 Dell Products, Lp Cover system for wireless power pad
US9876382B2 (en) 2015-09-01 2018-01-23 Dell Products, Lp Peak power caching in a wireless power system
US10148115B2 (en) 2015-09-01 2018-12-04 Dell Products, Lp Wireless charging pad with natural draft cooling and method therefor
US9973027B2 (en) 2015-09-01 2018-05-15 Dell Products, Lp Wireless power charging device with rear side magneto isolation marking
US9912187B2 (en) * 2015-09-01 2018-03-06 Dell Products, Lp Wireless power transmission antenna with thermally conductive magnetic shield and method therefor
US9954387B2 (en) 2015-09-01 2018-04-24 Dell Products, Lp Wireless charging pad with interdependent temperature control and method therefor
US9887555B2 (en) 2015-09-01 2018-02-06 Dell Products, Lp Articulating receiver for wireless power delivery system
US9905359B2 (en) 2015-09-01 2018-02-27 Dell Products, Lp Wireless power antenna winding including heat pipe and method therefor
GB2542345B (en) * 2015-09-14 2020-03-04 Jaguar Land Rover Ltd Vehicle communication apparatus and method
KR20170067426A (ko) * 2015-12-08 2017-06-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
WO2017171813A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Electromagnetic interference shielding for semiconductor packages using bond wires
EP3500891A4 (en) 2016-08-22 2020-03-25 View, Inc. ELECTROCHROME WINDOW WITH ELECTROMAGNETIC SHIELD
JP6672113B2 (ja) * 2016-09-09 2020-03-25 Ｔｏｗａ株式会社 電子回路装置及び電子回路装置の製造方法
US9836095B1 (en) * 2016-09-30 2017-12-05 Intel Corporation Microelectronic device package electromagnetic shield
DE102018000961A1 (de) * 2017-02-20 2018-08-23 Sew-Eurodrive Gmbh & Co Kg Elektronische Anordnung mit Leistungsmodul, Leiterplatte und Kühlkörper
US10388611B2 (en) * 2017-03-13 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming magnetic field shielding with ferromagnetic material
US10476307B2 (en) 2017-03-13 2019-11-12 Dell Products, Lp Wireless power system with foreign object detection and method therefor
US10523037B2 (en) 2017-03-13 2019-12-31 Dell Products, Lp Thermal management at a wireless power system
US10361590B2 (en) 2017-03-13 2019-07-23 Dell Products, Lp Wireless power system with device specific power configuration and method therefor
EP3419050A1 (en) * 2017-06-23 2018-12-26 ams International AG Radiation-hardened package for an electronic device and method of producing a radiation-hardened package
WO2019144342A1 (en) * 2018-01-25 2019-08-01 Shenzhen Xpectvision Technology Co., Ltd. Packaging of radiation detectors
CN113039052B (zh) 2018-11-16 2023-09-05 惠普发展公司，有限责任合伙企业 引线框架装配件及引线框架的两步模制成型方法
TW202206925A (zh) 2020-03-26 2022-02-16 美商視野公司 多用戶端網路中之存取及傳訊
US11631493B2 (en) 2020-05-27 2023-04-18 View Operating Corporation Systems and methods for managing building wellness
KR20220000538A (ko) * 2020-06-26 2022-01-04 삼성전자주식회사 반도체 모듈
US11495534B2 (en) * 2021-04-12 2022-11-08 Nanya Technology Corporation Semiconductor device with test pad and method for fabricating the same
CN117256203A (zh) * 2022-02-03 2023-12-19 微软技术许可有限责任公司 用于印刷电路板的印刷去耦平面

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1639866A (zh) * 2001-12-14 2005-07-13 莱尔德技术公司 包括有损耗的介质的电磁干扰屏蔽件
US20070045818A1 (en) * 2005-08-25 2007-03-01 Kuan Lee C Land grid array semiconductor device packages, assemblies including same, and methods of fabrication
CN1926682A (zh) * 2004-03-04 2007-03-07 斯盖沃克斯瑟路申斯公司 具有集成emi和rfi屏蔽的包覆成型半导体封装
US20080157294A1 (en) * 2006-12-28 2008-07-03 Xiang Yin Zeng Package level noise isolation
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors
CN101471329A (zh) * 2007-12-29 2009-07-01 清华大学 半导体封装件
CN101742814A (zh) * 2009-12-22 2010-06-16 深圳华为通信技术有限公司 一种印刷电路板屏蔽方法及印刷电路板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789064A (en) 1992-02-28 1998-08-04 Valente; Thomas J. Electromagnetic radiation absorbing and shielding compositions
US6707168B1 (en) 2001-05-04 2004-03-16 Amkor Technology, Inc. Shielded semiconductor package with single-sided substrate and method for making the same
EP1547222B1 (en) * 2002-06-10 2018-10-03 City University of Hong Kong Planar inductive battery charger
WO2005081609A1 (ja) 2004-02-24 2005-09-01 Shin-Etsu Polymer Co., Ltd. 電磁波ノイズ抑制体、電磁波ノイズ抑制機能付構造体、およびそれらの製造方法
US20050206015A1 (en) 2004-03-16 2005-09-22 Texas Instruments Incorporated System and method for attenuating electromagnetic interference
JP2006203086A (ja) 2005-01-24 2006-08-03 Citizen Electronics Co Ltd 電子部品パッケージ及びその製造方法
US7589284B2 (en) * 2005-09-12 2009-09-15 Parker Hannifin Corporation Composite polymeric material for EMI shielding
US8053279B2 (en) * 2007-06-19 2011-11-08 Micron Technology, Inc. Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
US9318403B2 (en) 2007-06-25 2016-04-19 Stats Chippac Ltd. Integrated circuit packaging system with magnetic film and method of manufacture thereof
US8780600B2 (en) * 2011-12-07 2014-07-15 Apple Inc. Systems and methods for stacked semiconductor memory devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1639866A (zh) * 2001-12-14 2005-07-13 莱尔德技术公司 包括有损耗的介质的电磁干扰屏蔽件
CN1926682A (zh) * 2004-03-04 2007-03-07 斯盖沃克斯瑟路申斯公司 具有集成emi和rfi屏蔽的包覆成型半导体封装
US20070045818A1 (en) * 2005-08-25 2007-03-01 Kuan Lee C Land grid array semiconductor device packages, assemblies including same, and methods of fabrication
US20080157294A1 (en) * 2006-12-28 2008-07-03 Xiang Yin Zeng Package level noise isolation
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors
CN101471329A (zh) * 2007-12-29 2009-07-01 清华大学 半导体封装件
CN101742814A (zh) * 2009-12-22 2010-06-16 深圳华为通信技术有限公司 一种印刷电路板屏蔽方法及印刷电路板

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107207950A (zh) * 2015-02-06 2017-09-26 莱尔德技术股份有限公司 具有碳化硅的导热电磁干扰(emi)吸收剂
CN107207950B (zh) * 2015-02-06 2021-05-14 莱尔德电子材料（上海）有限公司 具有碳化硅的导热电磁干扰(emi)吸收剂
CN108289369A (zh) * 2017-01-09 2018-07-17 莱尔德技术股份有限公司 具有介电间隔件的吸收器组件以及相应的组装方法
CN107236337A (zh) * 2017-08-02 2017-10-10 合肥东恒锐电子科技有限公司 一种电子产品用耐高温防辐射涂料
CN109559640A (zh) * 2018-12-05 2019-04-02 京东方科技集团股份有限公司 一种显示模组及其制作方法和显示装置

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