TWI654731B - 包括電磁吸收及屏蔽之半導體元件 - Google Patents

包括電磁吸收及屏蔽之半導體元件

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Publication number
TWI654731B
TWI654731B TW102105624A TW102105624A TWI654731B TW I654731 B TWI654731 B TW I654731B TW 102105624 A TW102105624 A TW 102105624A TW 102105624 A TW102105624 A TW 102105624A TW I654731 B TWI654731 B TW I654731B
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TW
Taiwan
Prior art keywords
layer
substrate
emi
rfi
molding compound
Prior art date
Application number
TW102105624A
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English (en)
Other versions
TW201344874A (zh
Inventor
黃大成
白曄
錢開友
邱進添
Original Assignee
晟碟半導體（上海）有限公司
晟碟信息技術（上海）有限公司
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Publication of TW201344874A publication Critical patent/TW201344874A/zh
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Publication of TWI654731B publication Critical patent/TWI654731B/zh

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Abstract

本發明揭示一種半導體元件，其包含用於吸收電磁干擾(EMI)及/或射頻干擾(RFI)之材料。該元件包含一基板、一或多個半導體晶粒及圍繞該一或多個半導體晶粒之模製化合物。用於吸收EMI及/或RFI之該材料可設置於該基板上之一焊料遮罩層內或該焊料遮罩層上，或設置於該基板之一介電核心內。該元件可進一步包含圍繞該模製化合物且與該基板上之該EMI/RFI吸收材料接觸以將該一或多個半導體晶粒完全圍封於EMI/RFI吸收材料中之EMI/RFI吸收材料。

Description

包括電磁吸收及屏蔽之半導體元件
本發明之實施例係關於半導體元件。
可攜式消費電子器件之強勁需求增長推動高容量儲存元件之需求。非揮發性半導體記憶體元件(諸如快閃記憶體儲存卡)變為廣泛用於滿足數位資訊儲存及交換之不斷增長需求。該等非揮發性半導體記憶體元件之可攜性、多功能性及堅固設計以及其高可靠性及大容量已使此等記憶體元件理想地用在各種電子元件(其例如包含數位相機、數位音樂播放器、視訊遊戲機、PDA及蜂巢式電話)中。
雖然吾人已知各種封裝組態，但快閃記憶體儲存卡一般可製造為系統級封裝(SiP)或多晶片模組(MCM)，其中複數個晶粒在一基板上安裝成呈一堆疊組態。先前技術之圖1及圖2中展示一習知半導體封裝20(不具有模製化合物)之一側視圖。典型封裝包含安裝於一基板26上之複數個半導體晶粒22、24。雖然圖1及圖2中未展示，但半導體晶粒形成有該晶粒之一上表面上之晶粒接合墊。基板26可由夾於上導電層與下導電層之間之一電絕緣核心形成。上導電層及/或下導電層可經蝕刻以形成包含電引線及接觸墊之導電圖案。接線30焊接於半導體晶粒22、24之晶粒接合墊與基板26之接觸墊之間以將半導體晶粒電連接至基板。基板上之電引線繼而在晶粒與一主機元件之間提供一電路 徑。在形成晶粒與基板之間之電連接之後，通常將總成封閉於一模製化合物中以提供一保護封裝。
吾人已知將半導體晶粒分層堆疊於彼此之頂上以具有一偏移(先前技術圖1)或呈一堆疊組態(先前技術圖2)。在圖1之偏移組態中，晶粒堆疊成具有一偏移，使得緊鄰下晶粒之接合墊被曝露。偏移需要基板上之一更大佔用面積，但空間非常珍貴。在圖2之堆疊組態中，兩個或兩個以上半導體晶粒直接堆疊於彼此之頂上，藉此佔用比一偏移組態小之基板上之佔用面積。然而，在一堆疊組態中，相鄰半導體晶粒之間必須提供空間用於接線30。除接線30自身之高度以外，接線上方亦必須留有額外空間，此係因為一晶粒之接線30與上方緊鄰晶粒之接觸會導致一電短路。因此，如圖2中所展示，吾人已知提供一介電間隔層34以給待接合至下晶粒24上之晶粒接合墊之接線30提供足夠空間。
隨著電子組件變得更小且以更高頻率操作，由電磁干擾(EMI)及射頻干擾(RFI)導致之雜訊及串音變得更受關注。EMI為電磁輻射之感應(由攜帶快速變化信號之電路將該感應(作為電路正常操作之一副產物)發射至其他電路)，其導致無用信號(干擾或雜訊)。RFI為自一電路至另一電路之射頻電磁輻射之傳輸，其亦導致無用干擾或雜訊。
一些半導體封裝已試圖屏蔽半導體封裝階層處之EMI及RFI輻射之傳輸及接收。雖然可防止干擾，但此等習知解決方案具有包含處於非所要封裝階層之此等特徵之其他缺點。因此，通常在其中使用一半導體封裝之主機元件階層處執行屏蔽。主機元件階層解決方案通常涉及圍繞其中接收或安裝一半導體封裝之空間而提供一金屬屏蔽。吾人亦已知吸收EMI及RFI以取代屏蔽。然而，習知吸收解決方案無法圓滿地解決一半導體封裝中之EMI及RFI。
20‧‧‧半導體封裝
22‧‧‧半導體晶粒
24‧‧‧半導體晶粒
26‧‧‧基板
30‧‧‧接線
34‧‧‧介電間隔層
200‧‧‧半導體元件
201‧‧‧基板面板
202‧‧‧基板
203‧‧‧介電核心
204‧‧‧導電層
204a‧‧‧接地平面
205‧‧‧介層孔
205a‧‧‧介層孔
206‧‧‧電跡線
208‧‧‧接觸墊
210‧‧‧焊料遮罩層/焊料遮罩
214‧‧‧液體層
218‧‧‧接觸墊
218a‧‧‧接地墊
224‧‧‧記憶體晶粒/半導體晶粒
225‧‧‧控制器晶粒/半導體晶粒
226‧‧‧接線
228‧‧‧接地接針/接地夾
230‧‧‧晶粒接合墊
240‧‧‧模製化合物
244‧‧‧覆蓋材料
244a‧‧‧吸收層/第一層
244b‧‧‧屏蔽層/第二層
248‧‧‧模製化合物
252‧‧‧焊料球
252a‧‧‧焊料球
圖1及圖2係其中省略模製化合物之兩個習知半導體封裝設計之先前技術側視圖。
圖3係展示根據本發明之一半導體元件之組裝之一流程圖。
圖4係根據本發明之一實施例之一基板之一俯視圖。
圖5係根據本發明之一實施例之一基板之一側視圖。
圖6係根據本發明之一實施例之一基板之一俯視圖。
圖7係根據本發明之一實施例之包含具有一EMI/RFI吸收體之一焊料遮罩之一基板之一側視圖。
圖8係根據本發明之一替代實施例之包含設置於焊料遮罩層上之EMI/RFI吸收層之一基板之一側視圖。
圖9係根據本發明之一實施例之包含EMI/RFI吸收焊料遮罩層之一基板之一俯視圖。
圖10係根據本發明之一實施例之包含半導體晶粒及一接地接針之一基板之一側視圖。
圖11係根據本發明之一實施例之包含半導體晶粒及一接地接針之一基板之一俯視圖。
圖12係包含在一第一囊封程序期間所囊封之半導體晶粒及一接地接針之一基板之一側視圖。
圖13係包含在一第一囊封程序期間所囊封之半導體晶粒及一接地接針之一基板之一俯視圖。
圖14係在施加EMI/RFI吸收及屏蔽層之後之根據本發明之一半導體元件之一側視圖。
圖15係在施加EMI/RFI吸收及屏蔽層之後之根據本發明之一半導體元件之一俯視圖。
圖16係在一第二囊封程序之後之根據本發明之一半導體元件之一側視圖。
圖17係在一第二囊封程序之後之根據本發明之一半導體元件之一俯視圖。
圖18係包含用於附接至一主機元件印刷電路板之一焊料球之根據本發明之一半導體元件之一側視圖。
現將參考圖3至圖18而描述實施例，其係關於一種包含EMI及RFI屏蔽及吸收之半導體封裝。應瞭解，本發明可體現為諸多不同形式且不應被解譯為受限於本文中所闡釋之實施例。相反，提供此等實施例，使得本發明透徹完全且將對熟習技術者完全傳達本發明。其實，本發明意欲涵蓋此等實施例之替代物、修改方案及等效物，其等包含於如由隨附申請專利範圍所界定之本發明之範疇及精神內。此外，在本發明之下列詳細描述中，闡釋諸多特定細節以提供本發明之一透徹理解。然而，一般技術者應明白，可在無此等特定細節之情況下實踐本發明。
如本文中所使用，術語「頂部」與「底部」及「上」與「下」僅用於方便及繪示目的且不意謂限制本發明之描述，此係因為參考項可交換至適當位置。
現將參考圖3之流程圖及圖4至圖18之俯視圖及側視圖而解釋本發明之一實施例。圖4係包含複數個基板202之一基板面板201之一俯視圖。面板201容許將基板202同時成批處理成諸多半導體元件200以達成規模經濟。僅以舉例方式展示基板面板201上之基板202之列數及行數，且在另外實施例中基板202之列數及/或行數可變動。
圖5及圖6之側視圖及俯視圖中展示一個別基板202之一實例。基板202可為各種不同晶片載體介質，其包含一印刷電路板(PCB)、一引線框或一捲帶式自動接合(TAB)捲帶。當基板202為一PCB時，基板可由各種導電層204形成，導電層204各由一介電核心203分離。為簡單期間，圖7、圖8、圖10、圖12、圖14、圖16及圖18之側視圖展示由一對導電層包圍之一單一核心203，但該等圖中之基板202可相同於圖5中之基板202。圖5中所展示之基板202中之層之數目僅為實例，且在另外實施例中可具有更多或更少層。
核心203可由各種介電材料，諸如(例如)聚醯亞胺層壓材料、環氧樹脂(其包含FR4及FR5)、雙馬來醯亞胺三嗪(BT)及類似物。雖然對本發明而言並非關鍵，但核心可具有40微米(μm)至200微米之間之一厚度，且在替代實施例中核心之厚度可在該範圍外變動。在替代實施例中，核心可為陶瓷或有機物。如下文所解釋，可添加一EMI/RFI吸收體或否則包含一EMI/RFI吸收體作為核心203之部分。
包圍核心203之導電層204可由銅或銅合金、鍍銅或鍍銅合金、銅鍍鋼或用在基板面板上之其他已知金屬及材料。導電層可具有約10微米至25微米之一厚度，但在替代實施例中導電層之厚度可在該範圍外變動。如下文所解釋，導電層之一者(例如層204a)可用作為一接地平面。
在步驟100中，在基板202上鑽孔以在基板202中界定直通介層孔205。提供介層孔205(其等之部分在圖中被標記元件符號)以在基板202之不同層之間傳送信號。所展示介層孔205之數目及位置作為實例，且基板可包含比圖中所展示數目多之介層孔205，且其等可位於與圖中所展示位置不同之位置中。如下文所解釋，介層孔205包含一或多個介層孔205a，其用於將基板之一頂面上之一接地接針耦合至接地平面204a及基板之一底面上之一接地墊。
接著，在步驟104中，可在設置於(若干)核心203上之導電層204之一或多者中形成導電圖案。可藉由各種方法(其例如包含藉由絲網印刷及藉由光微影)而形成頂部及底部導電層204中之導電圖案。圖6中展示頂層中之一導電圖案之一實例。應瞭解，剩餘導電層之一或多 者亦可具有界定於其內之導電圖案。
基板202之層204中之(若干)導電圖案可包含電跡線206及接觸墊208(其等之部分在圖中被標記元件符號)。所展示之跡線206及接觸墊208作為實例，且基板202可包含比圖中所展示跡線及/或接觸墊多之跡線及/或接觸墊，且其等可呈與圖中所展示配置不同之配置。其他結構可設置於導電圖案中，諸如(例如)用於測試半導體元件200之操作之測試接針。可藉由各種已知程序(其例如包含各種絲網印刷或光微影程序)而形成基板202之各種導電層204中之導電圖案。
再次參考圖3，接著，在步驟108中，可在一自動光學檢測(AOI)中檢測基板202。在被檢測之後，可在步驟112中將一焊料遮罩層210施加至基板202之上表面及/或下表面。焊料遮罩層可提供多項功能。在一實例中，(若干)焊料遮罩層由聚合物形成，該聚合物給導電圖案之銅跡線提供一保護塗層且防止焊料流出溢過曝露接觸墊及測試接針，藉此防止短路。
另外，根據本發明之實施例，可將一EMI/RFI吸收體212添加至焊料遮罩材料以吸收在半導體元件200內輻射及自外部源輻射至半導體元件200上之EMI及RFI。在實施例中，在將(若干)焊料遮罩層210施加至基板202上之前，在步驟110中形成EMI/RFI吸收體212(圖7及9)作為焊料遮罩之部分。然而，如下文相對於圖8所解釋，在將焊料遮罩210施加至基板202之後，可提供EMI/RFI吸收體212作為(若干)焊料遮罩層210上之一分離層。
將EMI/RFI吸收體212添加至焊料遮罩以藉由將EMI/RFI改變成熱能而減弱EMI/RFI。在一實例中，EMI/RFI吸收體212可包括磁性顆粒，諸如肥粒鐵。然而，在另外實施例中，吸收體212可為各種其他材料及組合物，其例如包含碳化矽、碳奈米管、二氧化鎂、羰基鐵粉、鋁矽鐵粉(SENDUST)(含85%鐵、9.5%矽及5.5%鋁之一合金)、矽 化鐵、磁性合金、磁性薄片及粉末、其他材料及此等材料之組合。吸收體212可包含或亦可不包含一導熱材料，諸如(例如)氮化鋁、氮化硼、金屬氧化物及以上各者之組合。當吸收體212形成為施加於導電圖案上之焊料遮罩之部分時，在實施例中吸收體212為一電絕緣體。
在實施例中，EMI/RFI吸收體212可與用在焊料遮罩210中之其他材料一起混合。在此等實施例中，吸收體212可形成20體積%至40體積%之焊料遮罩。設置於習知焊料遮罩中之一組合物為硫酸鋇。在實施例中，吸收體212可部分或完全取代焊料遮罩中之硫酸鋇。當EMI/RFI吸收體212為肥粒鐵時，吸收體可包含具有高達約30微米之一長度之肥粒鐵股線，但在另外實施例中肥粒鐵股線可更長。此等股線可彼此對準(大體上平行)，或其等可相對於彼此而隨機定向。
在另外實施例中，在將焊料遮罩施加至基板之前，EMI/RFI吸收體212可作為一分離層施加至焊料遮罩210(使得焊料遮罩與吸收體之組合一起施加至基板)。在此等實施例中，吸收體212可懸掛於一彈性體(諸如環氧樹脂或聚矽氧)中且接著在施加焊料遮罩層210之前施加至焊料遮罩材料。
當焊料遮罩為包含吸收體212之一液體時，焊料遮罩可印刷至基板上。當焊料遮罩為一乾燥膜(其包含併入至焊料遮罩中或作為一分離層施加至焊料遮罩之吸收體)時，焊料遮罩可層壓至基板上。
在實施例中，吸收體212有效吸收約100兆赫至約10吉赫(其在實例中為半導體元件200內所輻射之頻率)之一頻率範圍內之EMI/RFI。應瞭解，吸收體212可用於吸收具有高於及低於此範圍之頻率之EMI/RFI。用在吸收體中之顆粒之類型、顆粒尺寸、顆粒密度及焊料遮罩層210之厚度之變動將變動有效性及由吸收體212吸收之頻率範圍。
在實施例中，焊料遮罩層210可介於10微米至40微米之間，但在 另外實施例中其可比該範圍薄或厚。當焊料遮罩層210施加至基板202之上表面與下表面兩者時，EMI/RFI吸收體212可設置於上焊料遮罩層210、下焊料遮罩層210或兩者中。
如上文所指示，EMI/RFI吸收體212可施加於基板上之其他位置中以取代施加於焊料遮罩層210中，或施加於基板上之其他位置及焊料遮罩層210中。例如，圖8展示一實例，其中EMI/RFI吸收體212之一層可施加於基板之一上表面及/或下表面上之焊料遮罩層210上。在此等實施例中，可提供吸收體212作為諸如藉由印刷而施加至基板202之一液體層。替代地，吸收體212可懸掛於層中之一彈性體(諸如環氧樹脂或聚矽氧)中且接著在施加焊料遮罩層210之後層壓至焊料遮罩材料上。
在另外實施例中，EMI/RFI吸收體可併入至基板202之核心203中及焊料遮罩層210內及/或焊料遮罩層210上，或可併入至基板202之核心203中以取代併入至焊料遮罩層210內及/或焊料遮罩層210上。在此一實例中，EMI/RFI吸收體212可包括50體積%至70體積%之核心203，但在另外實施例中核心203內之吸收體可比該範圍大或小。
在形成焊料遮罩層之後，可在步驟114中通過一已知電解電鍍、無電鍍或薄膜沈積程序而用一Ni/Au層或類似物電鍍頂層及底層上之導電圖案(其例如包含接觸墊208)之曝露部分。
在步驟116中，可在一自動檢測程序中檢測及測試基板202，且在步驟120中，基板可經受一最後目視檢測以查看電操作及污染、刮痕與變色。
假定基板202通過檢測，接著，可在步驟122中將一或多個半導體晶粒貼附至基板202之頂面，如圖10及圖11之側視圖及俯視圖所展示。接著，可在步驟126中將該一或多個半導體晶粒線接合至基板202。在所繪示實例中，半導體元件200包含一對記憶體晶粒224及一 控制器晶粒225。記憶體晶粒224可例如為快閃記憶體晶片(NOR/NAND)，但可考量其他類型之記憶體晶粒。應瞭解，可提供一單一記憶體晶粒224及可提供兩個以上記憶體晶粒。控制器晶粒225可例如為一ASIC。
接線226可連接於晶粒224、225上之晶粒接合墊230與基板202上之接觸墊208之間。圖中僅展示及標記晶粒接合墊230及接線226之若干者。雖然晶粒接合墊230在圖中展示為沿著晶粒224、225之一單一側，但應瞭解：晶粒接合墊230及接線226可自晶粒224、225之多個側偏移至基板202之多個邊緣鄰近處之接觸墊208。
雖然圖中未展示，但一或多個被動組件亦可貼附及電耦合至基板202。該一或多個被動組件可安裝於基板202上且在已知表面安裝及回焊程序中諸如藉由連接至接觸墊而電耦合至導電圖案。該等被動組件可例如包含一或多個電容器、電阻器及/或電感器，但可考量其他組件。
在安裝半導體晶粒224、225及/或形成接線226之前或之後，亦可在步驟124中將一接地接針228貼附至基板。接地接針可例如焊接至基板202之一頂面上之一接觸墊上且透過一介層孔(諸如(例如)介層孔205a)而連接至接地平面204a。接地接針可由一電導體(諸如(例如)鋁)形成，且可呈自基板向上延伸之一接針之形狀。在另外實施例中，接地接針228可代以為自基板202之表面向上延伸之一撓性彈簧或夾片。如下文所解釋，接地接針228與完成半導體元件200中之一EMI/RFI屏蔽接觸以使該屏蔽接地。
在步驟128中，半導體元件200可經受一電漿清洗程序以移除微粒且改良表面之可濕性以容許用於保護半導體晶粒及接線之一模製化合物之更佳流動性質。
在晶粒224已安裝及線接合至基板及所貼附之接地接針228之 後，可在一第一囊封步驟(步驟130)中將晶粒224、225、接線226及接地接針228之一部分囊封於一模製化合物240中，如圖12及圖13之側視圖及俯視圖中所展示。在實施例中，可藉由使用例如購自日本Nitto Denko公司之一已知環氧樹脂之轉移模製而形成模製化合物240。
在另一實施例中，可藉由FFT(薄自由流動)壓縮模製而非轉移模製而形成模製化合物240之囊封。例如，在名稱為「Compression Molding Solutions For Various High End Package And Cost Savings For Standard Package Applications」(Microelectronics and Packaging Conference，2009年)之日本京都之Towa公司之Matsutani,H.之一公開案中獲知及描述此一FFT壓縮模製程序，該公開案之全文以引用方式併入本文中。一般而言，一FFT壓縮機利用一項技術：其中基板之面板浸入至含有一熔融樹脂之一模具中。
無論囊封程序之類型如何，均使接地夾228之一頂部部分突出穿過模製化合物。模製化合物240可覆蓋半導體晶粒224、225之全部及基板202之全部。替代地，可施加呈不同組態之模製化合物240，使得屏蔽環之周邊內之基板202之部分缺乏模製化合物。
現參考步驟134及圖14及圖15之側視圖及俯視圖，可在第一囊封程序之後將一或多層之覆蓋材料244沈積於模製化合物240上。在實施例中，覆蓋材料244包含兩個分離層。一第一層244a可為諸如根據上文所描述吸收體212之實施例之任何者之一EMI/RFI吸收體。
第一層244a可施加於模製化合物之全部表面上且向下與焊料遮罩層210接觸以因此將半導體元件200內之半導體晶粒224、225及其他組件完全圍封於EMI/RFI吸收體212內。在另外實施例中，吸收層244a可僅施加至模製化合物240之一頂面，且不施加於向下延伸至基板202之模製化合物之側面上。層244a可印刷或層壓至模製化合物240上。在實施例中，第一層244a可在模製化合物上具有數微米至數百微米之一 厚度。在另外實施例中，該厚度可比該範圍大或小。
材料244之一第二層可為一EMI/RFI屏蔽層244b。當吸收層244a吸收EMI/RFI且將其轉換成熱能時，屏蔽層244b可反射EMI/RFI。屏蔽層244b可為一電導體，諸如(例如)銅。屏蔽層244b可由僅電鍍至吸收層244a上之銅組成，或可為銅頂上之亮鎳。可使用其他導電電鍍材料。對於電鍍，可首先在一無電鍍程序中電鍍鎳或銅作為晶種層。無電鍍鎳或無電鍍銅電鍍提供一晶種層，如PCB工業中所知。該電鍍晶種層充當一電極以容許銅或其他金屬之一隨後更快電解電鍍。第二層244b可具有數奈米至數百微米之一厚度，其部分取決於沈積方法。在另外實施例中，層244b可比該範圍厚或薄。
接地接針228經定尺寸以便位於屏蔽層244b內。因此，屏蔽層244b接地至基板202之接地平面204a。
如同層244a，屏蔽層244b可電鍍於吸收層244a及/或模製化合物240之全部表面上。替代地，屏蔽層244b可設置於模製化合物240(及吸收層244a)之一頂面上，且不設置於向下延伸至基板202之模製化合物240之側面上。
層244a、244b兩者可僅設置於模製化合物240之頂上，或兩者可向下延伸至基板。替代地，吸收層244a設置於模製化合物240之頂部及向下至基板之側面上，但屏蔽層244b僅設置於頂面上且不設置於側面上。作為另一替代，屏蔽層244b設置於模製化合物240之頂部及向下至基板之側面上，但吸收層244a僅設置於頂面上且不設置於側面上。在所展示實施例中，吸收層244a設置於模製化合物240上且屏蔽層244b設置於吸收層244a上。在一替代實施例中，可交換層244a、244b之位置，使得屏蔽層244b設置於模製化合物240上且吸收層244a設置於屏蔽層244b上。
基板202中或基板202上之吸收材料212連同材料244之層244a、 244b減少半導體元件200之EMI及/或RFI。在一實例中，吸收材料212及材料244可在自100兆赫至10吉赫之頻率範圍內使干擾減小15分貝。應瞭解，在另外實施例中，可在此頻率範圍或其他範圍內使干擾減小15分貝以上或15分貝以下。
現參考圖16及圖17之側視圖及俯視圖，在覆蓋步驟之後，可在步驟136中執行一第二囊封程序。此步驟可施加一模製化合物248以完全封閉半導體元件200上之覆蓋材料244。模製化合物248可為與模製化合物240相同之材料之任何者，且可在用於施加模製化合物240之相同程序之任何者中施加模製化合物248。在另外實施例中，模製化合物248無需相同於模製化合物240，其例如包含FFT壓縮模製。雖然步驟136中之第二囊封程序係有利的，但應瞭解：可在另外實施例中省略第二囊封程序以使覆蓋材料244作為元件200之外表面。
在步驟140中，可將焊料球252施加至半導體元件200之底面上之接觸墊218，如圖18之側視圖所展示。焊料球容許元件200表面安裝至一主機元件中之一PCB(圖中未展示)。接觸墊218包含接地墊218a，其可各接收一焊料球252a。接地接針228可藉由介層孔205a、接地墊218a及焊料球252a而耦合至該PCB上之一接地位置。
在另外實施例中，可省略包含焊料球252a之焊料球252。例如，半導體元件200可為可移除地插入至一主機元件之操作位置中之一地柵陣列(LGA)封裝。在此等封裝中，元件200之底面上之接觸墊218可為接觸指。此等接觸指之一或多者可為經設計以與該主機元件中之一接地連接配合之一接地指。在此實施例中，接地接針228可電耦合至此一接地指。
在施加焊料球之後或在其中省略焊料球之第二囊封步驟之後，可在步驟144中自面板201單切半導體元件200以形成完成半導體元件200。可藉由各種切割方法(其包含鋸切、水噴切割、雷射切割、水導 雷射切割、乾式介質切割及金剛石塗層線切割)之任何者而單切各元件200。雖然直線切割將界定一大體上呈矩形或方形形狀之元件200，但應瞭解：在本發明之另外實施例中，元件200可具有除矩形及方形以外之形狀。
在切割成元件200之後，可在步驟148中測試元件以判定封裝是否適當運作。如此項技術中所知，此測試可包含電測試、預燒測試及其他測試。可在步驟150中視情況將元件封閉於一蓋子內。
總而言之，在一實施例中，本發明係關於一種半導體元件，其包括：一基板，其包含一介電核心、該介電核心上之一導電層及該導電層上之一焊料遮罩層，該基板包含用於吸收EMI及RFI之至少一者之一吸收材料；及一或多個半導體晶粒，其等貼附至該基板。
在另一實施例中，本發明係關於一種半導體元件，其包括：一基板；一焊料遮罩層，其位於該基板上，該焊料遮罩層包含用於吸收EMI及RFI之至少一者之一第一吸收材料；一或多個半導體晶粒，其等貼附及電連接至該基板；一模製化合物，其至少囊封該一或多個半導體晶粒；及一層，其設置於該模製化合物上，該等包含用於吸收EMI及RFI之至少一者之一第二吸收材料。
在另一實施例中，本發明係關於一種半導體元件，其包括：一基板；一焊料遮罩層，其位於該基板上，該焊料遮罩層包含用於吸收EMI及RFI之至少一者之一第一吸收材料；一或多個半導體晶粒，其等貼附及電連接至該基板；一模製化合物，其至少囊封該一或多個半導體晶粒；及第一及第二層，其等設置於該模製化合物上，該第一層包含用於吸收EMI及RFI之至少一者之一第二吸收層，且該第二層包含用於使半導體元件屏蔽EMI及RFI之至少一者之一導電材料。
在又一實施例中，本發明係關於一種使一半導體元件屏蔽EMI及RFI之至少一者之方法，其包括以下步驟：(a)將一或多個半導體晶粒 安裝於一基板上；(b)將該基板上之該一或多個半導體晶粒囊封於模製化合物中；及(c)將該一或多個半導體晶粒完全囊封於吸收EMI及RFI之至少一者之一或多層之吸收材料中。
已出於繪示及描述目的而呈現本發明之前述詳細描述。不意欲具窮舉性或將本發明限制於所揭示之精確形式。可根據上文教示而進行諸多修改及變動。選擇所描述之實施例以最佳地解釋本發明之原理及其實際應用以藉此使熟習技術者能夠在各種實施例中最佳地利用本發明且使本發明與適合於特定預期使用之各種修改一起使用。意欲由本發明之隨附申請專利範圍界定本發明之範疇。

Claims (16)

  1. 一種半導體元件，其包括：一基板；一焊料遮罩層，其位於該基板上，該焊料遮罩層包含用於吸收EMI及RFI之至少一者之一第一吸收材料，該第一吸收材料係一電絕緣體；一或多個半導體晶粒，其等貼附及電連接至該基板；一模製化合物，其至少囊封該一或多個半導體晶粒；及設置於該模製化合物上之第一及第二層，該第一層包含用於吸收EMI及RFI之至少一者之一第二吸收材料，且該第二層包含用於使該半導體元件屏蔽EMI及RFI之至少一者之一接地導電材料。
  2. 如請求項1之半導體元件，其進一步包括連接至該基板中之一接地平面且連接至該第二層之一接地接針。
  3. 如請求項1之半導體元件，其中該等第一與第二吸收材料具有相同組合物。
  4. 如請求項1之半導體元件，其中該第二吸收材料之該第一層設置於該模製化合物之一頂面上且設置於向下延伸且與該基板上之該焊料遮罩層接觸之該模製化合物之側面上，該等第一及第二吸收材料完全封閉該一或多個半導體晶粒。
  5. 如請求項1之半導體元件，其中該第二吸收材料之該第一層設置於該模製化合物之一頂面上且不設置於延伸成與該焊料遮罩層接觸之該模製化合物之側面上。
  6. 如請求項1之半導體元件，其中該第二吸收材料之該第一層設置於該模製化合物上，且該導電材料之該第二層設置於該第一層之吸收材料上。
  7. 如請求項1之半導體元件，其中該導電材料之該第二層設置於該模製化合物上，且該第二吸收材料之該第一層設置於該第二層之導電材料上。
  8. 如請求項1之半導體元件，其中該第一層與該第二層係彼此接觸。
  9. 如請求項1之半導體元件，其中該第二層係經電鍍至該第一層上。
  10. 如請求項1之半導體元件，其中第一吸收材料及該第二吸收材料係不同組合物。
  11. 如請求項10之半導體元件，其中該第二吸收材料係一電絕緣體。
  12. 一種使一半導體元件屏蔽EMI及RFI之至少一者之方法，其包括以下步驟：(a)將一或多個半導體晶粒安裝於一基板上，其中一焊料遮罩層係設置於該基板上，且該焊料遮罩層包含用於吸收EMI及RFI之至少一者之一第一吸收材料，且其中該第一吸收材料係一電絕緣體；(b)將該基板上之該一或多個半導體晶粒囊封於模製化合物中；及(c)將該一或多個半導體晶粒完全囊封於第一層及第二層中，該第一層係以吸收材料提供，其吸收EMI及RFI之至少一者，且該第二層係以接地反射材料提供，其反射EMI及RFI之至少一者。
  13. 如請求項12之方法，其進一步包括步驟(e)：將該導電屏蔽層接地至該基板。
  14. 如請求項13之方法，其中該步驟(e)包括以下步驟：藉由安裝於該基板上且延伸成與該導電屏蔽層接觸之一接地接針而將該導電屏蔽層接地至該基板。
  15. 如請求項12之方法，其中該步驟(c)包括將一層吸收材料施加於該模製化合物上之步驟，該方法進一步包括步驟(f)：在圍繞該層吸收材料而施加模製化合物之該等步驟(b)及(c)之後，執行一第二囊封步驟。
  16. 如請求項12之方法，其中該第一層之該吸收材料係一電絕緣體，且其中該第一吸收材料及該吸收材料係不同組合物。
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