WO2013029533A1 - 一种芯片封装结构、封装方法及电子设备 - Google Patents

一种芯片封装结构、封装方法及电子设备 Download PDF

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Publication number
WO2013029533A1
WO2013029533A1 PCT/CN2012/080683 CN2012080683W WO2013029533A1 WO 2013029533 A1 WO2013029533 A1 WO 2013029533A1 CN 2012080683 W CN2012080683 W CN 2012080683W WO 2013029533 A1 WO2013029533 A1 WO 2013029533A1
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Prior art keywords
chip
shielded
pad
pcb
shield
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PCT/CN2012/080683
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English (en)
French (fr)
Inventor
赵龙
李春澍
Original Assignee
华为终端有限公司
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Publication date
Application filed by 华为终端有限公司 filed Critical 华为终端有限公司
Priority to EP12799503.3A priority Critical patent/EP2602819A4/en
Priority to US13/722,270 priority patent/US20130113088A1/en
Publication of WO2013029533A1 publication Critical patent/WO2013029533A1/zh

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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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Definitions

  • the invention relates to a chip packaging structure, a packaging method and an electronic device.
  • the application is submitted to the Chinese Patent Office on September 2, 2011, and the application number is 201110258811. 8.
  • the invention name is "a chip package structure, a packaging method and an electronic device".
  • Priority of Chinese Patent Application the entire contents of which is incorporated herein by reference.
  • the present invention relates to the field of chip packaging, and in particular, to a chip package structure, a packaging method, and an electronic device.
  • a chip may be interfered with by an external electromagnetic signal, thereby causing degradation or even damage to the performance of the chip, and causing a failure of the device in which the chip is located.
  • the chip package structure usually adopts a method of spraying conductive paint on the surface of the molded chip to shield the interference of external electromagnetic signals.
  • the shielding film formed by the conductive paint in the chip package structure is easy to fall off, thereby causing the anti-interference ability of the chip package structure to be lowered, thereby causing the shielding function to be unsatisfactory.
  • Embodiments of the present invention provide a chip package structure, a package method, and an electronic device for solving the problem that a shielding film formed by a conductive paint in a chip package structure is easily detached.
  • the embodiment of the present invention adopts the following technical solutions:
  • a chip package structure including:
  • the shield cover is fixedly fastened on a part surface of the PCB board;
  • the chip to be shielded is disposed on a surface of the component of the PCB, and is located in the shield, and a pin of the chip to be shielded is connected to a first pad on the PCB;
  • the chip to be shielded is not in contact with the shield.
  • a chip packaging method including:
  • a shielding cover is disposed on a surface of the component of the PCB, and the shielding cover is fixedly connected to the second pad, and the shielding cover is not in contact with the chip to be shielded.
  • an electronic device comprising: the chip package structure described above.
  • a chip package structure, a package method, and an electronic device are provided in the embodiment of the present invention, wherein the chip package structure includes: a PCB board, a shield cover fixed on the component surface of the PCB board, and a chip to be shielded;
  • the chip to be shielded is disposed on the surface of the component of the PCB, is located in the shield, and the pin of the chip to be shielded is connected to the first pad on the PCB, so that the pin of the chip to be shielded can pass The first pad of the PCB is led out; at the same time, the chip to be shielded is not in contact with the shield, so that the shield does not interfere with the work of the chip to be shielded.
  • the shield cover is fixedly fastened on the PCB board, and the shield cover in the chip package structure is not easy to fall off, thereby improving the anti-interference ability of the chip package structure.
  • FIG. 1 is a cross-sectional view showing a chip package structure according to an embodiment of the present invention
  • FIG. 2 is a top plan view of a chip package structure according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a chip packaging method according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of another chip packaging method according to an embodiment of the present invention.
  • the chip package structure 100 provided by the embodiment of the present invention, as shown in FIG. 1, includes a PCB (Printed Circuit Board) 11, a shield 12, and a chip 13 to be shielded.
  • the shielding cover 12 is fixedly fastened on the component surface of the PCB board 11, that is, the A surface in FIG. 1, and the shielding chip 13 is disposed on the component surface of the PCB board 11, located in the shielding cover 12, and the chip to be shielded
  • the pin of 13 is connected to the first pad 16 on the PCB board 11; the chip 13 to be shielded is not in contact with the shield case 12.
  • the chip to be shielded in this embodiment may be a bare chip, a packaged chip, a chip or a chip set coated with a conductive paint, which is required to be isolated from external electromagnetic waves.
  • the shielding cover may be any cover body capable of shielding external electromagnetic waves, and the chip to be shielded in the shielding cover may be isolated from external electromagnetic waves; at the same time, the shielding cover is fixedly fastened on the component surface of the PCB board, and is fixed.
  • the method can be any way of fixing the shielding cover on the PCB board, so that the shielding cover in the chip packaging structure is not easy to fall off, thereby improving the anti-interference ability of the chip packaging structure.
  • the first pad can be fixedly connected to the pin of the chip to be shielded on the one hand, and can also lead the pin of the chip to be shielded on the surface of the PCB to the non-part surface.
  • the shield 12 includes: a metal piece 122, and an electrical conductor 121 that contacts and supports the metal piece 122.
  • the shield cover 12 is fixedly fastened to the component surface of the PCB board 11.
  • the conductor 121 of the shield cover 12 is soldered to the second pad 15 on the component surface of the PCB board 11.
  • the metal piece of the shielding cover not only prevents the chip to be shielded from being subjected to external electromagnetic interference, but also plays a good heat dissipation function; compared with the prior art, it does not need to rely on the PCB board to dissipate heat, thereby avoiding It affects other circuits on the PCB.
  • the shape of the pad may be various, and may be a circle, a square, an ellipse, a rectangle, an octagon or the like, and the specific shape thereof is determined by the shape of the element carried by the element.
  • the shape of the first pad is determined by the shape of the pin
  • the shape of the second pad is determined by the shape of the conductor.
  • the electrical conductor 121 is a bare conductor on the surface, and may specifically be a metal wire or a solder ball. Further preferably, the electrical conductor is grounded; the electrical conductor may be grounded by connecting the electrical conductor to the grounding pin of the chip to be shielded, or the second electrical pad may be used to lead the electrical conductor out of the ground. The body is grounded so that the shield can better shield the external electromagnetic signal.
  • the shield 14 and the PCB 11 provided with the chip 13 to be shielded are filled with an insulator 14.
  • the insulator may be plastic.
  • the insulator can not only make the shield cover and the chip to be shielded from contacting, so that the shield can not interfere with the work of the chip to be shielded; in addition, the insulator can also function as a shield and a PCB.
  • the support between the boards is to make the chip package structure more secure.
  • the pin of the chip to be shielded 13 is connected to the first pad 16 on the PCB board 11 and includes: the pin of the chip to be shielded 13 is soldered to one end of the wire 17, and the wire 17 is The other end is soldered to the first pad 16 on the PCB board 11.
  • This connection method is a conventional chip bonding process in which the wires can use gold wires or aluminum wires used in a conventional process.
  • the manner in which the pins of the shielded chip are connected to the first pad is not limited to being connected by wires.
  • the corresponding first pad position may be set according to the pin position of the chip to be shielded, and the tube to be shielded is to be shielded. The foot is soldered directly to the first pad.
  • the chip package structure further includes: a package housing; the package housing is provided with a third pad corresponding to the pin of the chip to be shielded; The third pad is connected to the first pad to lead the pin of the chip to be shielded corresponding to the third pad.
  • the package housing provided with the third pad is not shown in the drawing, but those skilled in the art can understand the chip package structure described in the present invention according to the existing packaging process.
  • FIG. 2 is a top view of a chip package structure according to an embodiment of the present invention.
  • the positional relationship of each part of the chip package structure 100 provided by the embodiment of the present invention can be further seen through FIG. 2, and the unidentified metal piece in FIG. 2 needs to be described. , insulation between metal sheets and PCB boards, etc.
  • the chip 13 to be shielded is located on the PCB board 11.
  • Electrical conductors 121 are disposed around the PCB board, and the pins and wires 17 of the chip 13 to be shielded are shielded. One end of the wire 17 is soldered, and the other end of the wire 17 is soldered to the first pad 16 on the PCB board 11.
  • the embodiment of the present invention further provides a chip packaging method, as shown in FIG. 3, and in conjunction with FIG. 1, the packaging method specifically includes the following steps:
  • the pin of the chip to be shielded 13 is connected to the first pad 16 by a chip bonding process
  • a shield cover 12 is disposed on the surface of the component of the PCB board 11, and the shield cover 12 is fixedly connected to the second pad 15, and the shield cover 12 is not in contact with the chip 13 to be shielded.
  • the chip packaging method provided by the embodiment of the invention can fix the chip to be shielded in the shielding cover from external electromagnetic waves by fixing the shielding cover on the surface of the PCB board on the PCB board; The cover is fixedly fastened on the PCB, so that the shield in the chip package structure is not easy to fall off; at the same time, the shield to be shielded is not in contact with the shield, so that the shield does not interfere with the work of the chip to be shielded.
  • S303 may specifically include:
  • the second pad 15 on the part surface of the PCB board 11 is soldered with the electrical conductor 121; Then, the surface of the part of the PCB board 11 is injection molded, and the plastic plane is higher than the chip 13 to be shielded and lower than the conductor 121;
  • the metal plate is placed on the electrical conductor 121 of the PCB board 11 and pressed so that the metal plate 122 is in close contact with the plastic and is in good contact with the electrical conductor; after the plastic is cured, the metal plate is cured. Bonded to plastic.
  • the plastic In the above injection molding process, the plastic is in a liquid state, and it is at a certain temperature, at which the electrical conductor will soften to some extent; before the plastic is completely cured, pressing the metal plate onto the electrical conductor can make both Good contact, in addition, because the plastic is not fully cured, pressing the metal plate to the plastic tightly can make the metal plate adhere to the plastic after curing; this can ensure that the metal plate will not peel off easily, and the production is guaranteed.
  • the robustness of the completed chip package structure is possible.
  • the method for manufacturing the chip package structure provided by the present invention may further include:
  • the chip package structure provided with the shield is packaged in the package by a packaging process, and the pin of the chip to be shielded is led out by a third pad on the package.
  • the first pad and the third pad may be connected by using a wire, so that the pin of the chip to be shielded is taken out to complete the package.
  • the packaging process can refer to the packaging process in the prior art, such as BGA (Ball Grid Array, Ball Grid Array) package, QFN (Quad Flat No-lead Package) and other packaging processes. Since the packaging process is known to those skilled in the art, it will not be described here.
  • chip packaging method shown in FIG. 3 or FIG. 4 can be applied to the manufacturing process of the actual chip package structure as a reference, but the order of the package method is not limited to the order shown in FIG. 3 or FIG.
  • an embodiment of the present invention further provides an electronic device, including: any one of the above chip package structures.
  • the electronic device can be a mobile terminal, and of course any electronic device of the chip can be used.
  • the mobile phone is taken as an example for detailed description.
  • the mobile phone hardware mainly includes: a display screen, an upper cover (front cover), a lower cover (rear cover), a battery cover, a speaker microphone and a motherboard, etc., wherein the motherboard further includes a radio frequency chip, a baseband chip, a power management chip, and a flash memory chip (flash) Speed memory chip), the pins of the chips on these motherboards are connected with peripherals such as the antenna, display, speaker microphone of the mobile phone, and realize the basic functions of the mobile phone.
  • the motherboard further includes a radio frequency chip, a baseband chip, a power management chip, and a flash memory chip (flash) Speed memory chip
  • the chip package structure provided by the embodiment of the present invention may be used in any one or more (two or more) of the radio frequency chip, the baseband chip, the power management chip, and the flash memory chip, so that the chip that needs to be packaged in the mobile phone is not easy to be used. Affected by external electromagnetic waves, it has strong anti-interference ability.

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Abstract

一种芯片封装结构、封装方法及电子设备,设计芯片封装领域,用以解决芯片封装结构中导电漆形成的屏蔽膜容易脱落的问题。所述芯片封装结构,包括:印刷电路板PCB板(11);屏蔽罩(12);所述屏蔽罩(12)固定扣置在所述PCB板(11)的零件面(A)上,待屏蔽芯片(13);所述待屏蔽芯片(13)设置在所述PCB板的零件面(A)上,位于所述屏蔽罩(12)之内,且所述待屏蔽芯片(13)的管脚与所述PCB板(11)上的第一焊盘(16)相连接;所述待屏蔽芯片(13)与所述屏蔽罩(12)不接触。提供的方案可以应用于芯片的封装。

Description

种芯片封装结构、 封装方法及电子设备 本申请要求于 2011年 09月 02日提交中国专利局、申请号为才能 201110258811. 8、 发明名称为 "一种芯片封装结构、 封装方法及电子设备"的中国专利申请的优先权, 其 全部内容通过引用结合在本申请中。 技术领域 本发明涉及芯片封装领域, 尤其涉及一种芯片封装结构、 封装方法及电子设备。
背景技术 在高密度封装技术中, 芯片可能受到来自外界电磁信号的干扰, 从而造成芯片的性 能下降甚至损坏, 并连带造成该芯片所在的设备引发故障。
目前已经出现具有屏蔽功能的芯片封装结构, 该芯片封装结构通常采用在塑封后的 芯片表面喷涂导电漆的方式, 以屏蔽外界电磁信号的干扰。 但这种芯片封装结构中由导 电漆形成的屏蔽膜容易脱落, 从而导致这种芯片封装结构的抗干扰能力降低, 也就造成 了其屏蔽功能的不理想。
发明内容 本发明的实施例提供一种芯片封装结构、 封装方法及电子设备, 用以解决芯片封装 结构中导电漆形成的屏蔽膜容易脱落的问题。
为解决上述问题, 本发明的实施例采用如下技术方案:
一方面, 提供一种芯片封装结构, 包括:
印刷电路板 PCB板;
屏蔽罩; 所述屏蔽罩固定扣置在所述 PCB板的零件面上;
待屏蔽芯片; 所述待屏蔽芯片设置在所述 PCB板的零件面上, 位于所述屏蔽罩内, 且所述待屏蔽芯片的管脚与所述 PCB板上的第一焊盘相连接;
所述待屏蔽芯片与所述屏蔽罩不接触。
另一方面, 提供一种芯片封装方法, 包括:
在印刷电路板 PCB板上设计第一焊盘、 第二焊盘; 在所述 PCB板的零件面上,采用芯片键合工艺将待屏蔽芯片的管脚与所述第一焊盘 连接;
在所述 PCB板的零件面上设置屏蔽罩, 将所述屏蔽罩与所述第二焊盘固定连接, 且 所述屏蔽罩与所述待屏蔽芯片不接触。
又一方面, 提供一种电子设备, 包括: 上述的芯片封装结构。
本发明实施例提供的一种芯片封装结构、 封装方法及电子设备, 其中所述芯片封装 结构包括: PCB板, 固定扣置在 PCB板的零件面上的屏蔽罩, 以及待屏蔽芯片; 其中, 待屏蔽芯片设置在 PCB板的零件面上,位于屏蔽罩之内,且待屏蔽芯片的管脚与所述 PCB 板上的第一焊盘相连接, 这样就可以将待屏蔽芯片的管脚通过 PCB板的第一焊盘导出; 同时, 待屏蔽芯片与屏蔽罩不接触, 这样屏蔽罩就不会干扰待屏蔽芯片工作。 与现有技 术相比, 本发明实施例提供的芯片封装结构中屏蔽罩固定扣置在 PCB板上, 这种芯片封 装结构中的屏蔽罩不易脱落, 进而能够提高芯片封装结构的抗干扰能力。
附图说明 为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对实施例或现 有技术描述中所需要使用的附图作简单地介绍, 显而易见地, 下面描述中的附图仅仅 是本发明的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动的前提 下, 还可以根据这些附图获得其他的附图。
图 1为本发明实施例提供的芯片封装结构的剖面图;
图 2为本发明实施例提供的芯片封装结构的俯视图;
图 3为本发明实施例提供的一种芯片封装方法流程图;
图 4为本发明实施例提供的另一芯片封装方法流程图。
附图标记:
100-芯片封装结构; 11-PCB板, 12-屏蔽罩, 121-导电体, 122-金属片, 13-待屏 蔽芯片, 14-绝缘物, 15-第二焊盘, 16-第一焊盘, 17-导线。
具体实施方式 下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行清楚、 完 整地描述, 显然, 所描述的实施例仅仅是本发明一部分实施例, 而不是全部的实施例。 基于本发明中的实施例, 本领域普通技术人员在没有做出创造性劳动前提下所获得的 所有其他实施例, 都属于本发明保护的范围。
本发明实施例提供的芯片封装结构 100,如图 1所示,包括 PCB板 (Printed Circuit Board, 印刷电路板) 11, 屏蔽罩 12, 待屏蔽芯片 13。 其中, 屏蔽罩 12固定扣置在 PCB板 11的零件面即图 1中 A面上, 待屏蔽芯片 13设置在 PCB板 11的零件面上, 位 于所述屏蔽罩 12之内,且待屏蔽芯片 13的管脚与 PCB板 11上的第一焊盘 16相连接; 待屏蔽芯片 13与屏蔽罩 12不接触。
本实施例中的待屏蔽芯片可以是需要与外界电磁波隔离的裸芯片、 已封装芯片、 喷涂导电漆的芯片或芯片组等。
所述屏蔽罩可以是任意能够屏蔽外界电磁波的罩体, 可以使位于该屏蔽罩内的待 屏蔽芯片与外界电磁波隔离; 同时, 该屏蔽罩固定扣置在 PCB板的零件面上, 且固定 的方式可以是任意将屏蔽罩固定在 PCB板上的方式, 这样就使得芯片封装结构中的屏 蔽罩不易脱落, 进而可以提高芯片封装结构抗干扰能力。
特别地, 所述第一焊盘一方面可以固定连接待屏蔽芯片的管脚, 另一方面还可以 将 PCB板零件面的待屏蔽芯片的管脚引至非零件面。
进一步地, 屏蔽罩 12包括: 金属片 122, 以及接触并支撑金属片 122的导电体 121。 此时, 所述屏蔽罩 12固定扣置在所述 PCB板 11的零件面上具体可以为: 屏蔽 罩 12的导电体 121焊接在 PCB板 11的零件面上的第二焊盘 15上。 在本实施例中, 屏蔽罩的金属片不仅起到防止待屏蔽芯片受外界电磁干扰的作用, 还起到良好的散热 作用; 与现有技术相比, 不需要依靠 PCB板散热, 从而可以避免对 PCB板上的其他电 路产生影响。
需要说明的是, 焊盘形状可以有多种, 可以是有圆形、 方形、 椭圆形、 矩形、 八 边形等, 其具体形状由其所承载的元件形状决定。 在本实施例中, 第一焊盘的形状由 管脚形状决定, 第二焊盘的形状由导电体形状决定。
优选的, 所述导电体 121为表面裸露的导电体, 具体可以为金属线或焊球。 进一 步优选的, 所述导电体接地; 导电体接地的方式可以是将导电体连接至待屏蔽芯片的 接地管脚,也可以由第二焊盘将导电体引出接地, 当然不排除其他方式将导电体接地, 以使得屏蔽罩可以更好的屏蔽外界电磁信号的干扰。
进一步的,屏蔽罩 12和设置有待屏蔽芯片 13的 PCB板 11之间填充有绝缘物 14。 优选的,绝缘物可以为塑胶。该绝缘物不仅可以使得屏蔽罩和待屏蔽芯片之间不接触, 从而使得屏蔽罩不会干扰待屏蔽芯片工作; 另外, 该绝缘物还可以起到屏蔽罩与 PCB 板之间的支撑作用, 以使得芯片封装结构更加牢固。
进一步的, 所述待屏蔽芯片 13的管脚与所述 PCB板 11上的第一焊盘 16相连接 包括: 所述待屏蔽芯片 13的管脚与导线 17的一端相焊接, 且导线 17的另一端与所 述 PCB板 11上的第一焊盘 16相焊接。 这种连接方式是采用传统的芯片键合工艺, 其 中, 所述导线可以使用传统工艺中使用的金线或铝线。 当然, 待屏蔽芯片的管脚与第 一焊盘连接方式不限于通过导线连接, 示例的, 也可以根据待屏蔽芯片的管脚位置设 置好相应的第一焊盘位置, 将待屏蔽芯片的管脚直接焊接在第一焊盘上。
更进一步的, 若所述芯片封装结构还需要封装, 则上述芯片封装结构还包括: 封 装外壳; 所述封装外壳上设置有与所述待屏蔽芯片的管脚对应的第三焊盘; 所述第三 焊盘与第一焊盘连接, 以便将与该第三焊盘对应的待屏蔽芯片的管脚引出。 需要说明 的是该设置有第三焊盘的封装外壳在图示中并未标示, 但本领域技术人员可以根据现 有的封装工艺理解本发明所描述的芯片封装结构。
图 2为本发明实施例提供的芯片封装结构的俯视图, 通过图 2可以进一步看清本 发明实施例提供的芯片封装结构 100的各个部分的位置关系, 需要说明的是图 2中未 标识金属片、 金属片与 PCB板之间的绝缘物等。 参考图 2所示, 并结合上述对芯片封 装结构的描述, 可以清楚了解待屏蔽芯片 13位于 PCB板 11上, 在 PCB板的四周设置 有导电体 121, 待屏蔽芯片 13的管脚与导线 17的一端相焊接, 导线 17的另一端与 PCB板 11上的第一焊盘 16相焊接。 本发明实施例还提供了芯片封装方法, 如图 3所示, 并结合图 1, 该封装方法具 体包括以下步骤:
5301、 在印刷电路板 PCB板 11上设计第一焊盘 16、 第二焊盘 15;
5302、 在 PCB板 11的零件面上, 采用芯片键合工艺将待屏蔽芯片 13的管脚与第 一焊盘 16连接;
S303、 在 PCB板 11的零件面上设置屏蔽罩 12, 将屏蔽罩 12与第二焊盘 15固定 连接, 且屏蔽罩 12与待屏蔽芯片 13不接触。
本发明实施例提供的芯片封装方法, 通过在 PCB板上固定扣置在 PCB板的零件面 上的屏蔽罩, 使得位于屏蔽罩之内的待屏蔽芯片可以免受外界电磁波的干扰; 并且由 于屏蔽罩固定扣置在 PCB板上, 使得这种芯片封装结构中的屏蔽罩不易脱落; 同时, 待屏蔽芯片与屏蔽罩不接触, 这样屏蔽罩就不会干扰待屏蔽芯片工作。
进一步的, S303具体可以包括:
首先, 在所述 PCB板 11的零件面上的第二焊盘 15焊接导电体 121 ; 然后, 在所述 PCB板 11的零件面上注塑, 并且塑胶平面高于待屏蔽芯片 13、 低 于导电体 121 ;
最后, 在塑胶未完全固化之前, 将金属板置于所述 PCB板 11的导电体 121之上, 并压合使得金属板 122紧贴塑胶, 且与导电体良好接触; 塑胶固化后, 金属板与塑胶 粘合。
由于上述的注塑过程中, 塑胶呈液态, 其自身处于一定温度, 在该温度下导电体 会在一定程度软化; 在塑胶未完全固化之前, 将金属板压合在导电体之上就可以使得 两者良好接触, 另外, 由于塑胶未完全固化, 将金属板压合至紧贴塑胶, 就可以使得 塑胶固化后, 金属板与塑胶粘合; 这就能够保证金属板不会轻易剥落, 也保证了制作 完成的芯片封装结构的牢固性。
更进一步的, 如果芯片封装结构还需要封装, 则本发明提供的芯片封装结构的制 作方法, 如图 4所示, 还可以包括:
S304、 通过封装工艺将设置有屏蔽罩的芯片封装结构封装在封装外壳中, 由封装 外壳上的第三焊盘将待屏蔽芯片的管脚引出。
具体的, 可以利用导线将第一焊盘与第三焊盘连接, 从而将所述待屏蔽芯片的管 脚引出, 完成封装。
该封装工艺可以参考现有技术中的封装工艺, 例如 BGA (英文全称为 Ball Grid Array, 球栅阵列结构) 封装、 QFN ( Quad Flat No-lead Package, 方形扁平无引脚 封装) 等封装工艺。 由于封装工艺是本领域技术人员所了解的, 故在此就不再赘述。
需要说明的是, 图 3或图 4所示的芯片封装方法可以作为参考应用于实际芯片封 装结构的制造过程中, 但封装方法的顺序不限于图 3或图 4所示的顺序。
另外, 本发明实施例还提供了一种电子设备, 包括: 上述任一芯片封装结构。 该 电子设备可以是移动终端, 当然也可以使用芯片的任何一种电子设备。
下面, 以手机为例进行详述。
手机硬件主要包括: 显示屏、 上盖 (前盖)、 下盖 (后盖)、 电池盖、 扬声器麦克 风和主板等, 其中主板又包括射频芯片、 基带芯片、 电源管理芯片、 Flash存储芯片 (闪速存储芯片), 这些主板上的芯片的引脚与手机的天线、 显示屏、 扬声器麦克风 等外围设备连接, 就实现了手机的基本功能。
所述射频芯片、基带芯片、 电源管理芯片、 Flash存储芯片中的任一个或多个(两 个以上) 都可以采用本发明实施例提供的芯片封装构造, 以使得该手机中需要封装的 芯片不易受外界电磁波影响, 抗干扰能力强。
以上所述, 仅为本发明的具体实施方式, 但本发明的保护范围并不局限于此, 任 何熟悉本技术领域的技术人员在本发明揭露的技术范围内, 可轻易想到变化或替换, 都应涵盖在本发明的保护范围之内。 因此, 本发明的保护范围应以所述权利要求的保 护范围为准。

Claims

权利要求
1、 一种芯片封装结构, 其特征在于, 包括:
印刷电路板 PCB板;
屏蔽罩; 所述屏蔽罩固定扣置在所述 PCB板的零件面上;
待屏蔽芯片;所述待屏蔽芯片设置在所述 PCB板的零件面上,位于所述屏蔽罩内, 且所述待屏蔽芯片的管脚与所述 PCB板上的第一焊盘相连接;
所述待屏蔽芯片与所述屏蔽罩不接触。
2、 根据权利要求 1 所述的芯片封装结构, 其特征在于, 所述屏蔽罩包括: 金属 片, 以及接触并支撑该金属片的导电体;
所述屏蔽罩固定扣置在所述 PCB板的零件面上包括:
所述屏蔽罩的导电体焊接在所述 PCB板的零件面上的第二焊盘上。
3、 根据权利要求 2 所述的芯片封装结构, 其特征在于, 所述导电体为金属线或 焊球。
4、 根据权利要求 2所述的芯片封装结构, 其特征在于, 所述导电体接地。
5、 根据权利要求 1-4任一项权利要求所述的芯片封装结构, 其特征在于, 所述 待屏蔽芯片的管脚与所述 PCB板上的第一焊盘相连接包括:
所述待屏蔽芯片的管脚与导线的一端相焊接, 且导线的另一端与所述 PCB板上的 第一焊盘相焊接。
6、 根据权利要求 广 5 任一项权利要求所述的芯片封装结构, 其特征在于, 所述 待屏蔽芯片与所述屏蔽罩不接触包括:
所述屏蔽罩和设置有待屏蔽芯片的 PCB板之间填充有绝缘物。
7、 根据权利要求 6所述的芯片封装结构, 其特征在于, 所述绝缘物为塑胶。
8、 根据权利要求 广 7 任一项权利要求所述的芯片封装结构, 其特征在于, 还包 括: 封装外壳; 所述封装外壳上设置有与所述待屏蔽芯片的管脚对应的第三焊盘; 所述第三焊盘与第一焊盘连接, 以便将与该第三焊盘对应的待屏蔽芯片的管脚引 出。
9、 一种芯片封装方法, 其特征在于, 包括:
在印刷电路板 PCB板上设计第一焊盘、 第二焊盘;
在所述 PCB板的零件面上, 采用芯片键合工艺将待屏蔽芯片的管脚与所述第一焊 盘连接;
在所述 PCB板的零件面上设置屏蔽罩, 将所述屏蔽罩与所述第二焊盘固定连接, 且所述屏蔽罩与所述待屏蔽芯片不接触。
10、 根据权利要求 9所述的芯片封装方法, 其特征在于, 所述在所述 PCB板的零 件面上设置屏蔽罩, 将屏蔽罩与所述第二焊盘固定连接, 且所述屏蔽罩与所述待屏蔽 芯片不接触包括:
在所述 PCB板的零件面上的第二焊盘焊接导电体;
在所述 PCB板的零件面上注塑, 并且塑胶平面高于待屏蔽芯片、 低于导电体; 在塑胶未完全固化之前, 将金属板置于所述 PCB板的导电体之上, 并压合使得金 属板紧贴塑胶, 且与导电体良好接触; 塑胶固化后, 金属板与塑胶粘合。
11、 根据权利要求 9或 10所述的芯片封装方法, 其特征在于, 还包括: 通过封装工艺将设置有屏蔽罩的芯片封装在封装外壳中, 由封装外壳上的第三焊 盘将待屏蔽芯片的管脚引出。
12、 一种电子设备, 其特征在于, 包括: 权利要求广 8任一项所述的芯片封装结 构。
PCT/CN2012/080683 2011-09-02 2012-08-29 一种芯片封装结构、封装方法及电子设备 WO2013029533A1 (zh)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9192057B2 (en) 2012-12-26 2015-11-17 Apple Inc. Electromagnetic interference shielding structures
KR102041635B1 (ko) * 2013-06-04 2019-11-07 삼성전기주식회사 반도체 패키지
US10224290B2 (en) * 2015-12-24 2019-03-05 Intel Corporation Electromagnetically shielded electronic devices and related systems and methods
CN105792504B (zh) * 2016-03-01 2018-09-28 中国电子科技集团公司第五十四研究所 一种具有屏蔽措施的pcb空穴埋置装置及制备工艺
US10453762B2 (en) 2017-07-28 2019-10-22 Micron Technology, Inc. Shielded fan-out packaged semiconductor device and method of manufacturing
CN107481997A (zh) * 2017-09-05 2017-12-15 中国电子科技集团公司第二十九研究所 一种双层堆叠气密封装结构及方法
CN107768323B (zh) * 2017-11-24 2023-12-05 安徽芯动联科微系统股份有限公司 抗高过载电子器件封装管壳
CN110978751A (zh) * 2019-12-27 2020-04-10 青岛歌尔微电子研究院有限公司 一种刷锡膏模具及锡膏印刷工艺
CN112768421B (zh) * 2020-12-14 2022-06-10 苏州浪潮智能科技有限公司 一种芯片装置、pcb板及电子设备
CN114498198B (zh) * 2022-02-28 2023-07-25 苏州浪潮智能科技有限公司 一种信号引脚集装置
CN114664673B (zh) * 2022-05-25 2022-09-02 武汉敏声新技术有限公司 一种射频模组封装结构及方法
CN116963385B (zh) * 2023-09-21 2023-11-24 荣耀终端有限公司 电路板组件和终端设备
CN117289411A (zh) * 2023-10-09 2023-12-26 四川泰瑞创通讯技术股份有限公司 优化emi屏蔽性能的光电转换器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001244508A (ja) * 2000-02-25 2001-09-07 Bunkyo So 表面実装ledのパッケージおよびその製造方法
CN101150123A (zh) * 2007-10-31 2008-03-26 日月光半导体制造股份有限公司 具有电磁屏蔽罩盖的半导体封装结构

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535719B2 (en) * 1999-08-04 2009-05-19 Super Talent Electronics, Inc. Single chip USB packages with contact-pins cover
DE10127009A1 (de) * 2001-06-05 2002-12-12 Infineon Technologies Ag Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform
US20020190353A1 (en) * 2001-06-19 2002-12-19 Jyh-Sheng Pan Plastic package structure for communication component
JP3632960B2 (ja) * 2001-11-27 2005-03-30 京セラ株式会社 半導体装置
JP2003249607A (ja) * 2002-02-26 2003-09-05 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
TW200411871A (en) * 2002-12-30 2004-07-01 Advanced Semiconductor Eng Thermal-enhance package and manufacturing method thereof
WO2004077560A1 (ja) * 2003-02-26 2004-09-10 Ibiden Co., Ltd. 多層プリント配線板
DE10350239A1 (de) * 2003-10-27 2005-06-16 Infineon Technologies Ag Halbleiterbauteil mit Gehäusekunststoffmasse, Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung desselben
US8125788B2 (en) * 2006-03-29 2012-02-28 Kyocera Corporation Circuit module and radio communications equipment, and method for manufacturing circuit module
US20080067650A1 (en) * 2006-09-15 2008-03-20 Hong Kong Applied Science and Technology Research Institute Company Limited Electronic component package with EMI shielding
US20090315156A1 (en) * 2008-06-20 2009-12-24 Harper Peter R Packaged integrated circuit having conformal electromagnetic shields and methods to form the same
TW201013881A (en) * 2008-09-10 2010-04-01 Renesas Tech Corp Semiconductor device and method for manufacturing same
JP2010205869A (ja) * 2009-03-03 2010-09-16 Sae Magnetics (Hk) Ltd 電子回路モジュールの製造方法
JP2011171436A (ja) * 2010-02-17 2011-09-01 Tdk Corp 電子部品内蔵モジュール及び電子部品内蔵モジュールの製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001244508A (ja) * 2000-02-25 2001-09-07 Bunkyo So 表面実装ledのパッケージおよびその製造方法
CN101150123A (zh) * 2007-10-31 2008-03-26 日月光半导体制造股份有限公司 具有电磁屏蔽罩盖的半导体封装结构

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2602819A4 *

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