WO2021195903A1 - 系统级封装及电子设备 - Google Patents

系统级封装及电子设备 Download PDF

Info

Publication number
WO2021195903A1
WO2021195903A1 PCT/CN2020/082230 CN2020082230W WO2021195903A1 WO 2021195903 A1 WO2021195903 A1 WO 2021195903A1 CN 2020082230 W CN2020082230 W CN 2020082230W WO 2021195903 A1 WO2021195903 A1 WO 2021195903A1
Authority
WO
WIPO (PCT)
Prior art keywords
heat dissipation
electronic device
substrate
package
heat
Prior art date
Application number
PCT/CN2020/082230
Other languages
English (en)
French (fr)
Inventor
张啸诚
沈彦旭
衡草飞
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/082230 priority Critical patent/WO2021195903A1/zh
Priority to CN202080093295.5A priority patent/CN114981963A/zh
Publication of WO2021195903A1 publication Critical patent/WO2021195903A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a system-in-package and electronic equipment.
  • a single packaging process is used to make SIP packages.
  • the high-power chips are placed on the top surface of the SIP package.
  • a heat sink is provided on the top of the SIP package corresponding to the high-power chips to ensure the heat dissipation of the high-power chips.
  • Other electronic devices with a certain thickness are arranged on the bottom of the package, so that the high-power chip must be electrically connected to the printed circuit board underneath through a long copper pillar.
  • the production cost of the SIP package is high; on the other hand, A large parasitic impedance is generated between the high-power chip and the printed circuit board, which adversely affects the electrical performance of the high-power chip (or even the entire SIP package).
  • the present application provides a system-in-package and electronic equipment, which can improve the electrical performance of the high-power device and reduce the manufacturing cost of the system-in-package on the basis of ensuring the effective heat dissipation of the high-power device in the system-in-package.
  • the embodiment of the application provides a system-in-package, including: a substrate, a heat sink, a first electronic device, and a second electronic device; the heat sink, the first electronic device, and the second electronic device are molded in a molding compound The first electronic device and the second electronic device are arranged on one side of the substrate and connected to the substrate; the heat sink includes a heat sink and a heat sink extending from the side of the heat sink Extension; the heat dissipation block is pasted on the surface of the first electronic device on the side away from the substrate through a thermally conductive glue.
  • the heat sink (including the heat sink and the heat dissipation extension) is plastic-encapsulated on the upper surface of the high-power first electronic device to ensure that the first electronic device effectively dissipates the heat upward.
  • all electronic devices (including the first electronic device and the second electronic device) are arranged on the upper surface of the substrate, so as to ensure that the lower surface of the substrate can be directly connected to the PCB through a shorter connector, thereby reducing
  • the parasitic impedance between the first electronic device and the PCB improves the electrical performance of the first electronic device.
  • the SIP package of the present application is easier to implement a strip packaging process; during production, a plurality of heat dissipation blocks can be connected to form a heat dissipation strip by a heat dissipation extension, and the heat dissipation strip can be pasted on a plurality of first electronic devices.
  • the upper surface is not prone to misalignment, the process requirements for manufacturing accuracy are reduced; at the same time, the preparation of multiple SIP packages can be completed through a single manufacturing process, which reduces the manufacturing cost of SIP packages.
  • the surface of the heat dissipation block and the heat dissipation extension part away from the substrate exposes the molding compound; in order to improve the heat dissipation effect of the heat sink, and effectively reduce the heat of the first electronic device Conduct out.
  • the first electronic device is a chip.
  • the heat dissipation block and the surface of the heat dissipation extension portion away from the substrate are flush; the thickness of the heat dissipation extension portion is smaller than the thickness of the heat dissipation block.
  • the heat dissipation extension portion includes a plurality of strip-shaped structures extending from the side surface of the heat dissipation block.
  • the heat dissipation extension portion includes a planar structure extending from the side surface of the heat dissipation block to the periphery.
  • the heat dissipation block overlaps with the orthographic projection of the first electronic device on the substrate to take into account both the size of the SIP package and the heat dissipation effect of the first electronic device.
  • a power line and a ground line are provided in the substrate; the first electronic device is connected to the power line and/or the ground line through a thermally conductive hole in the substrate.
  • the heat dissipation effect of the first electronic device is further improved; on the other hand, additional manufacturing processes can be avoided and the manufacturing cost can be reduced.
  • the material of the heat sink device includes copper to ensure effective heat dissipation of the heat sink device.
  • the first electronic device and the substrate are connected through a connection structure; the first electronic device and the substrate are filled with fillers located around the connection structure, The filler disperses the compression stress at the contact position between the connection structure and the first electronic device, thereby achieving the purpose of protecting the first electronic device and the connection structure.
  • the filler is resin or molding compound.
  • the system-in-package is covered with a metal film on the surface of the heat sink on the side away from the substrate; or, the system-in-package is on the side and located far from the heat sink.
  • the surface of one side of the substrate is covered with a metal film.
  • the first electronic device and the second electronic device inside the SIP package are shielded by the metal thin film, so as to avoid mutual interference between the electrical signals inside the SIP package and other electrical signals.
  • An embodiment of the present application also provides an electronic device, including a printed circuit board and a system-in-package in any of the foregoing implementation manners; the system-in-package is connected to the printed circuit board.
  • An embodiment of the present application also provides a method for manufacturing a system-in-package, including: setting a substrate, the substrate including a plurality of system-in-package areas to be formed; and each system-in-package on the substrate
  • the first electronic device and the second electronic device are respectively attached to the area to be formed;
  • the heat dissipation strip is pasted on the surface of the first electronic device on the side away from the substrate through a thermally conductive adhesive; wherein, the heat dissipation strip includes: and each A heat dissipation block corresponding to the first electronic device and a heat dissipation extension part extending from the side of the heat dissipation block and connected between adjacent heat dissipation blocks;
  • the electronic device, the second electronic device and the heat sink are molded; the molded substrate is cut to form a plurality of system-in-packages.
  • the SIP package manufacturing method provided in the embodiments of the present application is adopted.
  • a strip packaging process is adopted.
  • the upper surfaces of multiple first electronic devices are not prone to misalignment, which reduces the precision of the manufacturing process; at the same time, multiple SIP packages can be manufactured through a single manufacturing process, which reduces the manufacturing cost of SIP packages; on the other hand, the manufacturing method is used to manufacture
  • the SIP package of the first electronic device with high power plastic seals the heat sink (including the heat dissipation block and the heat dissipation extension) on the upper surface of the high-power first electronic device to ensure that the first electronic device performs effective heat dissipation upwards, and all the electronic devices (including the first The electronic device and the second electronic device) are both arranged on the upper surface of the substrate, so as to ensure that the lower surface of the substrate can be directly connected to the PCB through a short connector, thereby reducing the parasitic impedance of the first electronic device and the PCB, and improving The electrical performance of the
  • the heat dissipation extension portion connected between adjacent heat dissipation blocks includes a plurality of strip-shaped connection structures;
  • the molding of the second electronic device and the heat dissipation bar includes: molding the molding compound by injection molding, and the first electronic device, the second electronic device, and the heat dissipation bar are arranged on the substrate. Molding; grinding the surface of the molded molding compound on the side away from the substrate to expose the heat dissipation block and the heat dissipation extension; or, perform the molding on the surface of the molded molding compound on the side away from the substrate Grinding, exposing the heat dissipation block and removing the heat dissipation extension.
  • the heat dissipation extension portion connected between adjacent heat dissipation blocks is a planar connection structure; and the first electronic device and the first electronic device and the second device provided on the substrate are treated by a molding compound.
  • Molding the electronic device and the heat sink includes: molding the first electronic device, the second electronic device, and the heat sink provided on the substrate by injection molding. .
  • the manufacturing method of the system-in-package further includes: grinding the surface of the heat dissipation bar on the side away from the substrate, removing the heat dissipation extension part, and retaining the heat dissipation block.
  • the manufacturing method of the system-in-package further includes: a connection structure between the first electronic device and the substrate Fill the surrounding area with resin; the resin disperses the stress between the connection structure and the first electronic device, thereby protecting the first electronic device and the connection structure to a certain extent.
  • An embodiment of the present application also provides a method for manufacturing a system-in-package, including: setting a substrate, and mounting a first electronic device and a second electronic device on the upper surface of the substrate; The surface of the first electronic device on a side away from the substrate; wherein the heat sink device includes a heat dissipation block provided corresponding to the first electronic device and a heat dissipation extension extending from the side surface of the heat dissipation block; The plastic molds the first electronic device, the second electronic device, and the heat sink provided on the substrate to form a system-in-package.
  • the heat dissipation extension portion includes a plurality of strip-shaped connection structures; the heat sink device, the first electronic device, and the second electronic device provided on the substrate are treated with a molding compound.
  • the molding of the device includes: molding the first electronic device, the second electronic device and the heat sink provided on the substrate by injection molding of the molding compound; and molding The surface of the latter molding compound away from the substrate is ground to expose the heat dissipation block and the heat dissipation extension.
  • FIG. 1 is a schematic structural diagram of a SIP package provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a SIP package provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a heat sink in a SIP package provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a heat sink in a SIP package provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a SIP package provided by an embodiment of the application.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a SIP package according to an embodiment of the application
  • FIG. 7 is a schematic structural diagram of a SIP package in the manufacturing process according to an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a SIP package in the manufacturing process according to an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a heat sink used in the manufacturing process of a SIP package provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a heat sink used in the manufacturing process of a SIP package provided by an embodiment of the application;
  • FIG. 11 is a schematic structural diagram of a heat sink used in the manufacturing process of a SIP package provided by an embodiment of the application;
  • FIG. 12 is a schematic structural diagram of a SIP package in the manufacturing process according to an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of a SIP package in the manufacturing process provided by an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of a SIP package in the manufacturing process according to an embodiment of the application.
  • FIG. 15 is a flowchart of a method for manufacturing SIP encapsulation according to an embodiment of the application.
  • FIG. 16 is a schematic structural diagram of a SIP package in the manufacturing process provided by an embodiment of the application.
  • the embodiment of the present application provides an electronic device.
  • the electronic device can be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet and other electronic products.
  • the embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic device.
  • the electronic device includes a printed circuit board (PCB) and a system-in-package (hereinafter referred to as SIP package) connected to the printed circuit board.
  • PCB printed circuit board
  • SIP package system-in-package
  • the embodiments of the present application provide a SIP package.
  • the SIP package includes a high-power electronic device, and the high-power electronic device may be a high-power die.
  • Using the SIP package of the present application can reduce the parasitic impedance between the high-power electronic device and the PCB on the basis of ensuring the effective heat dissipation of the high-power electronic device, so that the high-power electronic device has better electrical performance; at the same time, the production cost of the SIP package can be reduced .
  • the SIP encapsulation provided by the embodiments of the present application will be further explained below.
  • the SIP package of the present application includes: a substrate 1, a heat sink device 5, a first electronic device (such as a high-power first chip 3), and a second electronic device 4; among them, the heat sink device 5, the first electronic device Both the device and the second electronic device 4 are plastic-encapsulated in the molding compound 2.
  • the first electronic device is a high-power first chip 3 as an example.
  • the above-mentioned second electronic device 4 may include a passive device, an active device, and the like.
  • passive devices can be capacitors, inductors, etc.
  • active devices can be low-power chips, processors, memories, etc.
  • the aforementioned heat sink device 5 includes a heat dissipation block 50 and a heat dissipation extension portion 51 extending from the side surface of the heat dissipation block 50; that is, the heat dissipation extension portion 51 and the heat dissipation block 50 form an integral structure.
  • the first chip 3 and the second electronic device 4 are both connected to the upper surface of the substrate 1, and the heat dissipation block 50 is pasted on the upper surface of the first chip 3 through the thermally conductive glue 6.
  • first chip 3 and second electronic device 4 it can be understood that the lower surfaces of the first chip 3 and the second electronic device 4 are active surfaces, thereby realizing the first chip 3 and the second electronic device 4
  • the lower surface of the substrate 1 is electrically connected to the upper surface of the substrate 1.
  • the first chip 3 and the second electronic device 4 can be mounted on the substrate 1.
  • the upper surface of the first chip 3 is a non-active surface, that is, the heat dissipation block 50 is pasted on the non-active surface of the first chip 3 through the thermally conductive glue 6, thereby forming an upward heat dissipation channel above the first chip 3, through The heat dissipation block 50 and the heat dissipation extension 51 effectively conduct the heat of the first chip.
  • the upper surface of the heat dissipation block 50 and the heat dissipation extension 51 may be provided to expose the molding compound 2 so as to effectively remove the first heat sink from the heat sink. The heat of a chip is conducted away.
  • the arrangement of the heat dissipation extension 51 is equivalent to increasing the heat dissipation area and improving the heat dissipation effect of the first chip 3; on the other hand, during the manufacturing process of the SIP package, a plurality of heat dissipation blocks 50 pass through The heat dissipating extensions 51 are connected to form a heat dissipating strip.
  • the substrate 1 it can be understood that in the SIP package of the present application, the first chip 3 and the second electronic device 4 are both arranged on the upper surface of the substrate 1.
  • the lower surface of the substrate 1 can be It is directly connected to the PCB through a short connector, thereby avoiding the need to set a long copper pillar on the lower surface of the substrate 1 to connect to the PCB in the related art, which causes a large parasitic between the first chip 3 and the PCB.
  • the impedance problem improves the electrical performance of the first chip.
  • the substrate 1 may be electrically connected to the PCB through solder balls, solder tips, bumps and other connectors 7 provided on the lower surface.
  • the thermally conductive adhesive 6 can generally be a thermal interface material (thermal interface material, TIM), which has the functions of fixed bonding and heat conduction, so that the heat sink 50 is pasted on the first chip 3 through the thermally conductive adhesive 6 Behind the surface, the heat dissipation effect of the upward heat dissipation channel of the first chip can be effectively ensured.
  • thermal interface material thermal interface material, TIM
  • the heat sink (including the heat sink and the heat dissipation extension) is plastic-encapsulated on the upper surface of the high-power first electronic device (the first chip) to ensure that the first electronic device While performing effective heat dissipation upwards, all electronic devices (including the first electronic device and the second electronic device) are arranged on the upper surface of the substrate, so as to ensure that the lower surface of the substrate can be directly connected to the PCB through a short connector.
  • the connection further reduces the parasitic impedance between the first electronic device and the PCB, and improves the electrical performance of the first electronic device.
  • the SIP package of the present application is easier to implement a strip packaging process; a plurality of heat dissipation blocks can be connected by a heat dissipation extension to form a heat dissipation strip, and it is not easy to paste the heat dissipation strip onto the upper surface of a plurality of first electronic devices. Dislocation occurs, which reduces the process requirements for manufacturing accuracy; at the same time, multiple SIP packages can be manufactured through a single manufacturing process, which reduces manufacturing costs.
  • the lower surface of the first chip 3 can be configured to pass through
  • the heat conducting holes H in the substrate 1 are connected to the heat dissipation traces, thereby forming a downward heat dissipation channel under the first chip, which further improves the heat dissipation effect of the first chip.
  • the above-mentioned heat conducting hole H generally adopts the form of stacked holes, which is more conducive to heat dissipation while ensuring the effective connection between the first chip 3 and the heat dissipation traces in the substrate 1.
  • heat dissipation traces may be separately provided for the first chip 3 in the substrate 1 for heat dissipation.
  • the power line and/or ground line in the substrate 1 can be used as heat dissipation traces, and connected to the first chip 3 through the thermally conductive holes H, so as to realize the transmission of related electrical signals and to the first chip 3 at the same time.
  • a chip 3 provides a downward heat dissipation channel.
  • the power line and ground line are indispensable wiring in the substrate 1, and the power line and ground line generally use a large and complete metal layer (such as a copper layer), which has relatively strong heat dissipation capacity; Based on this, in the case of using the power line and/or the ground line as the heat dissipation trace, on the one hand, it is possible to avoid adding additional processes to make the heat dissipation trace; on the other hand, it can effectively ensure the downward heat dissipation effect of the first chip.
  • the "and/or” in this application is used to describe the association relationship of the associated objects, indicating that there can be three types of relationships.
  • “A and/or B” can mean that there is only A, only B, and There are three cases of A and B at the same time, where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an "or” relationship.
  • the power line and/or ground line in the substrate 1 as a heat dissipation trace it can mean that the power line in the substrate 1 is used as a heat dissipation trace, or it can mean that the ground wire in the substrate 1 is used as a heat dissipation trace.
  • Line can also mean that both the power line and the ground line in the substrate 1 are used as heat dissipation traces.
  • the specific arrangement of the heat sink 5 (that is, the heat dissipation channel upward from the first chip 3) of the present application will be further described below.
  • the heat sink 5 may be mainly formed of copper material, and the heat dissipation block 50 is a copper pillar to ensure effective heat dissipation effect.
  • the present application is not limited to this.
  • the heat sink 5 may also be mainly formed of aluminum, and the heat sink 50 is an aluminum column.
  • the heat dissipation block 50 can be set to coincide with the orthographic projection of the first chip 3 on the substrate 1; that is, the shape and size of the heat dissipation block 50 and the first chip 3 are basically the same, and the heat dissipation The block 50 just covers the upper surface of the first chip 3, that is, the edges of the two are substantially flush, so as to ensure effective heat dissipation of the first chip 3.
  • the edge of the heat sink 50 exceeds the first chip 3 too much, the distance between the first chip 3 and the surrounding second electronic device 4 needs to be increased, which will increase the area of the SIP package. If the edge of the first chip 3 exceeds the heat dissipation block 50 too much, that is, the heat dissipation block 50 is relatively too small, which is not conducive to the heat dissipation of the first chip 3. Therefore, in practice, in order to take into account the size of the SIP package and the heat dissipation effect of the first chip 3, the heat dissipation block 50 can be arranged flush with the edge of the first chip 3 (that is, the heat dissipation block 50 and the first chip 3 are aligned on the substrate 1). Projection coincides).
  • the area difference between the heat sink 50 and the first chip 3 can also be adjusted according to requirements to balance the heat dissipation of the first chip and the limitation of occupying the position of the second electronic device.
  • the upper surface of the heat dissipation extension 51 is flush with the upper surface of the heat dissipation block 50, and the thickness of the heat dissipation extension 51 is less than the thickness of the heat dissipation block 50; that is, the lower surface of the heat dissipation block 50 It further protrudes from the lower surface of the heat dissipation extension 51, so as to ensure that the lower surface of the heat dissipation extension 51 is located above the second electronic device 4 around the first chip 3, thereby ensuring that the heat dissipation extension 51 and the second electronic device 4 They are separated by molding compound 2.
  • the heat dissipation extension portion 51 may include a plurality of strip structures extending from the side surface of the heat dissipation block 50.
  • the heat dissipation extension portion 51 may include a planar structure extending from the side surface of the heat dissipation block 50 to the periphery.
  • the first chip 3 The periphery of the connecting structure 31 between the lower surface of the substrate 1 and the upper surface of the substrate 1 is filled with fillers 32 to protect the first chip and the connecting structure to a certain extent.
  • the filler 32 filled around the connecting structure 31 may be resin; in some possible implementation manners, the filler 32 filled around the connecting structure 31 may be a molding compound.
  • the lower surface (that is, the active surface) of the first chip 3 is usually provided with a plurality of pads, and the first chip 3 is provided with a connection structure 31 at the position of the pads.
  • bumps are electrically connected to the substrate 1.
  • the lower surface of the first chip 1 is in the area other than the pads, and the dielectric layer material matching the process node is often used to form an extra low-k, ELK or low-k Dielectric layer (Low-k, LK), the dielectric layer has low strength and is easily damaged under pressure.
  • Fillers 32 are filled around the connection structure 31 to disperse the compression stress at the contact position between the connection structure and the first chip by the filler, thereby achieving the purpose of protecting the first chip and the connection structure.
  • the SIP package when used in electronic equipment, in order to avoid the electrical signal generated by the electronic device (including the first electronic device and the second electronic device) inside the SIP package and the electrical signal generated by other electronic devices in the electronic device
  • the sides of the SIP package and the upper surface of the SIP package on the side of the heat sink 50 away from the substrate 1 can be covered with a metal film, so as to shield the electronic devices inside the SIP package through the metal film. Function to avoid mutual interference between the electrical signals inside the SIP package and other electrical signals.
  • both can be completed by one manufacturing process or two manufacturing processes. In practice, it can be based on The production method of SIP package is selected.
  • the SIP package when the SIP package is manufactured using a separate packaging process, a single manufacturing process can be used to simultaneously complete the production of the metal film on the side and upper surface of the SIP package.
  • a metal film can be made on the upper surface of the entire package before the cutting process, and after the cutting process, a single SIP The side surface of the package is separately fabricated with a metal film.
  • the heat dissipation block 50 and the heat dissipation extension 51 are entirely covered on the upper surface of the SIP package.
  • the heat sink device 5 itself can achieve a shielding effect while achieving a heat dissipation effect; in this case, it is not necessary to fabricate a metal film on the upper surface of the SIP package, but only fabricate a metal film on the side of the SIP package.
  • FIGS. 1 and 2 are only schematic illustrations with a first chip 3 provided in the SIP package as an example, but the application is not limited to this, and in some possible implementation manners
  • multiple first chips 3 ie, multiple first electronic devices
  • a heat dissipation channel is provided for each first chip 3 respectively.
  • two first chips 3 may be provided in the SIP package, and upper and lower heat dissipation channels are respectively provided for the two first chips 3; but it is not limited to this.
  • the second electronic device 4 can be one or more; this application does not make any special restrictions on this; in practice, the first electronic device and the second electronic device can be selected and set according to needs. number.
  • the following describes the manufacturing method of the SIP package provided in the embodiments of the present application using a strip packaging process.
  • an embodiment of the present application provides a method for manufacturing a SIP package, including:
  • Step 101 As shown in FIG. 7, a substrate (strip) 11 is set, and the substrate includes a plurality of SIP packages to be formed regions; and a first strip is attached to each of the SIP packages to be formed regions on the upper surface of the substrate 11.
  • Electronic devices for example, the first chip 3) and the second electronic device 4.
  • FIG. 7 only illustrates a part of the area to be formed corresponding to a single SIP package, and the following descriptions are made on this basis.
  • the passive device For mounting the first electronic device (for example, the first chip 3) and the second electronic device 4 (for example, passive devices) in the area to be formed of each SIP package on the upper surface of the substrate 11, it is possible to implement In this manner, the passive device may be mounted on the corresponding position on the upper surface of the substrate 11 by surface mounting technology (SMT) first, and the passive device may be connected to the substrate 11 by reflow. Then, flip the active surface of the first chip 3 to a corresponding position on the substrate 11, and melt the bumps on the lower surface of the first chip 3 through reflow. , To ensure the formation of electrical interconnection between the first chip 3 and the substrate 11, and then remove the residual flux.
  • SMT surface mounting technology
  • first chip 3 it is also possible to mount the first chip 3 first, and then mount the passive devices.
  • This application does not specifically limit this. It can be made according to process requirements, as long as the first chip and passive devices are on the substrate. The electrical connection on the surface is sufficient.
  • a thermally conductive hole H can be formed at the position corresponding to the first chip 3, and the thermally conductive hole H and the power supply in the substrate 11 may be formed.
  • the wire and/or the ground wire are connected, so as to provide the first chip 3 with a downward heat conduction channel to ensure that the heat generated by the first chip 3 is conducted through the power wire and/or the ground wire.
  • Step 102 As shown in FIG. 8, the heat dissipation strip T is attached to the upper surface of the first chip 3 (first electronic device) through the thermal conductive glue 6 (lid attach).
  • the heat dissipation strip T includes: a heat dissipation block 50 corresponding to each first chip 3 and a heat dissipation extension portion connected between adjacent heat dissipation blocks 50 51. It can be understood here that the heat sink 50 of the heat sink T corresponding to each area where the SIP package is to be formed and the heat dissipation extension 51 extending from the side of the heat sink 50 serve as the heat sink 5 of the SIP package subsequently formed in this area. .
  • the upper surface of the heat dissipation extension portion 51 is flush with the upper surface of the heat dissipation block 50, and the thickness of the heat dissipation extension portion 51 is less than the thickness of the heat dissipation block 50, that is, the heat dissipation strip T is pasted on the first chip
  • the lower surface of the heat dissipation extension 51 is higher than the upper surface of the first chip 3 to ensure that there is a gap between the heat dissipation extension 51 and the upper surface of the second electronic device 4 located around the first chip 3. The two do not touch.
  • the heat sink T and the aforementioned substrate 11 are both provided for a plurality of SIP packages to be formed.
  • the heat sink T may be a stamped and formed integral structure; for example, the heat sink T may be a punched copper lid frame; during the pasting process of the heat sink T, The integrally formed heat sink T is not prone to misalignment, and the manufacturing cost is low.
  • the heat dissipation extension 51 serves as a connection structure connected between the plurality of heat dissipation blocks 50 and forms a connection frame between all the heat dissipation blocks 50.
  • the connection frame may be a hollow connection frame or a planar connection frame, and the specific form of the connection frame is not particularly limited in this application.
  • a plurality of strip structures extending from the side surface of the heat dissipation block 50 are connected to form a hollow connection frame.
  • a plurality of strip structures extending from the side of the heat dissipation block 50 are connected to the grid structure, and the strip structure and the grid structure together form a hollow connection frame.
  • the planar structure extending from the periphery of the heat dissipation block 50 forms a planar connection frame; in this case, the upper surface of the heat sink T forms a planar structure as a whole.
  • Step 103 As shown in FIG. 12, the first chip 3 (first electronic device), the second electronic device 4, and the heat sink T provided on the substrate 11 are molded by using a molding compound.
  • a suitable molding process can generally be selected according to actual requirements.
  • the above step 103 may include: adopting compression molding of the molding compound to set the substrate 11
  • the first chip 3, the second electronic device 4, and the heat sink T are molded; that is, the fluid-like molding compound is poured from top to bottom through the hollow area of the connection frame, so that the first chip, the second electronic device, and the heat sink are poured.
  • the strip and the substrate are sealed together by molding compound to protect the SIP package.
  • the upper surface of the heat sink T will be covered with a layer of molding compound.
  • the upper surface of the molding compound can be processed by a grinding process (grinding). Grind, remove excess molding compound, and expose the heat dissipation block 50 and the heat dissipation extension 51 (refer to FIG. 12).
  • the heat sink device 5 only includes the heat dissipation block 50.
  • the above-mentioned step 103 may include: using transfer molding of the molding compound to perform transfer molding to the first chip disposed on the substrate 11. 3.
  • the heat sink T is molded; that is, the fluid-like molding compound flows and fills laterally through the side area between the heat sink T and the substrate 1, so that the first chip, the second electronic device, and the heat sink are filled.
  • the strip and the substrate are sealed together by molding compound to protect the SIP package.
  • the heat dissipation strip T with a planar connection frame is used. Since the molding compound is injected from the side, the upper surface of the heat dissipation strip T has almost no molding compound. Therefore, after the heat dissipation strip T is molded by injection molding, the heat dissipation strip T can be molded. The upper surface is not polished (refer to FIG. 12), or is properly polished, leaving the heat dissipation block 50 and the heat dissipation extension 51.
  • the upper surface of the heat dissipation strip T can also be deeply ground, the heat dissipation extension 51 is removed, and the heat dissipation block 50 is retained (refer to FIG. 13).
  • the molded substrate 11 can be turned over (that is, the back side of the substrate 11 is facing upward), and the pad located on the back of the substrate 11 can be removed by flux.
  • the oxide film on the surface is ball-planted and reflowed, and solder balls are mounted on the back of the substrate 11; so that the subsequently formed SIP package can be electrically connected to the PCB through the solder balls.
  • Step 104 using a dicing process to cut the molded substrate 11 to form a plurality of independent SIP packages (refer to FIG. 2).
  • the SIP package manufacturing method provided in the embodiments of the present application is adopted.
  • a strip packaging process is adopted.
  • the upper surface of the multiple first electronic devices is not prone to misalignment, which reduces the precision of the manufacturing process; at the same time, multiple SIP packages can be manufactured through a single manufacturing process, which reduces the manufacturing cost; on the other hand, the SIP package manufactured by this manufacturing method ,
  • plastic-encapsulating the heat sink (including the heat sink and the heat dissipation extension) on the upper surface of the high-power first electronic device (the first chip) to ensure that the first electronic device performs effective heat dissipation upwards
  • all the electronic devices including the The first electronic device and the second electronic device
  • are both arranged on the upper surface of the substrate so as to ensure that the lower surface of the substrate can be directly connected to the PCB through a short connector, thereby reducing the parasitic impedance of the first electronic device and the PCB , Improve the electrical performance of the first electronic device.
  • the following describes the manufacturing method of the SIP package provided in the embodiment of the present application using a separate packaging process.
  • an embodiment of the present application provides a method for manufacturing a SIP package, including:
  • Step 201 referring to FIG. 3, a substrate 1 is set, and a first electronic device (such as a first chip 3) and a second electronic device 4 are mounted on the upper surface of the substrate 1.
  • a first electronic device such as a first chip 3
  • a second electronic device 4 are mounted on the upper surface of the substrate 1.
  • step 101 The difference from step 101 is that the substrate 1, the first electronic device, and the second electronic device in step 201 are for a single SIP package, and the related mounting process is basically the same. You can refer to the related content of step 101, which will not be repeated here.
  • Step 202 referring to FIG. 3, the heat sink 5 is pasted on the upper surface of the first electronic device through the thermally conductive glue 6.
  • the heat sink device 5 includes a heat dissipation block 50 and a heat dissipation extension 51 extending from the side surface of the heat dissipation block 50.
  • the heat sink 5 in this step 202 corresponds to only one SIP package, and the mounting process is basically the same as that of the foregoing step 102. You can refer to The relevant content in the foregoing step 102 will not be repeated here.
  • Step 203 Use molding compound to mold the first chip 3, the second electronic device 4, and the heat sink 5 arranged on the substrate 1 to form a system-in-package.
  • step 203 For other related content of this step 203, reference may be made to the aforementioned step 103, which will not be repeated here.
  • step 203 the selection of the molding method in step 203 can be set according to the structure of the heat sink 5 used.
  • step 203 may include: using compression molding of the molding compound to treat the first chip 3 and the second chip 3 on the substrate 1 Second, the electronic device 4 and the heat sink 5 are molded; and after the step 203, a step 204 is further included: grinding the upper surface of the molded plastic to expose the heat dissipation block 50 and the heat dissipation extension 51.
  • step 204 For other related content of step 204, refer to the aforementioned step 104, which will not be repeated here.
  • the first chip 3 After being mounted on the substrate 1 (or the substrate 11), as shown in FIG. 16, the resin can be filled around the connection structure 31 between the first chip 3 and the substrate 1 through an underfill process, and the resin is dispersed The stress between the connection structure 31 and the first chip 3 can protect the first chip 3 and the connection structure 31 to a certain extent.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种系统级封装及电子设备，能够在保证系统级封装中的大功率器件有效散热的基础上，提高大功率器件的电学性能，降低系统级封装的制作成本。该系统级封装包括基板（1）、散热器件（5）、第一电子器件（3）及第二电子器件（4）；散热器件（5）、第一电子器件（3）、第二电子器件（4）塑封在模塑料（2）中；第一电子器件（3）和第二电子器件（4）设置在基板（1）的一侧、并与基板（1）连接；散热器件（5）包括散热块（50）以及从散热块（50）的侧面延伸出的散热延伸部（51）；散热块（50）通过导热胶（6）粘贴在第一电子器件（3）远离基板（1）一侧的表面。

Description

系统级封装及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种系统级封装及电子设备。
背景技术
随着系统级封装(英文全称：system in package；英文缩写SIP；也可以简称为SIP封装)技术的发展，SIP封装产品的组装密度越来越高，大功率芯片在SIP封装产品中的应用越来越广泛，使得SIP封装单位面积上的功耗显著增加，导致SIP封装产生的热量增加，因此，对SIP封装进行可靠、有效的散热设计是大功率SIP封装类产品必须解决的问题。
相关技术中采用单个封装工艺制作SIP封装，将大功率芯片设置在SIP封装的顶面，通过在SIP封装的顶部对应大功率芯片的位置单独设置散热器件，来保证大功率芯片的散热；由于SIP封装的底部设置具有一定厚度的其他电子器件，从而导致大功率芯片必须通过较长的铜柱与位于下方的印刷线路板实现电气连接，一方面，导致SIP封装的制作成本高；另一方面，大功率芯片与印刷线路板之间产生会较大的寄生阻抗，对大功率芯片(甚至整个SIP封装)的电学性能造成不良影响。
发明内容
本申请提供一种系统级封装及电子设备，能够在保证系统级封装中的大功率器件有效散热的基础上，提高大功率器件的电学性能，降低系统级封装的制作成本。
本申请实施例提供一种系统级封装，包括：基板、散热器件、第一电子器件及第二电子器件；所述散热器件、所述第一电子器件、所述第二电子器件塑封在模塑料中；所述第一电子器件和所述第二电子器件设置在所述基板的一侧、并与所述基板连接；所述散热器件包括散热块以及从所述散热块的侧面延伸出的散热延伸部；所述散热块通过导热胶粘贴在所述第一电子器件远离所述基板一侧的表面。
综上所述，一方面，在本申请SIP封装中，通过在大功率的第一电子器件的上表面塑封散热器件(包括散热块和散热延伸部)来保证第一电子器件向上进行有效散热的同时，将所有的电子器件(包括第一电子器件和第二电子器件)均设置于基板的上表面，从而能够保证基板的下表面可以直接通过较短的连接件直接与PCB连接，进而降低了第一电子器件与PCB的寄生阻抗，提高了第一电子器件的电学性能。另一方面，本申请SIP封装更易于实现条形封装工艺(strip)；在制作时能够利用散热延伸部将多个散热块连接起来形成散热条，将散热条粘贴在多个第一电子器件的上表面，不易发生错位时，降低了制作精度的工艺要求；同时通过一次制作工艺可以完成多个SIP封装的制备，降低了SIP封装的制作成本。
在一些可能实现的方式中，所述散热块和所述散热延伸部远离所述基板一侧的表面裸露出所述模塑料；以提高散热器件的散热效果，有效的将第一电子器件的热量传导出去。
在一些可能实现的方式中，所述第一电子器件为芯片。
在一些可能实现的方式中，所述散热块和所述散热延伸部远离所述基板一侧的表 面平齐；所述散热延伸部的厚度小于所述散热块的厚度。
在一些可能实现的方式中，所述散热延伸部包括从所述散热块的侧面延伸出的多个条状结构。
在一些可能实现的方式中，所述散热延伸部包括从所述散热块的侧面向四周延伸的面状结构。
在一些可能实现的方式中，所述散热块与所述第一电子器件在所述基板上的正投影重合；以兼顾SIP封装的尺寸以及第一电子器件的散热效果。
在一些可能实现的方式中，所述基板中设置有电源线、接地线；所述第一电子器件通过位于所述基板中的导热孔与所述电源线和/或所述接地线连接。在此情况下，一方面，通过在第一电子器件的下方形成向下的散热通道，进一步的改善第一电子器件的散热效果；另一方面，能够避免额外增加工艺制作，降低制作成本。
在一些可能实现的方式中，所述散热器件的材质包括铜，以保证散热器件的有效散热。
在一些可能实现的方式中，所述第一电子器件与所述基板之间通过连接结构连接；所述第一电子器件与所述基板之间在位于所述连接结构的四周填充有填充物，通过填充物分散连接结构与第一电子器件接触位置的挤压应力，进而达到保护第一电子器件和连接结构的目的。
在一些可能实现的方式中，所述填充物为树脂或模塑料。
在一些可能实现的方式中，所述系统级封装在位于所述散热块远离所述基板的一侧的表面覆盖有金属薄膜；或者，所述系统级封装在侧面以及位于所述散热块远离所述基板的一侧的表面均覆盖有金属薄膜。在此情况下，通过金属薄膜对SIP封装内部的第一电子器件和第二电子器件起到屏蔽作用，避免SIP封装内部的电信号与其他电信号之间的相互干扰。
本申请实施例还提供一种电子设备，包括印刷线路板以及如前述任一种实现方式中的系统级封装；所述系统级封装与所述印刷线路板连接。
本申请实施例还提供一种系统级封装的制作方法，包括：设置基板，所述基板上包括多个系统级封装的待形成区域；并在所述基板上的每一所述系统级封装的待形成区域分别贴装第一电子器件及第二电子器件；将散热条通过导热胶粘贴在所述第一电子器件远离所述基板一侧的表面；其中，所述散热条包括：与每一所述第一电子器件对应的散热块以及从所述散热块的侧面延伸出、且连接在相邻散热块之间的散热延伸部；采用模塑料对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑；对模塑后的基板进行切割形成多个系统级封装。
综上所述，采用本申请实施例提供的SIP封装的制作方法，一方面，采用条形封装工艺(strip)，多个散热块通过散热延伸部连接起来形成散热条，将散热条贴附在多个第一电子器件上表面，不易发生错位，降低了制作工艺精度；同时通过一次制作工艺可以完成多个SIP封装的制备，降低了SIP封装的制作成本；另一方面，采用该制作方法制作的SIP封装，通过在大功率的第一电子器件的上表面塑封散热器件(包括散热块和散热延伸部)来保证第一电子器件向上进行有效散热的同时，将所有的电子器件(包括第一电子器件和第二电子器件)均设置于基板的上表面，从而能够保证 基板的下表面可以直接通过较短的连接件直接与PCB连接，进而降低了第一电子器件与PCB的寄生阻抗，提高了第一电子器件的电学性能。
在一些可能实现的方式中，所述连接在相邻散热块之间的散热延伸部包括多个条状连接结构；所述采用模塑料对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑包括：将模塑料采用压注成型的方式，对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑；对模塑后的模塑料远离所述基板一侧的表面进行研磨，以暴露出散热块和散热延伸部；或者，对模塑后的模塑料远离所述基板一侧的表面进行研磨，暴露出所述散热块并去除所述散热延伸部。
在一些可能实现的方式中，所述连接在相邻散热块之间的散热延伸部为面状连接结构；所述采用模塑料对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑包括：将模塑料采用注塑成型的方式，对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑。
在一些可能实现的方式中，在所述将模塑料采用注塑成型的方式，对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑之后，所述系统级封装的制作方法还包括：对所述散热条远离所述基板一侧的表面进行研磨，去除所述散热延伸部，保留所述散热块。
在一些可能实现的方式中，在所述基板的上表面贴装第一电子器件之后，所述系统级封装的制作方法还包括：在所述第一电子器件与所述基板之间的连接结构的四周填充树脂；通过树脂分散连接结构和第一电子器件之间的应力，从而对第一电子器件和连接结构起到一定的保护作用。
本申请实施例还提供一种系统级封装的制作方法，包括：设置基板，并在所述基板的上表面贴装第一电子器件及第二电子器件；将散热器件通过导热胶粘贴在所述第一电子器件远离所述基板一侧的表面；其中，所述散热器件包括与所述第一电子器件对应设置的散热块以及从所述散热块的侧面延伸出的散热延伸部；采用模塑料对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑，以形成系统级封装。
在一些可能实现的方式中，所述散热延伸部包括多个条状连接结构；所述采用模塑料对所述基板上设置的所述散热器件、所述第一电子器件和所述第二电子器件进行模塑，包括：将模塑料采用压注成型的方式，对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑；并对模塑后的模塑料远离所述基板一侧的表面进行研磨，以暴露出散热块和散热延伸部。
附图说明
图1为本申请实施例提供的一种SIP封装的结构示意图；
图2为本申请实施例提供的一种SIP封装的结构示意图；
图3为本申请实施例提供的一种SIP封装中的散热器件的示意图；
图4为本申请实施例提供的一种SIP封装中的散热器件的示意图；
图5为本申请实施例提供的一种SIP封装的结构示意图；
图6为本申请实施例提供的一种SIP封装的制作方法流程示意图；
图7为本申请实施例提供的一种SIP封装在制作过程中的结构示意图；
图8为本申请实施例提供的一种SIP封装在制作过程中的结构示意图；
图9为本申请实施例提供的一种SIP封装在制作过程中采用的散热条的结构示意图；
图10为本申请实施例提供的一种SIP封装在制作过程中采用的散热条的结构示意图；
图11为本申请实施例提供的一种SIP封装在制作过程中采用的散热条的结构示意图；
图12为本申请实施例提供的一种SIP封装在制作过程中的结构示意图；
图13为本申请实施例提供的一种SIP封装在制作过程中的结构示意图；
图14为本申请实施例提供的一种SIP封装在制作过程中的结构示意图；
图15为本申请实施例提供的一种SIP封装在制作方法流程图；
图16为本申请实施例提供的一种SIP封装在制作过程中的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备。该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环等电子产品。本申请实施例对上述电子设备的具体形式不做特殊限制。
该电子设备中包括印刷线路板(printed circuit board，PCB)以及与印刷线路板连接的系统级封装(下文简称为SIP封装)。
本申请实施例提供一种SIP封装，该SIP封装中包括大功率电子器件，该大功率电子器件可以为大功率芯片(die)。采用本申请的SIP封装能够在保证大功率电子器件的有效散热的基础，降低大功率电子器件与PCB之间的寄生阻抗，使得大功率电子器件具有较好电学性能；同时降低SIP封装的制作成本。以下对本申请实施例提供的SIP封装作进一步的说明。
如图1所示，本申请的SIP封装包括：基板1、散热器件5、第一电子器件(例如大功率的第一芯片3)以及第二电子器件4；其中，散热器件5、第一电子器件以及第二电子器件4均塑封在模塑料2中的。下文均是以第一电子器件为大功率的第一芯片3为例进行说明的。
上述第二电子器件4可以包括无源器件(passive device)、有源器件等。其中，无源器件可以为电容、电感等；有源器件可以为小功率的芯片、处理器、存储器等。
上述散热器件5包括散热块50以及从散热块50侧面延伸出的散热延伸部51；也即散热延伸部51与散热块50形成一体结构。
如图1所示，第一芯片3及第二电子器件4均与基板1的上表面连接，散热块50通过导热胶6粘贴在第一芯片3的上表面。
对于上述第一芯片3及第二电子器件4而言，可以理解的是，第一芯片3以及第二电子器件4的下表面为有源面，从而实现第一芯片3以及第二电子器件4的下表面与基板1的上表面之间电气连接。本申请中，对于第一芯片3和第二电子器件4与基板1之间的连接方式不做具体限制；例如，第一芯片3和第二电子器件4可以贴装于基板1上。
第一芯片3的上表面为非有源面，也即散热块50通过导热胶6粘贴在第一芯片3的非有源面上，从而在第一芯片3的上方形成向上的散热通道，通过散热块50和散热延伸部51有效的将第一芯片的热量传导出去。
在一些可能实现的方式中，为了提高散热器件5的散热效果，如图1所示，可以设置散热块50和散热延伸部51的上表面裸露出模塑料2，以通过散热器件有效的将第一芯片的热量传导出去。
需要说明的是，散热延伸部51的设置，一方面，相当于增加了散热面积，改善了第一芯片3的散热效果；另一方面，在SIP封装的制作过程中，多个散热块50通过散热延伸部51连接起来形成散热条，能够在采用条状(strip)封装工艺制作SIP封装时，散热条与多个第一芯片粘贴时，不易发生错位，降低了制作精度的工艺要求；同时通过一次制作工艺可以完成多个SIP封装的制备；进而降低了SIP封装的制作成本(具体可以参考后续SIP封装的制作方法的相关实施例部分)。
对于基板1而言，可以理解的是，在本申请的SIP封装中，通过将第一芯片3和第二电子器件4均设置于基板1上表面，在此情况下，基板1的下表面能够直接通过较短的连接件与PCB进行连接，从而避免了相关技术中需要在基板1的下表面设置较长的铜柱与PCB连接，而导致第一芯片3与PCB之间产生较大的寄生阻抗的问题，进而也就提高了第一芯片的电气性能。
示意的，如图1所示，基板1可以通过下表面设置的焊球(solder ball)、焊点(solder tip)、凸点(bump)等连接件7与PCB电连接。
需要说明的是，导热胶6一般可以采用热界面材料(thermal interface material，TIM)，其具有固定粘结和导热的功能，从而在通过导热胶6将散热块50粘贴在第一芯片3的上表面后，能够有效的保证第一芯片向上的散热通道的散热效果。
综上所述，一方面，在本申请SIP封装中，通过在大功率的第一电子器件(第一芯片)的上表面塑封散热器件(包括散热块和散热延伸部)来保证第一电子器件向上进行有效散热的同时，将所有的电子器件(包括第一电子器件和第二电子器件)均设置于基板的上表面，从而能够保证基板的下表面可以直接通过较短的连接件直接与PCB连接，进而降低了第一电子器件与PCB的寄生阻抗，提高了第一电子器件的电学性能。另一方面，本申请SIP封装更易于实现条形封装工艺(strip)；多个散热块 能够通过散热延伸部连接起来形成散热条，将散热条粘贴至多个第一电子器件的上表面时，不易发生错位，降低了制作精度的工艺要求；同时通过一次制作工艺可以完成多个SIP封装的制备，降低了制作成本。
在此基础上，在一些实施例中，为了进一步有效的降低第一芯片3的热阻，改善第一芯片3的散热能力，如图2所示，可以设置第一芯片3的下表面可以通过基板1中的导热孔H与散热走线连接，从而在第一芯片的下方形成向下的散热通道，进一步的改善第一芯片的散热效果。
上述导热孔H一般采用叠孔形式，在保证第一芯片3与基板1中的散热走线之间的有效连接的同时，更有利于散热。
本申请中对于上述散热走线的设置形式不做具体限制。在一些可能实现的方式中，可以在基板1中针对第一芯片3单独设置散热走线进行散热。在一些可能实现的方式中，可以将基板1中的电源线和/或接地线作为散热走线，通过导热孔H与第一芯片3连接，从而在实现相关电信号的传输的同时，向第一芯片3提供向下的散热通道。
可以理解的是，电源线、接地线作为基板1中必不可少的走线，并且电源线、接地线一般采用较大且完整的金属层(例如铜层)，具有相对较强的散热能力；基于此，在将电源线和/或接地线作为散热走线的情况下，一方面，能够避免额外增加工艺制作散热走线；另一方面，能够有效的保证第一芯片向下的散热效果。
需要说明的是，本申请中的“和/或”用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。例如，对于上述将基板1中的电源线和/或接地线作为散热走线而言，可以表示将基板1中的电源线作为散热走线，也可以表示将基板1中的接地线作为散热走线，还可以表示将基板1中的电源线和接地线均作为散热走线。
以下对本申请的散热器件5(即第一芯片3向上的散热通道)的具体设置做进一步的说明。
在一些可能实现的方式中，散热器件5可以主要采用铜材质形成，散热块50为铜柱，以保证有效的散热效果。但本申请并不限制于此，在一些可能实现的方式中，散热器件5也可以主要采用铝形成，散热块50为铝柱。
在一些可能实现的方式中，如图2所示，可以设置散热块50与第一芯片3在基板1上的正投影重合；也即散热块50与第一芯片3的形状大小基本一致，散热块50正好覆盖在第一芯片3的上表面，即两者的边缘基本平齐，以保证第一芯片3的有效散热。
可以理解的是，如果散热块50的边缘超出第一芯片3太多，就需要增加第一芯片3与周围第二电子器件4之间的距离，会造成SIP封装的面积增大。如果第一芯片3的边缘超出散热块50太多，也即散热块50相对太小，不利于第一芯片3的散热。因此，实际中为了兼顾SIP封装的尺寸以及第一芯片3的散热效果，可以设置散热块50与第一芯片3的边缘平齐(也即散热块50与第一芯片3在基板1上的正投影重合)。
当然，实际中也可以根据需求调整散热块50与第一芯片3的面积差异，来平衡 第一芯片的散热与挤占第二电子器件位置的限制。
以下对散热器件5中的散热延伸部51的具体设置形式进行说明。
在一些实施例中，如图2所示，散热延伸部51的上表面与散热块50的上表面平齐，散热延伸部51的厚度小于散热块50的厚度；也即散热块50的下表面更凸出于散热延伸部51的下表面，从而能够保证散热延伸部51的下表面位于第一芯片3四周的第二电子器件4的上方，进而能够保证散热延伸部51与第二电子器件4之间通过模塑料2隔离。
在一些可能实现的方式中，如图3所示，散热延伸部51可以包括从散热块50的侧面延伸出的多个条状结构。
在一些可能实现的方式中，如图4所示，散热延伸部51可以包括从散热块50的侧面向四周延伸的面状结构。
此处需要说明的是，针对本申请实施例提供的SIP封装而言，可以采用单独封装工艺进行制作；也可以采用条状封装工艺(strip)，通过切割的方式进行制作。当然，对于采用不同形式的散热延伸部51(条状结构或面状结构)，SIP封装的制作工艺会存在一定的区别，具体可以参考后续关于本申请的SIP封装的制作方法的实施例。
另外，考虑到将整个散热器件5整体叠放在第一芯片3的上表面，会对第一芯片3产生一定的压力，在一些可能实现的方式中，如图5所示，第一芯片3的下表面与基板1的上表面之间的连接结构31的四周填充有填充物32，以通过填充物对第一芯片和连接结构起到一定的保护作用。
示意的，在一些可能实现的方式中，连接结构31四周填充的填充物32可以为树脂；在一些可能实现的方式中，连接结构31四周填充的填充物32可以为模塑料。
此处应当理解的是，参考图5，第一芯片3的下表面(即有源面)通常设置有多个焊盘(pad)，第一芯片3通过在焊盘的位置设置连接结构31，例如凸点(bump)，与基板1实现电气连接。第一芯片1的下表面在设置焊盘(pad)以外的区域，多采用匹配工艺节点的介电层材料形成超低介电系数介电层(Extra Low-k、ELK)或低介电系数介电层(Low-k、LK)，该介电层强度较小，受压容易破损。在连接结构31的四周填充填充物32，通过填充物来分散连接结构与第一芯片在接触位置的挤压应力，进而达到保护第一芯片和连接结构的目的。
另外，在SIP封装应用在电子设备中时，为了避免SIP封装内部的电子器件(包括第一电子器件和第二电子器件)产生的电信号与电子设备中的其他电子器件产生的电信号之间互相产生影响，在一些实施例中，可以在SIP封装的侧面以及SIP封装位于散热块50远离基板1的一侧的上表面覆盖金属薄膜，从而通过金属薄膜对SIP封装内部的电子器件起到屏蔽作用，避免SIP封装内部的电信号与其他电信号之间的相互干扰。
对于上述位于SIP封装侧面的金属薄膜以及位于散热块远离基板的一侧的上表面覆盖的金属薄膜而言，两者可以通过一次制作工艺完成，也可以通过两次制作工艺完成，实际中可以根据SIP封装的制作方式选择进行。
例如，对于SIP封装采用单独封装工艺进行制作的情况下，可以采用一次制作工艺同时完成SIP封装的侧面以及上表面的金属薄膜的制作。
又例如，对于SIP封装采用条状封装工艺并通过切割的方式进行制作的情况下，可以在进行切割工艺前，在整个封装体的上表面制作金属薄膜，在进行切割工艺后，再针对单个SIP封装的侧面单独制作金属薄膜。
当然，还应当理解的是，对于前述SIP封装中，在散热器件5中的散热延伸部51采用面状结构的实施例中，散热块50和散热延伸部51整体覆盖在SIP封装的上表面，散热器件5自身在达到散热效果的同时，也可以实现屏蔽的作用；在此情况下，可以不在针对SIP封装的上表面制作金属薄膜，仅在SIP封装的侧面制作金属薄膜即可。
另外，还需要说明的是，图1、图2仅是示意的以SIP封装中设置有一个第一芯片3为例进行说明的，但本申请并不限制于此，在一些可能实现的方式中，SIP封装中也可以设置多个第一芯片3(即多个第一电子器件)，并且针对每一第一芯片3分别设置散热通道。例如，如图5所示，SIP封装中可以设置有两个第一芯片3，并针对两个第一芯片3分别设置上、下散热通道；但并不限制于此。另外，在该SIP封装中，第二电子器件4可以是一个，也可以是多个；本申请对此均不作特殊限制；实际中可以根据需要选择设置第一电子器件和第二电子器件的个数。
以下对本申请实施例中提供的SIP封装采用条状封装工艺的制作方法进行说明。
如图6所示，本申请实施例提供一种SIP封装的制作方法，包括：
步骤101、如图7所示，设置基板(strip)11，该基板上包括多个SIP封装的待形成区域；并在基板11上表面中的每一SIP封装的待形成区域分别贴装第一电子器件(例如第一芯片3)及第二电子器件4。
可以理解的是，上述基板11是针对多个SIP封装的走线基板，图7中仅示意了对应单个SIP封装的待形成区域的局部，以下均是在此基础上进行说明的。
对于在基板11的上表面中位于每一SIP封装的待形成区域贴装第一电子器件(例如第一芯片3)及第二电子器件4(例如无源器件)而言，在一些可能实现的方式中，可以先在基板11的上表面对应的位置通过表面贴装技术(surface mounting technology，SMT)贴装无源器件，并通过回流焊(reflow)将无源器件与基板11连接。然后，再将第一芯片3的有源面倒扣贴装(flip chip attach)在基板11上相应的位置，并通过回流焊(reflow)将位于第一芯片3下表面的凸点(bump)熔化，保证第一芯片3与基板11之间形成电气互连，随后清除掉残余的助焊剂即可。以下均是以第一电子器件为第一芯片3，第二电子器件4为无源器件的基础上，对该SIP封装的制作方法进行示意说明的。
当然，实际中，也可以先贴装第一芯片3，再贴装无源器件，本申请对此不作具体限定，具体可以根据工艺需求进行制作，只要保证第一芯片及无源器件与基板上表面的电气连接即可。
另外，如图7所示，在一些可能实现的方式中，在制作基板11时，可以在对应第一芯片3贴装的位置形成导热孔H，并且该设置导热孔H与基板11中的电源线和/或接地线连接，从而能够向第一芯片3提供向下的导热通道，以保证第一芯片3产生的热量通过电源线和/或接地线传导出去。
步骤102、如图8所示，将散热条T通过导热胶6粘贴(lid attach)在第一芯片3(第一电子器件)的上表面。
参考图9、图10、图11，并结合图8所示，上述散热条T中包括：与每一第一芯片3对应的散热块50以及连接在相邻散热块50之间的散热延伸部51。此处可以理解的是，散热条T在对应每一待形成SIP封装的区域中的散热块50以及从散热块50侧面延伸出的散热延伸部51作为该区域后续形成的SIP封装的散热器件5。
在一些可能实现的方式中，散热延伸部51的上表面与散热块50的上表面平齐，且散热延伸部51的厚度小于散热块50的厚度，也即在散热条T粘贴在第一芯片3的上表面后，散热延伸部51的下表面要高于第一芯片3的上表面，以保证散热延伸部51和位于第一芯片3四周的第二电子器件4的上表面留有空隙，两者不接触。
可以理解的是，上述散热条T与前述的基板11均是针对多个待形成的SIP封装设置的。在一些可能实现的方式中，该散热条T可以为冲压成型的一体结构；例如，散热条T可以为冲压成型的铜金属框架(punched copper lid frame)；在散热条T的粘贴过程中，采用一体成型的散热条T，不容易发生错位，并且制造成本低。
另外，对于散热条T而言，还可以理解的是，散热延伸部51作为连接在多个散热块50之间的连接结构，在所有的散热块50之间形成连接框架。示意的，该连接框架可以为镂空连接框架，也可以为面状连接框架，本申请对于该连接框架的具体形式不作特殊限制。
例如，如图9所示，在一些实施例中，从散热块50的侧面延伸出的多个条状结构连接形成镂空连接框架。又例如，如图10所示，在一些实施例中，从散热块50的侧面延伸出的多个条状结构连接到网格结构上，条状结构和网格结构共同形成镂空连接框架。再例如，如图11所示，在一些实施例中，从散热块50的四周延伸出的面状结构形成面状连接框架；在此情况下，散热条T的上表面整体构成面状结构。
步骤103、如图12所示，采用模塑料对基板11上设置的第一芯片3(第一电子器件)、第二电子器件4、散热条T进行模塑(molding)。
可以理解的是，针对采用不同形式的连接框架的散热条T而言，一般可以根据实际的需求选择合适的模塑工艺(molding)。
例如，对于在采用镂空连接框架的散热条T(如图9、图10)的情况下，上述步骤103可以包括：将模塑料采用压注成型(compression molding)的方式，对基板11上设置的第一芯片3、第二电子器件4、散热条T进行模塑；也即将流体状的模塑料通过连接框架的镂空区域从上到下进行灌注，从而将第一芯片、第二电子器件、散热条与基板通过模塑料密封在一起，以对SIP封装起到保护的作用。
可以理解的是，在采用压注成型的方式进行模塑后，散热条T的上表面会覆盖一层模塑料，在此情况下，可以采用研磨工艺(grinding)，对模塑料的上表面进行研磨，去除多余的模塑料，暴露出散热块50和散热延伸部51(可参考图12)。
当然，在一些可能实现的方式中，可以在暴露出散热块50和散热延伸部51后，继续进行研磨，去除散热延伸部51，保留散热块50(可参考图13)；在此情况下，散热器件5仅包括散热块50。
另外，对于在采用面状连接框架的散热条T(如图11)的情况下，上述步骤103可以包括：将模塑料采用注塑成型(transfer molding)的方式，对基板11上设置的第一芯片3、第二电子器件4、散热条T进行模塑；也即流体状的模塑料通过散热条T 与基板1之间的侧面区域横向流动填充，从而将第一芯片、第二电子器件、散热条与基板通过模塑料密封在一起，以对SIP封装起到保护的作用。
当然，采用面状连接框架的散热条T，由于模塑料通过侧面注入的方式，散热条T的上表面几乎没有模塑料，因此，在采用注塑成型的方式进行模塑后，可以对散热条T的上表面不进行研磨(可参考图12)，或者进行适当的研磨，保留散热块50和散热延伸部51。
在一些可能实现的方式中，也可以对散热条T的上表面进行深度研磨，去除散热延伸部51，保留散热块50即可(可参考图13)。
在步骤103之后，如图14所示，可以将模塑后的基板11进行翻转(也即将基板11的背面朝上)，并通过助焊剂去除(flux)位于基板11背面的焊盘(pad)表面的氧化膜，通过植球并进行回流焊(reflow)，在基板11的背面安装焊球(solder ball mount)；以使得后续形成的SIP封装能够通过该焊球与PCB进行电连接。
步骤104、采用切割工艺(dicing)，对模塑后的基板11进行切割形成多个独立的SIP封装(参考图2)。
综上所述，采用本申请实施例提供的SIP封装的制作方法，一方面，采用条形封装工艺(strip)，多个散热块通过散热延伸部连接起来形成散热条，将散热条贴附在多个第一电子器件上表面，不易发生错位，降低了制作工艺精度；同时通过一次制作工艺可以完成多个SIP封装的制备，降低了制作成本；另一方面，采用该制作方法制作的SIP封装，通过在大功率的第一电子器件(第一芯片)的上表面塑封散热器件(包括散热块和散热延伸部)来保证第一电子器件向上进行有效散热的同时，将所有的电子器件(包括第一电子器件和第二电子器件)均设置于基板的上表面，从而能够保证基板的下表面可以直接通过较短的连接件直接与PCB连接，进而降低了第一电子器件与PCB的寄生阻抗，提高了第一电子器件的电学性能。
以下对本申请实施例中提供的SIP封装采用单独封装工艺的制作方法进行说明。
如图15所示，本申请实施例提供一种SIP封装的制作方法，包括：
步骤201、参考图3所示，设置基板1，并在基板1的上表面贴装第一电子器件(如第一芯片3)及第二电子器件4。
与步骤101不同的是，步骤201中的基板1、第一电子器件及第二电子器件针对单个SIP封装，相关贴装过程基本一致，可以参考前述步骤101的相关内容，此处不再赘述。
步骤202、参考图3所示，将散热器件5通过导热胶6粘贴在第一电子器件的上表面。
上述散热器件5包括散热块50以及从散热块50侧面延伸出的散热延伸部51。
与前述步骤102中的散热条T包括对应多个SIP封装的散热器件5不同的是：该步骤202中的散热器件5仅对应一个SIP封装，其贴装过程与前述步骤102基本一致，可以参考前述步骤102中的相关内容，此处不再赘述。
步骤203、采用模塑料对基板1上设置的第一芯片3、第二电子器件4、散热器件5进行模塑，以形成系统级封装。
该步骤203的其他相关内容可以参考前述步骤103，此处不再赘述。
需要说明的是，对于上述步骤203中的模塑方式的选择，可以根据采用的散热器件5的结构进行设置。
例如，在散热器件5中的散热延伸部51包括条状结构的情况，步骤203可以包括：将模塑料采用压注成型(compression molding)的方式，对基板1上设置的第一芯片3、第二电子器件4、散热器件5进行模塑；并在该步骤203之后还包括步骤204：对模塑后的模塑料的上表面进行研磨，以暴露出散热块50和散热延伸部51。
步骤204的其他相关内容可以参考前述步骤104，此处不再赘述。
对于该采用单独封装工艺制作SIP封装的工艺的其他的相关内容，可以对应的参考条状封装工艺制作多个SIP封装的工艺中的对应部分，此处不再赘述。
在此基础上，无论是对于前述采用单独封装工艺制作SIP封装的制作方法，还是前述采用条状封装工艺制作多个SIP封装的制作方法，在一些可能实现的方式中，可以在第一芯片3贴装至基板1(或者基板11)上后，如图16所示，可以通过填充工艺(under fill)，在第一芯片3与基板1之间的连接结构31的四周填充树脂，通过树脂分散连接结构31和第一芯片3之间的应力，从而对第一芯片3和连接结构31起到一定的保护作用。
另外，对于上述SIP封装的两种制作方法中其他的相关内容，可以对应的参考前述SIP封装结构实施例中的对应部分；对于前述SIP封装结构实施例中的其他设置结构的制作，可以对应参考上述制作方法或者相关制作方法进行适应的调整，此处不再一一赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种系统级封装，其特征在于，包括：基板、散热器件、第一电子器件及第二电子器件；所述散热器件、所述第一电子器件、所述第二电子器件塑封在模塑料中；
    所述第一电子器件和所述第二电子器件设置在所述基板的一侧、并与所述基板连接；
    所述散热器件包括散热块以及从所述散热块的侧面延伸出的散热延伸部；
    所述散热块通过导热胶粘贴在所述第一电子器件远离所述基板一侧的表面。
  2. 根据权利要求1所述的系统级封装，其特征在于，所述散热块和所述散热延伸部远离所述基板一侧的表面裸露出所述模塑料。
  3. 根据权利要求1或2所述的系统级封装，其特征在于，所述散热块和所述散热延伸部远离所述基板一侧的表面平齐；
    所述散热延伸部的厚度小于所述散热块的厚度。
  4. 根据权利要求1-3任一项所述的系统级封装，其特征在于，所述散热延伸部包括从所述散热块的侧面延伸出的多个条状结构。
  5. 根据权利要求1-3任一项所述的系统级封装，其特征在于，所述散热延伸部包括从所述散热块的侧面向四周延伸的面状结构。
  6. 根据权利要求1-5任一项所述的系统级封装，其特征在于，所述散热块与所述第一电子器件在所述基板上的正投影重合。
  7. 根据权利要求1-6任一项所述的系统级封装，其特征在于，
    所述基板中设置有电源线、接地线；所述第一电子器件通过位于所述基板中的导热孔与所述电源线和/或所述接地线连接。
  8. 根据权利要求1-7任一项所述的系统级封装，其特征在于，所述散热器件的材质包括铜。
  9. 一种电子设备，其特征在于，包括印刷线路板以及如权利要求1-8任一项所述系统级封装；所述系统级封装与所述印刷线路板连接。
  10. 一种系统级封装的制作方法，其特征在于，包括：
    设置基板，所述基板上包括多个系统级封装的待形成区域；并在所述基板上的每一所述系统级封装的待形成区域分别贴装第一电子器件及第二电子器件；
    将散热条通过导热胶粘贴在所述第一电子器件远离所述基板一侧的表面；其中，所述散热条包括：与每一所述第一电子器件对应的散热块以及从所述散热块的侧面延伸出、且连接在相邻散热块之间的散热延伸部；
    采用模塑料对所述基板上设置的所述第一电子器件、所述第二电子器件和所述散热条进行模塑；
    对模塑后的基板进行切割形成多个系统级封装。
  11. 根据权利要求10所述的系统级封装的制作方法，其特征在于，所述连接在相邻散热块之间的散热延伸部包括多个条状连接结构；
    所述采用模塑料对所述基板上设置的所述散热条、所述第一电子器件和所述第二电子器件进行模塑包括：
    将模塑料采用压注成型的方式，对所述基板上设置的所述散热条、所述第一电子器件和所述第二电子器件进行模塑；
    对模塑后的模塑料远离所述基板一侧的表面进行研磨，以暴露出散热块和散热延伸部。
  12. 根据权利要求10所述的系统级封装的制作方法，其特征在于，所述连接在相邻散热块之间的散热延伸部为面状连接结构；
    所述采用模塑料对所述基板上设置的所述散热条、所述第一电子器件和所述第二电子器件进行模塑包括：将模塑料采用注塑成型的方式，对所述基板上设置的所述散热条、所述第一电子器件和所述第二电子器件进行模塑。
PCT/CN2020/082230 2020-03-31 2020-03-31 系统级封装及电子设备 WO2021195903A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/082230 WO2021195903A1 (zh) 2020-03-31 2020-03-31 系统级封装及电子设备
CN202080093295.5A CN114981963A (zh) 2020-03-31 2020-03-31 系统级封装及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/082230 WO2021195903A1 (zh) 2020-03-31 2020-03-31 系统级封装及电子设备

Publications (1)

Publication Number Publication Date
WO2021195903A1 true WO2021195903A1 (zh) 2021-10-07

Family

ID=77927032

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/082230 WO2021195903A1 (zh) 2020-03-31 2020-03-31 系统级封装及电子设备

Country Status (2)

Country Link
CN (1) CN114981963A (zh)
WO (1) WO2021195903A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117275A (zh) * 2013-01-31 2013-05-22 华为技术有限公司 一种芯片封装结构及芯片封装方法
CN104241218A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种带有散热结构的倒装芯片塑封结构及制造方法
CN105489597A (zh) * 2015-12-28 2016-04-13 华为技术有限公司 系统级封装模块组件、系统级封装模块及电子设备
CN109860131A (zh) * 2019-03-22 2019-06-07 西安微电子技术研究所 一种具有内散热装置的系统级封装结构
CN110707081A (zh) * 2019-11-12 2020-01-17 中南大学 用于系统级封装的散热结构

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232294A (ja) * 1993-02-03 1994-08-19 Hitachi Ltd 半導体集積回路装置
US6458626B1 (en) * 2001-08-03 2002-10-01 Siliconware Precision Industries Co., Ltd. Fabricating method for semiconductor package
JP2008130706A (ja) * 2006-11-20 2008-06-05 Sony Corp 半導体装置の製造方法
CN201623107U (zh) * 2010-01-30 2010-11-03 江苏长电科技股份有限公司 印刷线路板芯片倒装散热块外接散热板封装结构
US10580717B2 (en) * 2016-01-11 2020-03-03 Intel Corporation Multiple-chip package with multiple thermal interface materials
KR102167021B1 (ko) * 2018-05-15 2020-10-19 주식회사 네패스 히트싱크를 탑재한 반도체 패키지
CN110911365A (zh) * 2019-10-28 2020-03-24 北京时代民芯科技有限公司 一种倒装焊封装散热结构及制造方法
CN110828407B (zh) * 2019-11-19 2021-08-24 华进半导体封装先导技术研发中心有限公司 一种SiP封装结构及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117275A (zh) * 2013-01-31 2013-05-22 华为技术有限公司 一种芯片封装结构及芯片封装方法
CN104241218A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种带有散热结构的倒装芯片塑封结构及制造方法
CN105489597A (zh) * 2015-12-28 2016-04-13 华为技术有限公司 系统级封装模块组件、系统级封装模块及电子设备
CN109860131A (zh) * 2019-03-22 2019-06-07 西安微电子技术研究所 一种具有内散热装置的系统级封装结构
CN110707081A (zh) * 2019-11-12 2020-01-17 中南大学 用于系统级封装的散热结构

Also Published As

Publication number Publication date
CN114981963A (zh) 2022-08-30

Similar Documents

Publication Publication Date Title
US7960827B1 (en) Thermal via heat spreader package and method
US9472485B2 (en) Hybrid thermal interface material for IC packages with integrated heat spreader
US9142473B2 (en) Stacked type power device module
US8314486B2 (en) Integrated circuit packaging system with shield and method of manufacture thereof
US7633144B1 (en) Semiconductor package
US10818637B2 (en) Thin bonded interposer package
EP4030475A1 (en) Encapsulation structure and electronic apparatus
KR20160012589A (ko) 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US7489044B2 (en) Semiconductor package and fabrication method thereof
JP2011114192A (ja) 半導体装置
KR20160044685A (ko) 반도체 패키지 및 그 제조 방법
EP0880176B1 (en) Semiconductor device having pellet mounted on radiating plate thereof
CN105789154A (zh) 一种倒装芯片模组
KR20130089473A (ko) 반도체 패키지
JP2000294723A (ja) 積層型半導体装置およびその製造方法
JP5667381B2 (ja) 半導体装置及びその製造方法
JP2003086726A (ja) 高電力モノリシックマイクロ波集積回路パッケージ
CN210575901U (zh) 具有高散热性的板级扇出封装结构
CN115332195B (zh) 双面SiP封装结构及其制作方法
WO2021195903A1 (zh) 系统级封装及电子设备
CN112259463B (zh) 扇出芯片的封装方法及扇出芯片封装结构
US20180240738A1 (en) Electronic package and fabrication method thereof
CN209880583U (zh) 半导体封装结构
KR20140070141A (ko) 열 방출 부를 갖는 반도체 패키지
KR20120126365A (ko) 유닛 패키지 및 이를 갖는 스택 패키지

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20928348

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20928348

Country of ref document: EP

Kind code of ref document: A1