TWI724313B - 屏蔽扇出型封裝之半導體裝置及製造方法 - Google Patents

屏蔽扇出型封裝之半導體裝置及製造方法 Download PDF

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TWI724313B
TWI724313B TW107123875A TW107123875A TWI724313B TW I724313 B TWI724313 B TW I724313B TW 107123875 A TW107123875 A TW 107123875A TW 107123875 A TW107123875 A TW 107123875A TW I724313 B TWI724313 B TW I724313B
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conductive
semiconductor die
conductive wall
die
encapsulant
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TW107123875A
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TW201921632A (zh
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渡邊住友
草薙京葉
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美商美光科技公司
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Abstract

本發明之若干態樣係針對具有防電磁干擾之一整合屏蔽之扇出型封裝半導體裝置及此等裝置之製造方法。可藉由在一重佈結構上形成一導電壁且將一導電蓋安置於一囊封物之一上表面上來建構該屏蔽。該導電壁及該導電蓋彼此電連接。由於在該重佈結構上直接形成該導電壁且將該導電蓋單獨安置至該囊封物之一上表面上，所以可易於使用有效率且具成本效益之晶圓級或面板級處理技術來形成一電磁屏蔽。因此，根據本發明之半導體裝置之若干實施例屏蔽半導體晶粒之積體電路免受電磁干擾。

Description

屏蔽扇出型封裝之半導體裝置及製造方法
本發明大體上係針對半導體裝置。特定言之，本發明之若干實施例係針對具有防電磁干擾之一整合屏蔽之扇出型封裝半導體裝置及此等裝置之製造方法。
微電子裝置大體上具有一半導體晶粒(即，一晶片)，其包含具有一高密度之極小組件之積體電路。通常，晶粒包含電耦合至積體電路之一極小接合墊陣列。接合墊係供應電壓、信號等等透過其傳輸至積體電路及自積體電路傳輸之外部電接點。在形成晶粒之後，「封裝」晶粒以將接合墊耦合至可更容易耦合至各種電力供應線、信號線及接地線之一較大電端子陣列。用於封裝晶粒之習知程序包含將晶粒上之接合墊電耦合至一中介層基板之引線、球墊或其他類型之電端子之一陣列。接著，囊封晶粒以保護其免受環境因數(例如水分、微粒、靜電及實體衝擊)影響。
不同類型之半導體晶粒可具有大不相同接合墊配置，但應與類似外部裝置相容。因此，既有封裝技術可包含將一重佈層附接至一半導體晶粒。重佈層包含將晶粒之接合墊與重佈層之接合墊連接之線及/或通路。重佈層包含經配置以與外部裝置之電端子配合之引線、球墊或其他類型之電端子之一陣列。
一挑戰係電磁干擾會損及高效能半導體裝置之操作。因此，可期望保護一半導體晶粒之積體電路免受電磁干擾。然而，預成形銅蓋及其他形式之外部屏蔽較昂貴且可能不實用。類似地，將完全嵌入一囊封物內之預成形銅屏蔽併入至半導體裝置之封裝中亦較昂貴。
在一實施例中，一種封裝半導體裝置包括：一重佈結構，其具有第一側、一第二側、具有自該第一側至該第二側之一厚度之一介電形成物、該重佈結構之該第一側處之晶粒接點、該重佈結構之該第一側處之至少一屏蔽接點及該重佈結構之該第二側處之球墊；一半導體晶粒，其安裝於該重佈結構之該第一側上，其中該半導體晶粒具有一外周邊；一導電壁，其在該重佈結構之該第一側上與該半導體晶粒之該外周邊橫向隔開，其中該導電壁電耦合至該屏蔽接點且圍繞該半導體晶粒之該外周邊之至少一部分延伸；一囊封物，其覆蓋該半導體晶粒之至少一部分且相對於該半導體晶粒之該外周邊橫向向外延伸；及一導電蓋，其附接至該囊封物且電耦合至該導電壁，使得該導電壁及該導電蓋形成經組態以保護該半導體晶粒免受電磁干擾之一屏蔽。
在另一實施例中，一種封裝半導體裝置包括：一重佈結構，其具有一第一側、一第二側、具有自該第一側至該第二側之一厚度之一介電形成物、該重佈結構之該第一側處之晶粒接點、該重佈結構之該第一側處之至少一屏蔽接點及該重佈結構之該第二側處之球墊；一半導體晶粒，其安裝於該重佈結構之該第一側上，其中該半導體晶粒包含一外周邊；一導電屏蔽結構，其具有位於該重佈結構之該第一側上之一導電側壁及電耦合至該側壁之一導電蓋，其中該側壁電耦合至該屏蔽接點；一囊封物，其具有一第一部分及一第二部分，該第一部分具有位於該半導體晶粒上方之一上表面且該第一部分相對於該半導體晶粒之該外周邊橫向向外延伸至該導電屏蔽結構之該側壁，該第二部分自該導電屏蔽結構橫向向外延伸，且該導電蓋附接至該第一部分之該上表面。
在另一實施例中，一種封裝一半導體裝置之方法包括：將一半導體晶粒電耦合至一重佈結構之一第一側處之晶粒接點，其中該等晶粒接點電耦合至該重佈結構之一第二側處之球墊；在該重佈結構之該第一側上形成一導電壁，其中該導電壁電耦合至該重佈結構之該第一側處之至少一屏蔽接點，且其中該屏蔽接點電耦合至該重佈結構之該第二側處之一球墊；將一囊封物沈積於該半導體晶粒上方，其中該囊封物具有一上表面；及將一導電蓋安置至該囊封物之該上表面上，其中該導電蓋電耦合至該導電壁。
下文將描述半導體裝置之若干實施例之特定細節。本發明之若干實施例之一態樣係：藉由在一重佈結構上形成一導電壁且將一導電蓋安置於一囊封物之一上表面上來建構一屏蔽結構。該導電壁及該導電蓋彼此電連接。由於在該重佈結構上直接形成該導電壁且將該導電蓋單獨安置至該囊封物之一上表面上，所以可易於使用有效率且具成本效益之晶圓級或面板級處理技術來形成一電磁屏蔽。因此，根據本發明之半導體裝置之若干實施例保護半導體晶粒之積體電路免受電磁干擾。
根據本發明之若干實施例之封裝半導體裝置包含一重佈結構及一半導體晶粒。該重佈結構具有一第一側、一第二側及具有自該第一側至該第二側之一厚度之一介電形成物。該重佈結構亦可包含該第一側處之晶粒接點、該第一側處之至少一屏蔽接點及該第二側處之球墊。該半導體晶粒安裝至該重佈結構之該第一側，且該半導體晶粒具有一外周邊。該等封裝半導體裝置可進一步包含一導電壁、一囊封物及一導電蓋。該導電壁位於該重佈結構之該第一側上且與該半導體晶粒之該外周邊橫向隔開。該導電壁電耦合至該屏蔽接點，且該導電壁圍繞該半導體晶粒之該外周邊之至少一部分延伸。該囊封物覆蓋該半導體晶粒之至少一部分且相對於該半導體晶粒之該外周邊橫向向外延伸。該導電蓋附接至該囊封物且電耦合至該導電壁。該導電壁及該導電蓋形成經組態以保護該半導體晶粒免受電磁干擾之一屏蔽結構。
圖1A係根據本發明之實施例之一封裝半導體裝置100 (「裝置100」)之一橫截面圖，且圖1B係其中為了清楚而切去各種層之圖1A之裝置100之一俯視圖。參考圖1A，裝置100包含：一半導體晶粒110；一重佈結構(RDS) 120，其支撐半導體晶粒110；及一囊封物140，其覆蓋半導體晶粒110之至少一部分且跨RDS 120之一表面橫向延伸。裝置100進一步包含一導電壁160及電耦合至導電壁160之一導電蓋170。導電壁160電耦合至一接地接點，使得導電壁160及導電蓋170共同界定經組態以保護半導體晶粒110免受電磁干擾之一屏蔽結構。
半導體晶粒110可包含經配置以形成積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他構件之半導體材料、導電材料及介電材料。例如，半導體晶粒110可包含積體記憶體電路及/或邏輯電路，其可包含各種類型之半導體組件及功能構件，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體構件。半導體晶粒110可進一步包含電耦合至積體電路之接合墊112及附接至接合墊112之導電凸塊114。在一些實施例中，裝置100可包含可彼此相同之複數個半導體晶粒(例如經製造以具有相同設計及規格之記憶體晶粒)或可彼此不同之複數個半導體晶粒(例如不同類型之記憶體晶粒或控制器、邏輯及/或記憶體晶粒之一組合)。
RDS 120具有一第一側121、一第二側122及具有自第一側121至第二側122之一厚度之一介電形成物124。RDS 120進一步包含第一側121處之晶粒接點125、第一側121處之至少一屏蔽接點126、第二側122處之球墊127及將球墊127電耦合至晶粒接點125及屏蔽接點126之導線128。在所繪示之實施例中，晶粒接點125及對應球墊127可位於對應導線128之對置端處。類似地，屏蔽接點126及對應球墊127可位於對應導線128之對置端處。在圖1A所繪示之實施例中，半導體晶粒110之個別接合墊112經由導電凸塊114電耦合至晶粒接點125之一對應者。
囊封物140具有導電壁160內之一第一部分142 (其覆蓋半導體晶粒110之至少一部分)及導電壁160外之一第二部分144。囊封物140之第一部分142可相對於半導體晶粒之一外周邊116橫向向外延伸至導電壁160之一內表面161。第一部分142可包含完全覆蓋半導體晶粒110之一背面118之一上表面143，且囊封物140之第一部分142亦可填充半導體晶粒110與RDS 120之間之一間隙。替代地，半導體晶粒110與RDS 120之間之間隙可由一底膠材料填充。囊封物140之第二部分144可自導電壁160之一外表面162橫向向外延伸。囊封物140之第二部分144可具有與囊封物140之第一部分142之上表面143共面之一上表面145。囊封物140之第一部分142及第二部分144可由相同材料製成，或替代地，第一部分142及第二材料144可為不同材料。
囊封物140可為使用一噴嘴或其他類型之沈積技術來沈積至RDS 120上之一密封樹脂。替代地，可使用注射模製或其他模製技術來將囊封物140模製至RDS 120上及半導體晶粒110周圍。
導電壁160可為形成於RDS 120之第一側121上之一側壁，使得導電壁160之至少一部分接觸RDS 120之屏蔽接點126之一或多者。同時參考圖1A及圖1B，可藉由沈積銀、焊錫、銅或其他適合導電材料來形成導電壁160，使得導電壁160圍繞半導體晶粒110之外周邊116之至少一部分延伸。參考圖1B，導電壁160可完全圍繞半導體晶粒110之周邊116延伸，但在其他實施例中，導電壁160可具有藉由間隙來彼此分離之離散分段。例如，導電壁160可具有其中各分段與外周邊116之一對應側橫向向外隔開之四個分段，或在其他實施例中，導電壁160可具有兩個L形分段，等等。導電壁160可具有與囊封物140之上表面143共面之一頂面163及電耦合至屏蔽接點126之一或多者之一底面164。導電壁160之底面164可靜置於屏蔽接點126及/或介電形成物124之上表面上。無論何種情況，導電壁160電耦合至RDS 120之第二側122上之一焊球130或其他電連接器。
導電蓋170可藉由一導電黏著劑172來附接至囊封物140之上表面143及導電壁160之頂面163。導電蓋170可完全覆蓋導電壁160內之區域。例如，導電蓋170可覆蓋囊封物140之第一部分142 (其包含半導體晶粒110之背面118上方之囊封物140之部分)及導電壁160之頂面163之至少一部分。在其他實施例中，導電蓋170可具有開口、狹槽、通道或其他類型之空隙，使得導電蓋170不完全覆蓋導電壁160內之區域。導電蓋170可為經預成形且使用導電黏著劑172來附接至囊封物140之第一部分142及導電壁160之一銅面板。在其他實施例中，導電蓋170可為依其他方式安置於囊封物140及導電壁160上之一或多個導電材料層。
在操作中，導電壁160及導電蓋170可經由RDS 120之第二側122上之對應焊球130來電耦合至接地。導電壁160及導電蓋170一起形成經組態以保護半導體晶粒110免受電磁干擾之一屏蔽結構。本發明之實施例之一優點係：可在晶圓級或面板級處形成屏蔽結構，此係因為可使用晶圓級或面板級處理之已知技術來針對若干不同裝置形成個別封裝裝置100之個別導電壁160。類似地，可使用已知晶圓級或面板級處理技術來將導電蓋170安裝至對應裝置100。因此，預期本發明將有效率地產生屏蔽封裝之半導體裝置。
圖2A至圖2H係繪示使用晶圓級或面板級製造技術來形成圖1A之裝置100之實施例之方法之各種階段的橫截面圖。更明確而言，將一完整裝置100繪示為形成於中間且將兩個額外裝置之部分繪示為形成於完整裝置之左邊及右邊。儘管圖2A至圖2H中僅展示一單一完整裝置100，但應瞭解，可使用晶圓級或面板級處理來同時封裝複數個裝置。
圖2A展示(a)已使RDS 120形成及附接至一載體200且(b) 已使導電壁160形成於RDS 120之第一側121上之後之方法之一階段。載體200對後續處理階段提供機械支撐且可為由(例如)矽、絕緣體上矽、化合物半導體(例如氮化鎵)、玻璃或其他適合材料形成之一臨時載體。在一些實施例中，載體200由一釋放層210覆蓋，使得可在自釋放層210移除封裝裝置之後再使用載體200。釋放層210防止RDS 120與載體200直接接觸以保護RDS 120免受污染或實體損壞。釋放層210可為一次性膜(例如基於環氧樹脂之材料之一層疊膜)或其他適合材料。在一些實施例中，釋放層210係促進一後續階段中之移除之一雷射敏感或光敏材料。
可藉由將一導電材料安置於RDS 120之第一側121上來形成導電壁160。導電材料之至少一部分接觸屏蔽接點126之至少一者。在一實施例中，首先將一基座220沈積於RDS 120之第一側121上且在基座220中形成開口222。接著，在開口222中且跨RDS 120之第一側121沈積導電材料以形成導電壁160。導電壁160之導電材料可為一導電膏，諸如銀膏或焊錫膏。可視情況回焊導電膏，使得回焊膏之表面張力引起導電材料留在開口222內且自RDS 120之第一表面121突出。在其他實施例中，可藉由將一導電材料三維印刷於RDS 120之第一表面121上及屏蔽接點126上方來形成導電壁160。在額外實施例中，可藉由電鍍、無電電鍍、氣相沈積技術及/或其他金屬化技術來形成導電壁。
圖2B至圖2E繪示已將半導體晶粒110安裝至RDS 120且已將囊封物140安置於半導體晶粒110上方之後之後續階段。更明確而言，圖2B繪示將半導體晶粒110安裝至RDS 120之第一側121使得半導體晶粒110之接合墊112經由導電凸塊114電耦合至RDS 120之晶粒墊125。圖2C繪示已將囊封物140之材料安置於半導體晶粒110及導電壁160上方之後之方法。可使用注射模製技術、其他模製技術或藉由使用圍繞晶圓或面板之周邊之一圍擋使囊封物140之材料跨RDS 120之正面121流動來安置囊封物140。囊封物140可經組態以完全覆蓋導電壁160以及半導體晶粒110。在所繪示之實施例中，囊封物140亦可填充半導體晶粒110與RDS 120之第一表面121之間之間隙，或間隙可由一單獨底膠材料填充。圖2D繪示已充分固化囊封物140以提供半導體晶粒110之結構完整性且已移除載體200之後之方法。
圖2E繪示已形成囊封物140之上表面143及導線160之頂面163之後之方法。可藉由研磨、化學機械拋光、蝕刻或適合於移除囊封物140之上部分及導電壁160之導電材料之上部分之其他技術來形成上表面143及頂面163。在所繪示之實施例中，已研磨圖2D中所展示之囊封物140之材料之上部分及導電壁160之上部分以形成導電壁160之暴露頂面163且保留半導體晶粒110之背面118上方之囊封物140之一部分。因此，囊封物140之上表面143及導電壁160之頂面163彼此共面。在其他實施例中，囊封物140之上表面143及導線160之頂面163之標高可與半導體晶粒110之背面118共面。方法之此階段中之導電壁160之頂面163之形成進一步形成(a)半導體晶粒110所在之導電壁160之間之區域中之囊封物140之第一部分142及(b)切割道「L」所在之導電壁160之間之區域中之囊封物140之第二部分144。
圖2F繪示已將導電蓋170附接至囊封物140之上表面143及導電壁160之頂面163之後之方法之一階段。可使用一導電黏著劑172來將導電蓋170附接至導電壁160之頂面163。在所繪示之實施例中，導電蓋170亦附接至半導體晶粒110上方之囊封物140之第一部分142之上表面143。在其中囊封物140之上表面143與半導體晶粒110之背面118共面之實施例中，導電蓋170可直接附接至半導體晶粒110之背面118以促進熱量自半導體晶粒110耗散。導電蓋170及與導電蓋170附接之對應導電壁160一起形成用於保護半導體晶粒110免受電磁干擾之屏蔽結構。
圖2G繪示已將焊球130沈積於RDS 120之球墊127上之後之一階段。圖2H繪示藉由沿切割道「L」切穿囊封物140之第二部分144來形成個別裝置100。
圖3A係根據本發明之實施例之一封裝半導體裝置300 (「裝置300」)之一橫截面圖，且圖3B係其中為了清楚而切去各種層之圖3A之裝置300之一俯視圖。參考圖3A，裝置300包含藉由電鍍或其他金屬化技術所形成之一導電壁360。在此實例中，在形成導電壁360之前，將半導體晶粒110附接至RDS 120且將囊封物140之材料安置於半導體晶粒110及RDS 120上方。在安置囊封物140之後，形成穿過囊封物140之開口，使得穿過囊封物140之開口與屏蔽接點126對準。接著，可使用屏蔽接點126來將一導電材料鍍覆至開口中。例如，可使用濺鍍或化學氣相沈積技術來將銅或其他適合導電材料之一晶種層沈積至開口中，接著可使用電鍍或無電電鍍技術來將銅或另一適合導電材料鍍覆至開口中。
圖3B繪示其中導電壁360具有四個單獨分段之一實施例，其中各分段與半導體晶粒110之一對應邊緣隔開。替代地，其他實施例可包含在兩個筆直分段之間具有導電材料之隅角362 (以虛線展示)之兩個L形分段。應瞭解，導電壁可在個別分段之間具有比圖1B及圖3B中所展示之間隙少或多之間隙。
圖4係根據本發明之實施例之一封裝半導體裝置400 (「裝置400」)之一橫截面圖。除裝置400包含具有一介電形成物424及多個導電層之一多層級重佈結構(RDS) 420之外，裝置400類似於上文所描述之裝置100。例如，RDS 420具有包含晶粒接點425及屏蔽接點426之一第一導電層級及包含一屏蔽組件460及球墊427之一第二導電層級。在圖4所繪示之實施例中，屏蔽組件460電耦合至第一導電層級處之一導線428，使得屏蔽組件460、半導體晶粒110之一接合墊112 (例如最左接合墊112)、導電壁160及導電蓋170全部彼此電耦合。因此，屏蔽組件460、導電壁160及導電蓋170一起形成保護半導體晶粒110免受電磁干擾之一屏蔽結構。
圖5係根據本發明之實施例之一封裝半導體裝置500 (「裝置500」)之一橫截面圖。裝置500類似於裝置400，但裝置500包含一導電蓋570，其形成於囊封物140之上表面143及導電壁160之頂面163上，而非為附接至囊封物140及導電壁160之一預成形導電面板。例如，可藉由使用電鍍、無電電鍍、氣相沈積或適合於沈積金屬之其他技術沈積銅或其他適合導電材料來使導電蓋570形成於囊封物140及導電壁160上。因此，此實施例無需一預成形金屬罩及一黏著劑。
圖6至圖8分別為具有多個半導體晶粒之封裝半導體裝置600、700及800之橫截面圖。在圖1A至圖8中，相同元件符號係指類似或甚至相同組件。裝置600、700及800各包含至少一第一半導體晶粒110a及一第二半導體晶粒110b (統稱為「第一晶粒110a及第二晶粒110b」)。第一晶粒110a及第二晶粒11b可彼此相同或其等可為不同類型之晶粒。例如，第一晶粒110a及第二晶粒110b可為相同或類似類型之記憶體晶粒，或第一半導體晶粒110a可為一記憶體晶粒且第二半導體晶粒110b可為一邏輯晶粒或一處理器晶粒。
參考圖6，半導體裝置600 (「裝置600」)具有上文相對於裝置100所描述之RDS 120、導電壁160及頂蓋170。在此實施例中，第一晶粒110a及第二晶粒110b兩者位於囊封物140之一共同部分中。如同裝置100，導電蓋170及導電壁160電耦合在一起且形成保護第一晶粒110a及第二晶粒110b免受電磁干擾之一屏蔽。
參考圖7，半導體裝置700 (「裝置700」)具有靠近裝置700之外周邊之導電壁160及將囊封物140之第一部分分成導電壁160內之一第一區段742a及一第二區段742b之一內導電分隔物760。裝置700亦包含具有屏蔽組件770之一多層級RDS 720。內導電分隔物760可電耦合至屏蔽組件770，且屏蔽組件770之至少一者可電耦合至導電壁160及頂蓋170。因而，內導電分隔物760、屏蔽組件770、導電壁160及頂蓋170可圍繞第一晶粒110a及第二晶粒110b之各者形成保護第一晶粒110a及第二晶粒110b免受電磁干擾之屏蔽結構。
參考圖8，半導體裝置800 (「裝置800」)類似於裝置700，但僅完全屏蔽第一半導體晶粒110a。更明確而言，導電壁160僅圍繞第一半導體晶粒110a而非裝置800之整個外周邊部分延伸。第二半導體晶粒110b之一側未被屏蔽。
上文參考圖1A至圖8所描述之半導體裝置之任何者可併入至各者更大及/或更複雜系統之任何者中，圖9中所示意性展示之系統990係該等系統之一代表性實例。系統990可包含一半導體晶粒總成900、一電源992、一驅動器994、一處理器996及/或其他子系統或組件998。半導體晶粒總成900可包含具有大體上類似於上文所描述之半導體裝置之特徵之特徵之半導體裝置。所得系統990可執行各種功能之任何者，諸如記憶體儲存、資料處理及/或其他適合功能。因此，代表性系統990可包含(但不限於)手持裝置(例如行動電話、平板電腦、數位讀取器及數位音訊播放器)、電腦及電器。系統990之組件可收容於一單一單元中或分佈於多個互連單元上(例如，透過一通信網路)。系統990之組件亦可包含遠端裝置及各種電腦可讀媒體之任何者。
可自上文瞭解，本文已為了說明而描述本發明之特定實施例，但可在不背離本發明之範疇的情況下作出各種修改。因此，本發明僅受限於隨附申請專利範圍。
100‧‧‧封裝半導體裝置110‧‧‧半導體晶粒110a‧‧‧第一半導體晶粒110b‧‧‧第二半導體晶粒112‧‧‧接合墊114‧‧‧導電凸塊116‧‧‧外周邊118‧‧‧背面120‧‧‧重佈結構(RDS)121‧‧‧第一側122‧‧‧第二側124‧‧‧介電形成物125‧‧‧晶粒接點126‧‧‧屏蔽接點127‧‧‧球墊128‧‧‧導線130‧‧‧焊球140‧‧‧囊封物142‧‧‧第一部分143‧‧‧上表面144‧‧‧第二部分145‧‧‧上表面160‧‧‧導電壁161‧‧‧內表面162‧‧‧外表面163‧‧‧頂面164‧‧‧底面170‧‧‧導電蓋172‧‧‧導電黏著劑200‧‧‧載體210‧‧‧釋放層220‧‧‧基座222‧‧‧開口300‧‧‧封裝半導體裝置360‧‧‧導電壁362‧‧‧隅角400‧‧‧封裝半導體裝置420‧‧‧RDS424‧‧‧介電形成物425‧‧‧晶粒接點426‧‧‧屏蔽接點427‧‧‧球墊428‧‧‧導線460‧‧‧屏蔽組件500‧‧‧封裝半導體裝置570‧‧‧導電蓋600‧‧‧封裝半導體裝置700‧‧‧封裝半導體裝置720‧‧‧多層級RDS742a‧‧‧第一區段742b‧‧‧第一區段760‧‧‧內導電分隔物770‧‧‧屏蔽組件800‧‧‧封裝半導體裝置900‧‧‧半導體晶粒總成990‧‧‧系統992‧‧‧電源994‧‧‧驅動器996‧‧‧處理器998‧‧‧其他子系統/組件L‧‧‧切割道
可參考以下圖式來較佳理解本發明之諸多態樣。圖式中之組件未必按比例繪製。相反地，重點放在清楚地繪示本發明之原理。
圖1A係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖1B係其中為了清楚而切去各種層之圖1A之封裝半導體裝置之一俯視圖。
圖2A至圖2H係用於形成根據本發明之實施例之封裝半導體裝置之一方法之各種階段之橫截面圖。
圖3A係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖3B係其中為了清楚而切去各種層之圖3A之封裝半導體裝置之一俯視圖。
圖4係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖5係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖6係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖7係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖8係根據本發明之實施例之一封裝半導體裝置之一橫截面圖。
圖9係包含根據本發明之實施例所組態之一半導體裝置之一系統之一示意圖。
為便於參考，在本發明中，相同元件符號用於識別類似或類比組件或特徵，但使用相同元件符號不隱含應將部件解釋為相同的。其實，在本文所描述之諸多實例中，相同元件符號部件具有不同結構及/或功能。此外，相同陰影可用於指示可為組成類似之一材料橫截面，但使用相同陰影不隱含應將材料解釋為相同的。
另外，在以下描述中，討論若干特定細節以提供本發明之實施例之一透徹且可行描述。然而，熟悉相關技術者將認識到，可在無一或多個特定細節的情況下實踐本發明。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以免使本發明之其他態樣不清楚。一般而言，應瞭解，除本文中所揭示之特定實施例之外，各種其他裝置、系統及方法亦可在本發明之範疇內。
如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可係指半導體晶粒總成中之特徵鑑於圖中所展示之定向之相對方向或位置。例如，「上」或「最上」可涉及比一特徵更靠近於一頁之頂部之另一特徵。然而，此等術語應被廣義解釋為包含具有其他定向(諸如其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換之相反或傾斜定向)之半導體裝置。
100‧‧‧封裝半導體裝置
110‧‧‧半導體晶粒
112‧‧‧接合墊
114‧‧‧導電凸塊
116‧‧‧外周邊
118‧‧‧背面
120‧‧‧重佈結構(RDS)
121‧‧‧第一側
122‧‧‧第二側
124‧‧‧介電形成物
125‧‧‧晶粒接點
126‧‧‧屏蔽接點
127‧‧‧球墊
128‧‧‧導線
130‧‧‧焊球
140‧‧‧囊封物
142‧‧‧第一部分
143‧‧‧上表面
144‧‧‧第二部分
145‧‧‧上表面
160‧‧‧導電壁
161‧‧‧內表面
162‧‧‧外表面
163‧‧‧頂面
164‧‧‧底面
170‧‧‧導電蓋
172‧‧‧導電黏著劑

Claims (6)

  1. 一種封裝一半導體裝置之方法，其包括：將一半導體晶粒電耦合至一重佈結構之一第一側處之多個晶粒接點，其中該等晶粒接點電耦合至該重佈結構之一第二側處之多個球墊；藉由印刷一導電材料或回流一導電膏以在該重佈結構之該第一側上形成一導電壁，其中該導電壁電耦合至該重佈結構之該第一側處之至少一屏蔽接點，且其中該屏蔽接點電耦合至該重佈結構之該第二側處之一球墊；將一囊封物沈積於該半導體晶粒上方，其中該囊封物具有一上表面；移除該囊封物之一部分及該導電壁之一部分以在該半導體晶粒上方之該囊封物上形成該上表面及在該導電壁上形成一頂面，其中該囊封物之該上表面及該導電壁之該頂面係共面的；及將一導電蓋安置至該囊封物之該上表面上，其中該導電蓋電耦合至該導電壁。
  2. 如請求項1之方法，其中：沈積該囊封物包括：使用該囊封物來覆蓋該半導體晶粒之一背面。
  3. 如請求項2之方法，其中將該導電蓋安置至該囊封物之該上表面上包括：將一金屬板黏著至該囊封物之該上表面及該導電壁之該頂面。
  4. 如請求項2之方法，其中將該導電蓋安置至該囊封物之該上表面上包括：將至少一層之一導電材料沈積至該囊封物之該表面上及直接沈積至該導電壁之該頂面上。
  5. 如請求項2之方法，其中該重佈結構包括一多層級屏蔽結構，且其中該方法進一步包括：在該多層級屏蔽結構中形成電耦合至該導電壁及該導電蓋之一屏蔽組件。
  6. 一種封裝半導體裝置，其包括：一重佈結構，其具有一第一側、一第二側、具有自該第一側至該第二側之一厚度之一介電形成物、該重佈結構之該第一側處之多個晶粒接點、該重佈結構之該第一側處之至少一屏蔽接點及該重佈結構之該第二側處之多個球墊；一半導體晶粒，其安裝於該重佈結構之該第一側上，其中該半導體晶粒具有一外周邊；一導電壁，其電耦合至該屏蔽接點且位在該重佈結構之該第一側上在一位置處與該半導體晶粒之該外周邊橫向隔開，其中該導電壁圍繞該半導體晶粒之該外周邊之僅一部分延伸；一囊封物，其覆蓋該半導體晶粒之至少一部分且相對於該半導體晶粒之該外周邊橫向向外延伸；及一導電蓋，其附接至該囊封物且電耦合至該導電壁，使得該導電壁及該導電蓋形成經組態以保護該半導體晶粒免受電磁干擾之一屏蔽；其中該導電壁係不連續的，使其具有一間隙。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10453762B2 (en) 2017-07-28 2019-10-22 Micron Technology, Inc. Shielded fan-out packaged semiconductor device and method of manufacturing
KR20190088810A (ko) * 2018-01-19 2019-07-29 삼성전자주식회사 팬-아웃 반도체 패키지
US11270953B2 (en) * 2018-08-31 2022-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with shielding structure
GB2584106B (en) * 2019-05-21 2024-03-27 Pragmatic Printing Ltd Flexible electronic structure
CN111816640A (zh) * 2020-06-02 2020-10-23 江苏长电科技股份有限公司 一种bga电磁屏蔽封装结构及其制造方法
TWI774008B (zh) 2020-06-19 2022-08-11 啟碁科技股份有限公司 封裝結構及其製造方法
CN112802822A (zh) * 2020-09-10 2021-05-14 成都芯源系统有限公司 集成电路封装结构、集成电路封装单元及相关制作方法
CN112736065A (zh) * 2020-09-10 2021-04-30 成都芯源系统有限公司 用于集成电路封装的面板状金属墙格阵列及其制造方法
CN112701089A (zh) * 2020-09-10 2021-04-23 成都芯源系统有限公司 集成电路封装结构、集成电路封装单元及相关制造方法
CN112802823A (zh) * 2021-03-30 2021-05-14 江苏芯德半导体科技有限公司 一种emi屏蔽的晶圆级芯片封装结构及封装方法
US20220384505A1 (en) * 2021-05-28 2022-12-01 UTAC Headquarters Pte. Ltd. Semiconductor Device and Method of Forming an Optical Semiconductor Package with a Shield Structure
TWI828491B (zh) * 2022-12-23 2024-01-01 創意電子股份有限公司 中介層裝置及半導體封裝結構

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110298105A1 (en) * 2009-05-01 2011-12-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure
US20110298109A1 (en) * 2010-06-02 2011-12-08 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated emi shielding frame with cavities containing penetrable material over semiconductor die
US20150108621A1 (en) * 2013-10-17 2015-04-23 Eduard J. Pabst Shielded device packages and related fabrication methods
US20160148882A1 (en) * 2008-05-28 2016-05-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128890A1 (en) 2006-11-30 2008-06-05 Advanced Semiconductor Engineering, Inc. Chip package and fabricating process thereof
US7741567B2 (en) * 2008-05-19 2010-06-22 Texas Instruments Incorporated Integrated circuit package having integrated faraday shield
US8378383B2 (en) 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US9484279B2 (en) 2010-06-02 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9312218B2 (en) * 2011-05-12 2016-04-12 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor die
CN102315200A (zh) * 2011-09-02 2012-01-11 华为终端有限公司 一种芯片封装结构、封装方法及电子设备
US8872312B2 (en) * 2011-09-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. EMI package and method for making same
TW201405758A (zh) * 2012-07-19 2014-02-01 矽品精密工業股份有限公司 具有防電磁波干擾之半導體元件
US9818734B2 (en) * 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
KR20140057982A (ko) * 2012-11-05 2014-05-14 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
KR20170019023A (ko) * 2015-08-10 2017-02-21 에스케이하이닉스 주식회사 전자기 간섭 차폐부를 갖는 반도체 패키지 및 제조 방법
US10624248B2 (en) * 2016-04-08 2020-04-14 Samsung Electronics Co., Ltd. EMI shielding structure and manufacturing method therefor
US10553542B2 (en) * 2017-01-12 2020-02-04 Amkor Technology, Inc. Semiconductor package with EMI shield and fabricating method thereof
US10453762B2 (en) 2017-07-28 2019-10-22 Micron Technology, Inc. Shielded fan-out packaged semiconductor device and method of manufacturing
US10410999B2 (en) * 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
US10593629B2 (en) * 2018-07-09 2020-03-17 Powertech Technology Inc. Semiconductor package with a conductive casing for heat dissipation and electromagnetic interference (EMI) shield and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160148882A1 (en) * 2008-05-28 2016-05-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield
US20110298105A1 (en) * 2009-05-01 2011-12-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure
US20110298109A1 (en) * 2010-06-02 2011-12-08 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated emi shielding frame with cavities containing penetrable material over semiconductor die
US20150108621A1 (en) * 2013-10-17 2015-04-23 Eduard J. Pabst Shielded device packages and related fabrication methods

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