TWI541976B - 三維積體電路封裝 - Google Patents

三維積體電路封裝 Download PDF

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TWI541976B
TWI541976B TW102147441A TW102147441A TWI541976B TW I541976 B TWI541976 B TW I541976B TW 102147441 A TW102147441 A TW 102147441A TW 102147441 A TW102147441 A TW 102147441A TW I541976 B TWI541976 B TW I541976B
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conductive
wafer
integrated circuit
transient voltage
voltage suppression
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TW102147441A
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TW201523833A (zh
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柯明道
莊哲豪
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晶焱科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

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Description

三維積體電路封裝
本發明係關於一種封裝技術，且特別關於一種系統級靜電放電保護之三維積體電路封裝。
由於積體電路(IC)之元件已微縮化至奈米尺寸，很容易受到靜電放電(ESD)的衝擊而損傷，再加上一些電子產品，如筆記型電腦或手機亦作的比以前更加輕薄短小，對ESD衝擊的承受能力更為降低。對於這些電子產品，若沒有利用適當的ESD保護裝置來進行保護，則電子產品很容易受到ESD的衝擊，而造成電子產品發生系統重新啟動，甚至硬體受到傷害而無法復原的問題。目前，所有的電子產品都被要求能通過IEC 61000-4-2標準之ESD測試需求。對於電子產品的ESD問題，使用暫態電壓抑制器(TVS)是較為有效的解決方法，讓ESD能量快速透過TVS予以釋放，避免電子產品受到ESD的衝擊而造成傷害。
TVS的工作原理如第1圖所示，在印刷電路板(PCB)上，暫態電壓抑制器10並聯欲保護裝置12，當ESD情況發生時，暫態電壓抑制器10係瞬間被觸發，同時，暫態電壓抑制器10亦可提供一低電阻路徑，以供暫態之ESD電流進行放電，讓ESD暫態電流之能量透過暫態電壓抑制器10得以釋放。
第2圖為先前技術之二維之具有TVS之系統封裝(System-in-Package,SiP)。此系統封裝包含一功能性晶片14與一暫態電壓抑制(TVS)晶片16，其係安裝於一晶粒銲盤(die paddle)18。功能性晶片14與TVS晶片16藉由銲線連接接腳(lead)20。在此二維封裝中，L1與L2是銲線之寄生電感。假使L1小於L2，則經過TVS晶片16之靜電放電電流之阻抗(ωL)將大於功能性晶片14之阻抗。在系統級ESD應力下，功能性晶片14在TVS晶片16導通前，會先受到ESD電流的傷害。所以，ESD保護設計在功能性晶片14中仍然是必須的。此外，TVS整合於IC晶片中是傳統技術。當TVS的崩潰電壓或輸入寄生電容需要被改變時，同時需要改變IC的複雜製程，進而改變製程成本，且可能降低功能性晶片之性能。
因此，本發明係在針對上述的困擾，提出一種三維積體電路封裝，以解決習知所產生的問題。
本發明的主要目的，在於提供一種三維積體電路封裝，其係經由導電栓安裝一積體電路(IC)晶片與一暫態電壓抑制(TVS)晶片在一封裝基板上，以避免形成銲線電感以降低TVS晶片之保護能力，其中此IC晶片可以或無法抑制一暫態電壓。此外，IC晶片與TVS晶片可以使用不同製程技術，使TVS晶片之電特性容易調整，並節省製作成本。
為達上述目的，本發明提供一種三維積體電路封裝，其係包含具有一表面之一封裝基板，此表面上設有彼此電性連接之至少一積體電路晶片與至少一暫態電壓抑制晶片，其中此積體電路晶片可以或無法抑制一暫態電壓，且積體電路晶片與暫態電壓抑制晶片互相獨立。互相堆疊之 積體電路晶片與暫態電壓抑制晶片設於封裝基板之表面上，或者，積體電路晶片與暫態電壓抑制晶片一起透過一中介層設於封裝基板上。
茲為使貴審查委員對本發明的結構特徵及所達成的功效更有進一步的瞭解與認識，謹佐以較佳的實施例圖及配合詳細的說明，說明如後：
10‧‧‧暫態電壓抑制器
12‧‧‧欲保護裝置
14‧‧‧功能性晶片
16‧‧‧暫態電壓抑制晶片
18‧‧‧晶粒銲盤
20‧‧‧接腳
22‧‧‧封裝基板
24‧‧‧積體電路晶片
26‧‧‧暫態電壓抑制晶片
28‧‧‧導電栓
30‧‧‧第一導電凸塊
32‧‧‧第二導電凸塊
34‧‧‧P型半導體基板
38‧‧‧P型井區
40‧‧‧第一P型重摻雜區
42‧‧‧第一N型重摻雜區
44‧‧‧N型井區
46‧‧‧第二P型重摻雜區
48‧‧‧第二N型重摻雜區
50‧‧‧積體電路晶片
52‧‧‧暫態電壓抑制晶片
54‧‧‧導電栓
56‧‧‧第二導電凸塊
58‧‧‧封裝基板
60‧‧‧積體電路晶片
62‧‧‧暫態電壓抑制晶片
64‧‧‧第一導電凸塊
66‧‧‧第二導電凸塊
68‧‧‧中介層
70‧‧‧第一導電栓
72‧‧‧第二導電栓
74‧‧‧第三導電凸塊
76‧‧‧第四導電凸塊
第1圖為先前技術之連接欲保護電路之暫態電壓抑制器的電路示意圖。
第2圖為先前技術之具有暫態電壓抑制器之二維系統封裝示意圖。
第3圖為本發明之第一實施例之結構示意圖。
第4圖為本發明之第一實施例之三維積體電路封裝電性連接高電壓端、低電壓端與輸入輸出接腳之示意圖。
第5圖為本發明之第一實施例之暫態電壓抑制晶片之結構示意圖。
第6圖為本發明之第二實施例之結構示意圖。
第7圖為本發明之第二實施例之三維積體電路封裝電性連接高電壓端、低電壓端與輸入輸出接腳之示意圖。
第8圖為本發明之第三實施例之結構示意圖。
第9圖為本發明之第三實施例之三維積體電路封裝電性連接高電壓端、低電壓端與輸入輸出接腳之示意圖。
本發明利用暫態電壓抑制晶片整合於三維積體電路封裝 中，將系統級靜電放電保護能力嵌入於積體電路晶片裡。
以下介紹本發明之第一實施例，請參閱第3圖與第4圖。第一實施例包含一封裝基板22，其係具有一表面。至少一暫態電壓抑制(TVS)晶片26與至少一積體電路(IC)晶片24依序堆疊於封裝基板22之表面上，且彼此電性連接，其中積體電路晶片24可以或無法抑制一暫態電壓。積體電路晶片24與暫態電壓抑制晶片26互相獨立。此暫態電壓抑制晶片26僅具有靜電放電(ESD)功能，且不包含記憶體、類比電路、數位電路及/或射頻(RF)電路。在第一實施例中，係以一個暫態電壓抑制晶片26與一個積體電路晶片24為例。TVS晶片26中設有複數個導電栓28，例如直通矽晶穿孔元件(through-silicon-via devices,TSV)。複數個第一導電凸塊30設於封裝基板22之表面的導電區域，每一第一導電凸塊30分別位於每一導電栓28下方，使TVS晶片26經由第一導電凸塊30與導電栓28電性連接上述導電區域。另有複數個第二導電凸塊32，每一第二導電凸塊32分別位於每一導電栓28上，且IC晶片24位於第二導電凸塊32上，使IC晶片24經由第一導電凸塊30、第二導電凸塊32與導電栓28電性連接上述導電區域與TVS晶片26。第一導電凸塊30與第二導電凸塊32之材質為鉛或錫，導電栓28之材質為銅。此外，其中一導電栓28連接一高電壓端VDD，另一導電栓28連接一低電壓端VSS，其餘導電栓28連接輸入輸出接腳(I/O pins)。
TVS晶片26之結構係以第5圖為例，但並不限於此結構。請參閱第5圖，TVS晶片26更包含一P型半導體基板34，且導電栓28係設於P型半導體基板34中。P型半導體基板34中設有一P型井區38與一N型井區44，且一第一P型重摻雜區40與一第一N型重摻雜區42設於P型井區38中，一第二P 型重摻雜區46與一第二N型重摻雜區48設於N型井區44中。導電栓28、P型井區38與N型井區44彼此獨立。此外，有一導電栓28連接一高電壓端VDD，另一導電栓28連接一低電壓端VSS，其餘導電栓28連接輸入輸出接腳。
以下介紹本發明之第二實施例。請參閱第6圖與第7圖。第二實施例包含一封裝基板22，其係具有一表面。至少一積體電路(IC)晶片50與至少一暫態電壓抑制(TVS)晶片52依序堆疊於封裝基板22之表面上，且彼此電性連接，其中積體電路晶片50可以或無法抑制一暫態電壓。積體電路晶片50與暫態電壓抑制晶片52互相獨立。此暫態電壓抑制晶片52僅具有靜電放電(ESD)功能，且不包含記憶體、類比電路、數位電路及/或射頻(RF)電路。在第二實施例中，係以一個暫態電壓抑制晶片52與一個積體電路晶片50為例。積體電路晶片50中設有複數個導電栓54，例如直通矽晶穿孔元件(through-silicon-via devices,TSV)。封裝基板22之表面的導電區域上設有複數個第一導電凸塊30，每一第一導電凸塊30分別位於導電栓54下方，使積體電路晶片50經由第一導電凸塊30與導電栓54電性連接上述導電區域。每一導電栓54上設有一第二導電凸塊56，且積體電路晶片54設於第二導電凸塊56上，使暫態電壓抑制晶片54經由第一導電凸塊30、第二導電凸塊56與導電栓54電性連接上述導電區域與積體電路晶片50。第一導電凸塊30與第二導電凸塊56之材質為鉛或錫，導電栓54之材質為銅。此外，其中一導電栓54連接一高電壓端VDD，另一導電栓54連接一低電壓端VSS，其餘導電栓54連接輸入輸出接腳(I/O pins)。
因為暫態電壓抑制晶片與不具有靜電放電保護設計之積體電路晶片互相獨立，所以可以輕易調整暫態電壓抑制晶片之電特性，此可 降低製作成本。此外，利用導電栓，暫態電壓抑制晶片與積體電路晶片可以互相電性連接，以避免銲線電感之形成。
基於相同的優點，以下介紹本發明之第三實施例，請參閱第8圖與第9圖。第三實施例包含一封裝基板58，其係具有一表面。至少一積體電路(IC)晶片60與至少一暫態電壓抑制(TVS)晶片62設於封裝基板58之表面上，且彼此電性連接，其中積體電路晶片60可以或無法抑制一暫態電壓。積體電路晶片60與暫態電壓抑制晶片62互相獨立。此暫態電壓抑制晶片62僅具有靜電放電(ESD)功能，且不包含記憶體、類比電路、數位電路及/或射頻(RF)電路。在第三實施例中，係以一個暫態電壓抑制晶片62與一個積體電路晶片60為例。封裝基板58之表面的導電區域上設有複數個第一導電凸塊64與複數個第二導電凸塊66，且第一導電凸塊64彼此相鄰，第二導電凸塊66彼此相鄰。另有一中介層(interposer)68設於第一導電凸塊64與第二導電凸塊66上，中介層68係具有複數個第一導電栓70與複數個第二導電栓72，且每一第一導電栓70分別設於每一第一導電凸塊64上，每一第二導電栓72分別設於每一第二導電凸塊66上。第一導電栓70與第二導電栓72係以直通矽晶穿孔元件(through-silicon-via devices,TSV)為例。每一第一導電栓70上分別設有每一第三導電凸塊74，且暫態電壓抑制晶片62位於第三導電凸塊74上。每一第二導電栓72上分別設有每一第四導電凸塊76，且積體電路晶片60設於第四導電凸塊76上。積體電路晶片60經由上述導電區域、第一導電栓70、第二導電栓72、第一導電凸塊64、第二導電凸塊66、第三導電凸塊74與第四導電凸塊76電性連接暫態電壓抑制晶片62。第一導電凸塊64、第二導電凸塊66、第三導電凸塊74與第四導電凸塊76之 材質為鉛或錫，第一導電栓70與第二導電栓72之材質為銅。此外，有一第一導電栓70連接一高電壓端VDD，另一第一導電栓70連接一低電壓端VSS，其餘第一導電栓70連接輸入輸出接腳，且一第二導電栓72連接一高電壓端VDD，另一第二導電栓72連接一低電壓端VSS，其餘第二導電栓72連接輸入輸出接腳(I/O pins)。
綜上所述，本發明使用不同製程製作積體電路晶片與暫態電壓抑制晶片，以降低製作成本。此外，本發明亦可解決形成寄生電感之問題。
22‧‧‧封裝基板
24‧‧‧積體電路晶片
26‧‧‧暫態電壓抑制晶片
28‧‧‧導電栓
30‧‧‧第一導電凸塊
32‧‧‧第二導電凸塊

Claims (3)

  1. 一種三維積體電路封裝，包含：一封裝基板，其係具有一表面，且至少一積體電路(IC)晶片與至少一暫態電壓抑制(TVS)晶片設於該表面上，且彼此電性連接，該積體電路晶片與該暫態電壓抑制晶片互相獨立；複數個導電栓，其係設於該暫態電壓抑制晶片中；複數個第一導電凸塊，其係設於該表面之導電區域上，且每一該第一導電凸塊分別位於每一該導電栓下方，該暫態電壓抑制晶片經由該些第一導電凸塊與該些導電栓電性連接該導電區域；以及複數個第二導電凸塊，每一該第二導電凸塊分別位於每一該導電栓上，且該積體電路晶片經由該些第一導電凸塊、該些第二導電凸塊與該些導電栓電性連接該導電區域與該暫態電壓抑制晶片；其中該暫態電壓抑制晶片更包含：一P型半導體基板，該些導電栓係設於該P型半導體基板中；一P型井區，其係設於該P型半導體基板中，且一第一P型重摻雜區與一第一N型重摻雜區設於該P型井區中；以及一N型井區，其係設於該P型半導體基板中，且一第二P型重摻雜區與一第二N型重摻雜區設於該N型井區中，又該P型井區與該N型井區彼此獨立。
  2. 如請求項1所述之三維積體電路封裝，其中該些第一導電凸塊與該些第二導電凸塊之材質為鉛或錫，該些導電栓之材質為銅。
  3. 如請求項1所述之三維積體電路封裝，其中一該導電栓連接一高電壓端， 另一該導電栓連接一低電壓端，其餘該導電栓連接輸入輸出接腳(I/O pins)。
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