CN103779303A - 凸点式封装及其形成方法 - Google Patents

凸点式封装及其形成方法 Download PDF

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Publication number
CN103779303A
CN103779303A CN201310631177.7A CN201310631177A CN103779303A CN 103779303 A CN103779303 A CN 103779303A CN 201310631177 A CN201310631177 A CN 201310631177A CN 103779303 A CN103779303 A CN 103779303A
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China
Prior art keywords
salient point
solder layer
type surface
salient
contact pad
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CN201310631177.7A
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English (en)
Inventor
K·C·吴
T·H·林
M-T·王
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN103779303A publication Critical patent/CN103779303A/zh
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Abstract

本发明涉及凸点式封装及其形成方法。根据本发明的实施例，半导体封装包括半导体芯片和凸点。半导体芯片具有主表面上的接触垫。凸点被置于半导体芯片的接触垫上。焊料层被置于凸点的侧壁上。

Description

凸点式封装及其形成方法
技术领域
本发明一般涉及半导体封装，以及更特别地涉及凸点式封装及其形成方法。
背景技术
半导体器件被用于多种电子设备及其他应用中。半导体器件可包括在半导体晶片上形成的集成电路。替代地，半导体器件可被形成为单片器件，例如，分立器件。通过在半导体晶片上沉积多种类型的材料的薄膜、对材料的薄膜进行图案化、对半导体晶片的选择性区域进行掺杂等等，来在半导体晶片上形成半导体器件。
在传统的半导体制造过程中，大量半导体器件在单个晶片中被制造。在器件级和互连级制造过程完成后，晶片上的半导体器件被分离。例如，晶片可经历分割(singulation)。在分割期间，晶片被机械和／或化学处理，并且半导体器件被物理分离，以形成各个管芯。各个管芯随后根据封装规格而被封装。封装设计的示例包括薄的小型无引线封装、嵌入式晶片级球栅阵列封装、以及其他。
发明内容
通过本发明的说明性实施例，通常解决或规避了这些以及其他问题，以及通常实现了技术优点。
根据本发明的实施例，半导体封装包括在主表面上具有接触垫的半导体芯片，置于所述接触垫上的凸点，以及置于所述凸点的侧壁上的焊料层。
根据本发明的替代实施例，半导体器件包括具有在第一主表面上的第一接触垫和在第二主表面上的第二接触垫的半导体芯片，置于所述第一接触垫上的磁性凸点，以及置于所述第二接触垫上的非磁性的凸点。
根据本发明的实施例，一种形成半导体封装的方法包括：在衬底中形成多个芯片。所述衬底具有第一主表面上的多个第一接触部和第二主表面上的多个第二接触部。提供包括多个凸点的凸点框架。所述凸点框架被附着到所述衬底的第一主表面。所述衬底被分割以形成各个单元。
附图说明
为了更完整地理解本发明及其优点，现在对结合附图进行的以下描述做出参考，在附图中：
图1包括图1A-1C，图示出了根据本发明的实施例的半导体封装，其中，图1A图示了横截面视图，以及图1B和图1C图示了顶部截面图；
图2包括图2A-2D，图示出了根据本发明的实施例的第一凸点框架的形成；
图3包括图3A-3D，图示出了根据本发明的实施例的第二凸点框架的形成；
图4图示出了根据本发明的实施例的制造之后的半导体器件；
图5图示出了根据本发明的实施例的在半导体封装的制造期间的定位过程；
图6图示出了根据本发明的实施例的将凸点附着到衬底期间半导体封装的横截面视图；
图7图示出了根据本发明的实施例的将带层从凸点框架移除后的半导体封装的横截面视图；
图8图示出了根据本发明的实施例的分割之后的半导体封装的横截面视图；
图9图示出了根据本发明的实施例在带和卷轴上封装的多个半导体芯片；
图10图示出了根据本发明的替代实施例的在形成包括多个芯片的重构晶片后的半导体器件的横截面视图；
图11图示出了根据本发明的替代实施例的在将第一凸点框架和第二凸点框架附着到重构晶片后的半导体器件的横截面视图；
图12图示出了根据本发明的替代实施例的将具有凸点框架的重构晶片切割后的半导体器件的横截面视图；
图13图示出了根据本发明的另外的替代实施例的半导体封装，其中凸点未完全覆盖重分配层；
图14图示出了另外的替代实施例，其中，每个半导体封装包括嵌入在绝缘材料中的单个芯片；以及
图15图示出了另外的替代实施例，其中，凸点包括多个凹槽，以改善焊点(solder joint)区域。
除非另有指示，否则不同附图中对应的数字和符号一般指代对应的部件。附图被绘制成清楚地图示实施例的相关方面，并且不一定按比例绘制。
具体实施例
下面详细讨论各种实施例的制造和使用。然而，应当理解的是，本发明提供了多种可适用的发明性概念，其可被体现在广泛的具体情境中。所讨论的具体实施例仅是对制造和使用本发明的具体方式的说明，而并不限制本发明的范围。
将使用图1来描述本发明的结构实施例。另外的结构实施例将通过使用图12-15进行描述。一种形成半导体器件的方法将通过使用图2-9进行描述。形成半导体器件的替代实施例将通过使用图10-12、13、14和15进行描述。
图1包括图1A-1C，图示出了根据本发明的实施例的半导体封装。图1A图示了横截面视图，以及图1B和图1C图示了顶部截面图。
参照图1A，半导体芯片50包括第一主表面上的第一接触垫310和相对的第二主表面上的第二接触垫320。在一个或多个实施例中，半导体芯片50可包括分立的半导体芯片。替代地，在一些实施例中，半导体芯片50可包括集成电路芯片。在一个或多个实施例中，半导体芯片50可包括分立器件，诸如二极管、晶体管、晶闸管、电容器、电感器及其他。在各种实施例中，半导体芯片50可包括功率半导体器件，在一个实施例中，其可以是分立器件。在一个实施例中，半导体芯片50可包括两端子器件，诸如PIN二极管或肖特基二极管。在一个或多个实施例中，半导体芯片50是三端子器件，诸如功率金属绝缘体半导体场效应晶体管(MISFET)、结型场效应晶体管(JFET)、双极结型晶体管(BJT)、以及绝缘栅双极晶体管(IGBT)、或半导体晶闸管。
第一接触垫310和第二接触垫320可包括被配置为形成与半导体芯片50的焊料接触的垫。第一凸点110被置于半导体芯片50的第一接触垫310上，而第二凸点210被置于第二接触垫320上。在各种实施例中，第一凸点110和第二凸点210可包括与半导体芯片50相同的横截面尺寸。替代地，第一凸点110和第二凸点210可包括小于半导体芯片50的横截面尺寸但大于对应的第一接触垫310或第二接触垫320的横截面尺寸。
如图1A和1B中所图示，第一凸点110包括第一凸点材料130和置于第一凸点材料130周围的第一焊料层120。在一个或多个实施例中，第一焊料层120被置于第一凸点材料130的所有四个侧壁上。另外，在一些实施例中，第一焊料层120可被置于第一凸点材料130的顶表面上，使得第一凸点110的所有五个表面都被第一焊料层120所覆盖。
类似地，第二凸点210包括具有第二焊料层220的第二凸点材料230，该第二焊料层220被置于第二凸点材料230上。第二焊料层220可覆盖第二凸点材料230的所有四个侧壁。与第一焊料层120类似，第二焊料层220可覆盖第二凸点材料230的所有五个表面。
如图1B和1C中所示，在一个实施例中，第一接触垫310和第二接触垫320可具有圆形或椭圆形的形状。在另一个实施例中，第一接触垫310和第二接触垫320可具有正方形或长方形的形状。在替代的实施例中，第一接触垫310和第二接触垫320可包括其他合适的形状。
在各种实施例中，第一凸点材料130可包括不同于第二凸点材料230的材料。在各种实施例中，第一凸点材料130包括铁磁材料，而第二凸点材料230包括非铁磁材料或非磁性材料。替代地，第一凸点材料130包括非铁磁材料或非磁性材料，而第二凸点材料230包括铁磁材料。在一个或多个实施例中，第一凸点材料130(或第二凸点材料230)的铁磁材料包括镍。在替代的实施例中，铁磁材料包括铁、铬、钴以及其他。本发明的各种实施例中所公开的铁磁材料和其他材料可以是纯金属、合金和混合物。在各种实施例中，纯金属(诸如纯铜)可包括痕量杂质。
在各种实施例中，第一焊料层120包括一种材料，其形成可焊接材料或替代地与焊料结合。因此，第一焊料层120可形成与焊料的焊料结合部，并可被附着到例如电路板。在一个或多个实施例中，第一焊料层120包括可与第一凸点材料130混合的材料，以形成可焊接材料。类似地，第二焊料层220可包括形成可焊接材料的材料。在各种实施例中，第一焊料层120和第二焊料层220可包括金、银、铂以及其他。在各种实施例中，第一焊料层120和第二焊料层220可包括锡(Sn)、锡-铅(SnPb)、镍、以及诸如锡合金、锌合金以及其他的合金。
本发明的实施例可具有常规封装设计的许多优点。例如，由于使用本发明的实施例形成的焊点将是外部可见的，所以本发明的实施例可以能够进行自动光学检查。
通过提供五个表面(至少四个)用于连接，本发明的实施例改善了焊点区域。另外，所有表面均是可焊接，这消除了在特定方向上对准芯片的任何要求。另外，通过允许选择焊接材料(例如，第一焊料层120的材料，以及其他)方面的灵活性，本发明的实施例提供了很大的灵活性。
通过使用颜色编码，本发明的实施例提供了识别垫的极性的能力。例如，第一焊料层120的颜色可与第二焊料层220的颜色不同。在一个实施例中，第一焊料层120可通过使用金而具有金色，而第二焊料220可通过使用银而具有银色。
由于在一侧上选择性使用铁磁材料，本发明的实施例能够易于处理散装芯片。此外，本发明的实施例不对比例施加限制。因此，可形成远小于目前设计的封装，而无需成本结构上的显著改变。
图2-9图示出了根据本发明的实施例的制造的各种阶段期间的半导体装置。
在各种实施例中，三个单独的组件可例如在并行或不同的设施中被制造。两个单独的凸点框架和包括半导体芯片的衬底可被制造。替代地，凸点框架可被直接沉积在衬底的正面和背面上。
图2包括图2A-2D，图示出了根据本发明的实施例的第一凸点框架的形成。图3包括图3A-3D，图示出了根据本发明的实施例的第二凸点框架的形成。
参照图2A和3A，第一凸点材料130可被置于第一载体10上，以及类似地，第二凸点材料230可被置于第二个载体20上。接下来参照图2B，第一凸点材料130可被图案化以形成第一凸点110。在一个实施例中，第一凸点材料130可在光刻过程后通过湿式蚀刻而被图案化。替代地，可使用其他技术来形成图案化的凸点结构。类似地，第二凸点材料230可被图案化以形成第二凸点210(图3B)。
参照图2C，第一焊料层120被形成于第一凸点材料130上。在一个或多个实施例中，第一焊料层120被电镀。在替代的实施例中，第一焊料层120可使用其他技术来沉积，例如，在一个实施例中，第一焊料层120可被喷射到第一凸点材料130上。类似地，第二焊料层220被形成于第二凸点材料230上(图3C)。
如接下来在图2D中所图示的，将第一凸点框架105从第一载体10移除并置于第一带100上。特别地，第一凸点框架105被翻转，使得第一凸点材料130一直背对第一带100。类似地，将第二凸点框架205从第二载体20移除并置于第二带200上。
图4图示出了根据本发明的实施例的制造后的半导体器件。
图4可以是在一个或多个实施例中的所有处理完成后的晶片。如图4中所图示，形成包括多个接触部的衬底300。如图4的横截面视图中所图示的，衬底300包括多个半导体芯片50。衬底300包括具有多个第一接触垫310的第一主表面和具有多个第二接触垫320的相对的第二主表面。
图5图示出了根据本发明的实施例的在半导体封装的制造期间的定位过程。
第一凸点框架105被反转，使得第一凸点材料130面对衬底300的第一主表面。特别地，多个第一接触垫310中的每一个均面对第一凸点框架105的第一凸点110。类似地，多个第二接触垫320中的每一个均面对第二凸点框架205的第二凸点210。
图6图示出了根据本发明的实施例的将凸点附着到衬底期间的半导体封装的横截面视图。
参考图6，第一凸点110被附着到衬底300的顶表面301，而第二凸点210被附着到衬底300的底表面302。在各种实施例中，通过施加压强和／或热，第一凸点110被附着到衬底300。例如，第一带100可被压缩以增加第一凸点材料130和第一接触垫310之间的界面处的压强。在各种实施例中，第一接触垫310和第一凸点材料130包括可焊性材料。例如，在一个或多个实施中，第一接触垫310的材料可与第一凸点材料130组合，以形成共熔固体溶体。类似地，在另一个实施例中，第二接触垫320的材料和第二凸点材料230可组合以形成不同的共熔固体溶体。因此，衬底300和第一凸点110可被加热，以便在第一凸点110和第一接触垫310之间形成焊点。在各种实施例中，衬底300和第一凸点框架105可被加热至100℃以上。在替代的实施例中，衬底300和第一凸点框架105可被加热到约100℃至约400℃。在另外的替代实施例中，衬底300和第一凸点框架105可被加热到约250℃至约350℃。在另外的替代实施例中，例如，在银的烧结过程中，衬底300和第一凸点框架105可被加热到约150℃至约250℃。替代地，在一些实施例中，在可使用摩擦结合的地方可使用超声连接过程。
类似地，通过施加压强和／或热来将第二凸点210附着到衬底300。例如，第二带200可被压缩以增加第二凸点材料230和第二接触垫320之间的界面处的压强。另外，衬底300和第二凸点210可被加热，例如，相对于第一凸点框架105的连接如上所述，以便在第二凸点210和第二接触垫320之间形成焊点。在各种实施例中，压强可同时被施加到第一带100和第二带200上。
在各种实施例中，第一凸点框架105、衬底300和第二凸点框架205可被同时结合在一起。在替代的实施例中，第一凸点框架105、衬底300和第二凸点框架205可被顺序地结合。
图7示出了根据本发明的实施例的从凸点框架移除带层后的半导体封装的横截面视图。
参考图7，第一带层100和第二带层200被移除。因此，第一凸点110和第二凸点210的顶表面上的第一焊料层120和第二焊料层220被暴露。
图8图示出了根据本发明的实施例的分割后的半导体封装的横截面视图。
如由虚线所图示的，衬底300可通过切割通道而被分割。在一个或多个实施例中，在分割之前，具有半导体封装的衬底300可被放置在箔片上。替代地，如图9中将描述的，半导体封装可在分割后被放置在箔片上。在一个实施例中，分割可被机械地执行，例如，使用砂轮。在替代实施例中，分割可被化学地执行，例如，使用各向异性蚀刻过程。在另外的实施例中，可使用激光过程来执行分割。在各种实施例中，可使用机械、化学、和／或激光过程的组合来执行分割。第一凸点110和第二凸点210表现为保护底层衬底300的蚀刻掩模。因此，在分割后，芯片50被生成，如果它们是以松散形式的，则芯片50也被成为散装。散装芯片50如果被生产则随后可以各种方式被封装。替代地，各个芯片50在其正被处理时可保持附着到带上。
图9图示出了根据本发明的实施例的在带和卷轴上封装的多个半导体芯片。
分割的芯片50可被馈送到分拣机中，诸如碗式送料器(bowlfeeder)处理机。常规上，碗式送料器处理机可执行进一步的测试(通常是基本功能测试)，并顺序地将芯片50附着到带上。
常规上，分离的芯片被单独挑选、测试，并且良好的(无缺陷)单元在封装期间被放置到载体带(或其他合适的衬底)上。然而，这样的过程是耗时的，并可能成为整个生产的瓶颈。
有利地，使用本发明的实施例，由于第一凸点110和第二凸点210在磁性质上的差异，分拣机可以容易地区分芯片50的顶面和底面。类似地，在另一实施例中，第一凸点110和第二凸点210之间的光学差异可被用来区分芯片50的不同接触部。因此，参照图9，芯片50被放置在带和卷轴层400上。
在本发明的各种实施例中，有利地，测试可被执行为批量过程。如果在切割前芯片50被放置在分割箔片上，批量测试可被直接执行。替代地，在一个实施例中，测试可在将芯片50附着到带之后使用批量处理来执行。换言之，在各种实施例中，可使用晶片测试过程代替顺序测试每个芯片50。
在各种实施例中，芯片50被如此放置，使得所有的第一凸点110面朝上。在替代实施例中，芯片50被如此放置，使得所有的第二凸点210背对带和卷轴层400而面朝上。在各种实施例中，使用磁性分拣过程可促进芯片50的放置。在各种实施例中，所有第一凸点110或所有第二凸点210是磁性的。在一个实施例中，通过使用第一凸点110的磁性质，所有第一凸点110可在一个方向上取向。因此，磁性分拣机可使用磁性凸点来抬起芯片50。
图10-13图示出了根据本发明的替代实施例的制造的各种阶段期间的半导体器件的横截面视图。
本发明的实施例也可被应用到包括一个以上半导体芯片的半导体封装。
图10图示出了根据本发明的替代实施例的形成包括多个芯片的重构晶片后的半导体器件的横截面视图。
参照图10，形成了包括第一芯片51、第二芯片52和第三芯片53的重构晶片500。在各种实施例中，第一芯片51、第二芯片52、以及第三芯片53可以是不同或相同类型的芯片，并且可以在不同的过程和设施中被形成。例如，在一个实施例中，第一芯片51和第三芯片53可包括分立的功率半导体芯片，而第二芯片52可以包括集成电路芯片。在其他实施例中，第一芯片51、第二芯片52和第三芯片53包括分立的垂直半导体芯片。第一芯片51、第二芯片52和第三芯片53被嵌入在密封剂510内，以形成重构晶片500。在各种实施例中，多个第一芯片51、多个第二芯片52和多个第三芯片53在密封剂510内被形成。
图11图示出了根据本发明的替代实施例的在将第一凸点框架和第二凸点框架附着到重构晶片后的半导体器件的横截面视图。
在一个或多个实施例中，前侧和后侧重分配层可被形成在重构晶片500之上或之下。第一重分配层505被形成在重构晶片500上。可通过第一重分配金属线520来耦合第一接触垫310。例如，第一接触垫310中在第一芯片51处的一个垫可被耦合到第一接触垫310中在第二芯片52处的另一个垫。类似地，通过第二重分配层515中的第二重分配金属线540来耦合重构晶片500的相对侧上的第二接触垫320。
如先前相对于图6所描述的，第一凸点框架105被附着到第一接触垫310，而第二凸点框架205被附着到第二接触垫320。在各种实施例中，可通过焊点将第一凸点110附着到第一接触垫310。类似地，可通过焊点将第二凸点210附着到第二接触垫320。如先前所描述的，第一凸点框架105和第二凸点框架205可使用压力和／或热能来被附着。
此外，第一凸点110可被焊接到一个以上的第一接触垫310。例如，结果，通过公共的第一凸点110，第一芯片51上的垫可被耦合到第二芯片52上的垫。类似地，第三芯片53上的垫可被耦合到第二芯片52上的垫。因此，通过另一公共的第一凸点110，第二芯片52和第三芯片53可被耦合。类似地，第二凸点210可被焊接到一个以上的第二接触垫320。
在各种实施例中，有利地，在重构晶片500上正确地定位第一凸点框架105(第二凸点框架205)确保了第一凸点110(第二凸点210)的适当定位。
图12图示出了根据本发明的替代实施例的将具有凸点框架的重构晶片分割后的半导体器件的横截面视图。
重构晶片500被分割以形成包括多个芯片的半导体封装。在各种实施例中，可使用机械、化学、和／或激光过程的组合来执行分割。如在先前的实施例中那样，如果使用湿式蚀刻来执行，第一凸点110和第二凸点210可为分割过程提供蚀刻掩模。替代地，在一些实施例中，重构晶片500可被机械地分割。在另外的实施例中，可使用激光过程，诸如二氧化碳激光过程，或在一些实施例中甚至使用隐形激光过程，来分割重构晶片500。
图13图示出了另外的替代实施例，其中，凸点未完全覆盖重分配层。
在此实施例中，第一凸点110可以不覆盖第一芯片51上的第一接触垫310和第二芯片52上的第一接触垫310。而是，通过包括第一重分配金属线520的第一重分配层505，来耦合这些接触垫。类似地，通过第二重分配层515中的第二重分配金属线540，来耦合重构晶片500的相对侧上的第二接触垫320。
图14图示出了另外的替代实施例，其中，每个半导体封装包括与上述相对于图10-12所描述的实施例不同的单个芯片。因此，在图14中，芯片50被密封剂510所密封，而第一凸点110和第二凸点210被形成在密封的芯片50的上方和下方。
图15图示出了另外的替代实施例，其中，凸点包括多个凹槽以改善焊点区域。
在各种实施例中，第一凸点110和第二凸点210可包括诸如第一凹槽125或第二凹槽225的图案。在各种实施例中，由于用来沉积这些焊料层的电镀过程的适形性质，第一凸点材料130或第二凸点材料230上的凹槽或图案可被转移到第一焊料层120或第二焊料层220上。这些图案可被用于增加第一凸点110和／或第二凸点210的表面面积。结果，由于更大的焊点区域，半导体封装可在更好的粘合的情况下被焊接到电路板。
虽然已参照说明性实施例对本发明进行了描述，但该描述不意在以限制意义被解释。在参考描述时，说明性实施例以及本发明的其他实施例的各种修改和组合，将对本领域技术人员来说是显而易见的。作为说明，图1-15中所描述的实施例可在各种实施例中相互组合。因此，意在的是，所附权利要求涵盖任何此类修改或实施例。
虽然已经详细描述了本发明及其优点，但应该理解的是，在不脱离如由所附权利要求所限定的本发明的精神和范围的情况下，此处可做出各种改变、替换和变更。例如，本领域技术人员将容易地理解的是，此处所描述的特征、功能、过程以及材料中的许多可以被改变，同时仍在本发明的范围内。
此外，本申请的范围不意在被限于说明书中所描述的过程、机器、制造、物质的组成、装置、方法和步骤的特定实施例。如本领域普通技术人员从本发明的公开内容将容易理解的，可根据本发明来利用与本文所描述的对应实施例基本上执行相同功能或基本上实现相同结果的当前存在的或以后将开发的过程、机器、制造、物质的组成、装置、方法和步骤。因此，所附权利要求意在将这样的过程、机器、制造、物质的组成、装置、方法和步骤包括在其范围内。

Claims (31)

1.一种半导体封装，包括：
第一半导体芯片，具有第一主表面上的第一接触垫；
第一凸点，被置于所述第一接触垫上；以及
第一焊料层，被置于所述第一凸点的侧壁上。
2.如权利要求1所述的封装，其中，所述第一焊料层被置于所述第一凸点的所有四个侧壁和顶表面上。
3.如权利要求1所述的封装，其中，所述第一凸点包括铁磁材料。
4.如权利要求3所述的封装，其中，所述铁磁材料包括镍、钴、铬和／或铁。
5.如权利要求1所述的封装，其中，所述第一焊料层包括金、银、铂、锡、镍、锡铅、和／或锌合金。
6.如权利要求1所述的封装，其中，所述第一半导体芯片包括分立的垂直晶体管。
7.如权利要求1所述的封装，进一步包括置于所述第一半导体芯片周围的密封剂。
8.如权利要求1所述的封装，进一步包括：
第二凸点，置于所述第一半导体芯片的第二接触垫上，所述第二接触垫被置于与所述第一主表面相对的第二主表面上，以及
第二焊料层，被置于所述第二凸点的侧壁上。
9.如权利要求8所述的封装，其中，所述第一焊料层被置于所述第一凸点的所有四个侧壁和顶表面上，以及其中，所述第二焊料层被置于所述第二凸点的所有四个侧壁和顶表面上。
10.如权利要求8所述的封装，其中，所述第二凸点是与所述第一凸点不同的材料。
11.如权利要求8所述的封装，其中，所述第一凸点包括铁磁材料，并且其中，所述第二凸点包括非磁性材料。
12.如权利要求11所述的封装，其中，所述非磁性材料包括铜、银和／或金。
13.如权利要求8所述的封装，进一步包括：
密封剂，被置于所述第一半导体芯片周围；以及
第二半导体芯片，其紧接所述第一半导体芯片被置于所述密封剂中，其中所述第二半导体芯片包括所述第一主表面上的第三接触垫和所述第二主表面上的第四接触垫。
14.如权利要求13所述的封装，进一步包括：
第三凸点，被置于所述第三接触垫上；
第三焊料层，被置于所述第三凸点的侧壁上；
第四凸点，被置于所述第四接触垫上；以及
第四焊料层，被置于所述第四凸点的侧壁上。
15.如权利要求14所述的封装，其中，所述第三焊料层被置于所述第三凸点的所有四个侧壁和顶表面上，以及其中，所述第四焊料层被置于所述第四凸点的所有四个侧壁和顶表面上。
16.一种半导体器件，包括：
半导体芯片，具有第一主表面上的第一接触垫和第二主表面上的第二触垫；
磁性凸点，被置于所述第一接触垫上；以及
非磁性凸点，被置于所述第二接触垫上。
17.如权利要求16所述的器件，进一步包括：
第一焊料层，被置于所述磁性凸点的侧壁上；
第二焊料层，被置于所述非磁性凸点的侧壁上。
18.如权利要求17所述的器件，其中，所述第一焊料层被置于所述磁性凸点的所有四个侧壁和顶表面上。
19.如权利要求18所述的器件，其中，所述第二焊料层被置于所述非磁性凸点的所有四个侧壁和顶表面上。
20.如权利要求16所述的器件，其中，所述磁性凸点包括镍、钴、铬和／或铁，以及其中所述非磁性凸点包括铜、银和／或金。
21.一种形成半导体封装的方法，所述方法包括：
在衬底中形成多个芯片，所述衬底具有第一主表面上的多个第一接触部，以及第二主表面上的多个第二接触部；
提供包括多个第一凸点的第一凸点框架；
将所述第一凸点框架与所述衬底的第一主表面附着；以及
分割所述衬底以形成各个单元。
22.如权利要求21所述的方法，进一步包括：
提供包括多个第二凸点的第二凸点框架；以及
将所述第二凸点框架与所述衬底的所述第二主表面附着。
23.如权利要求22所述的方法，其中，所述多个第一凸点包括铁磁材料，以及其中，所述多个第二凸点包括非磁性材料。
24.如权利要求21所述的方法，其中，提供所述第一凸点框架包括在所述多个第一凸点的所有四个侧壁上形成多个第一凸点以及形成第一焊料层。
25.如权利要求21所述的方法，其中，将所述第一凸点框架与所述衬底的第一主表面附着包括在所述多个第一凸点和所述第一主表面上的多个第一接触部之间形成焊料结合部。
26.如权利要求21所述的方法，其中，分割所述衬底包括湿式蚀刻所述衬底。
27.如权利要求21所述的方法，进一步包括：使用磁性送料器来将各个单元附着到带上。
28.一种形成半导体封装的方法，所述方法包括：
形成包括多个芯片的重构晶片，所述重构晶片具有第一主表面上的多个第一接触部，以及第二主表面上的多个第二接触部；
提供包括多个第一凸点的第一凸点框架；
提供包括多个第二凸点的第二凸点框架；
将所述第一凸点框架与所述重构晶片的第一主表面附着；
将所述第二凸点框架与所述重构晶片的第二主表面附着；以及
分割所述重构晶片以形成各个单元。
29.如权利要求28所述的方法，其中，所述多个第一凸点包括铁磁材料，以及其中所述多个第二凸点包括非磁性材料。
30.如权利要求28所述的方法，其中，提供第一凸点框架包括在所述多个第一凸点的所有四个侧壁上形成多个第一凸点以及形成第一焊料层。
31.如权利要求28所述的方法，其中，将所述第一凸点框架与所述重构晶片的第一主表面附着包括在所述多个第一凸点和所述第一主表面上的多个第一接触部之间形成焊料结合部。
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