CN101436575A - 半导体封装件及其安装方法 - Google Patents
半导体封装件及其安装方法 Download PDFInfo
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- CN101436575A CN101436575A CNA2008101740332A CN200810174033A CN101436575A CN 101436575 A CN101436575 A CN 101436575A CN A2008101740332 A CNA2008101740332 A CN A2008101740332A CN 200810174033 A CN200810174033 A CN 200810174033A CN 101436575 A CN101436575 A CN 101436575A
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Abstract
本发明公开了一种通过增强印刷电路板和表面安装封装件的粘合强度来提高可靠性的半导体封装件和安装方法,该半导体封装件包括其上设置有半导体器件的芯片焊盘及引线端子,其中,引线端子和芯片焊盘中的至少一个具有多个槽。因此,与典型的封装件相比,因为多个槽形成在封装件的粘合到印刷电路的芯片焊盘和引线端子上,所以扩大了封装件和膏状焊料的粘合面积,从而可以提高抗剪强度,并可以获得更大的焊点可靠性。
Description
技术领域
本发明的多个方面涉及一种通过增强印刷电路板和表面安装封装件之间的粘合强度来提高可靠性的半导体封装件和安装方法。
背景技术
通常使用的表面安装封装件包括J形引线小外形(SOJ)型表面安装封装件和特殊用途的链齿状双排脚封装件(ZIP)表面安装封装件。此外,有一种适用于标准化存储卡的薄小外形封装(TSOP)型表面安装封装件。
采用镀金的镍来形成典型的表面安装封装件,且典型的表面安装封装件被构造成具有芯片焊盘和引线端子,其中,半导体器件将粘合在芯片焊盘上,引线端子用于将该封装件电连接到外部器件。因为半导体器件和引线端子包括粘合带或者粘合剂,所以它们用导线电连接。此外,为了保护半导体器件免于由外部热影响和外部机械冲击或外部化学冲击导致的任何损坏,通过形成用环氧模塑化合物(EMC)模塑的包络单元(enveloping ),来完成封装件。
为了将典型的底部引线塑料封装件(BLP)安装在印刷电路板(PCB)上,将膏状焊料涂覆在PCB上,从而接触BLP的芯片焊盘和端子,并对PCB和设置在PCB上的BLP施加热。因此,膏状焊料熔化并硬化,所以最终将封装件安装在PCB上。
发明内容
根据本发明的多个方面,一种半导体封装件具有其上设置有半导体器件的芯片焊盘,并具有引线端子,其中,引线端子和芯片焊盘中的至少一个包括多个槽。
根据本发明的一方面,半导体器件可通过导线连接到引线端子。根据本发明的一方面,芯片焊盘可由覆有金的镍制成。根据本发明的一方面,所述槽可沿着一个方向延伸地形成。
根据本发明的一方面,所述槽可具有网状。根据本发明的一方面,所述槽具有矩阵形状。根据本发明的一方面,当形成芯片焊盘和引线端子时,形成所述槽;或者在完成半导体封装件之后,形成所述槽。
根据本发明的另一方面,一种方法包括以下步骤:提供具有端子的印刷电路板;将膏状焊料涂覆在印刷电路板的端子上;将具有芯片焊盘和引线端子的半导体封装件设置在印刷电路板上,引线端子和芯片焊盘具有多个槽;通过将半导体封装件和印刷电路板压制在一起,迫使膏状焊料进入所述多个槽中;通过硬化膏状焊料,使半导体封装件粘合到印刷电路板上。
根据本发明的另一方面,一种半导体封装件包括:半导体器件;芯片焊盘,在芯片焊盘上设置有所述半导体器件;引线端子,通过相应的导线电连接到半导体器件;包络单元,其中,除了引线端子和芯片焊盘中的每个的被暴露于外部的表面之外,包络单元被模塑成包络半导体器件、芯片焊盘和引线端子,芯片焊盘和引线端子包括形成在芯片焊盘的暴露的表面和引线端子的暴露的表面上的多个槽。
根据本发明的另一方面,一种半导体封装件的安装方法包括以下步骤:提供具有端子的印刷电路板;将膏状焊料涂覆在印刷电路板的端子上;将半导体封装件设置在印刷电路板上,半导体封装件包括半导体器件、芯片焊盘、引线端子和包络单元,其中,半导体器件设置在芯片焊盘上,引线端子通过相应的导线电连接到半导体器件,除了引线端子和芯片焊盘中的每个的被暴露于外部的表面之外,包络单元被模塑成包络半导体器件、芯片焊盘和引线端子,芯片焊盘和引线端子包括形成在芯片焊盘的暴露的表面和引线端子的暴露的表面上的多个槽,芯片焊盘和引线端子与印刷电路板的端子对准;通过将半导体封装件和印刷电路板压制在一起,迫使膏状焊料进入所述多个槽中;通过硬化膏状焊料,使半导体封装件粘合到印刷电路板上。
本发明另外的方面和/或优点将在下面的描述中被部分地阐述,通过所述描述将部分地清楚,或者可通过实践本发明而获知。
附图说明
通过以下结合附图对本发明的多个方面进行的描述,本发明的这些和/或其他方面及优点将变得清楚且更易于理解,在附图中:
图1A是示出根据本发明一方面的半导体封装件的结构的平面图;
图1B是图1A的半导体封装件的侧面前视图;
图1C至图1E是本发明的在图1A的芯片焊盘和引线端子中形成的槽的外观;
图2A至图2D是示出根据本发明一方面的半导体封装件的安装方法的示图。
具体实施方式
现在将对本发明的多个方面做出详细描述,附图中示出了本发明多个方面的示例,其中,相同的标号始终表示相同的元件。以下参照附图来描述这些方面,以解释本发明。图1A是示出根据本发明一方面的半导体封装件的结构的平面图,图1B是图1A的半导体封装件的侧面前视图。参照图1A和图1B,封装件100可包括:芯片焊盘110,半导体器件120设置在芯片焊盘110上;多个引线端子130,向外部连接半导体器件120;导线140,将半导体器件120电连接到引线端子130。芯片焊盘110可由覆有金的镍制成。
通过采用粘合带或者粘合剂将半导体器件120和引线端子130本身固定,来使半导体器件120和引线端子130彼此电连接。此外,为了保护半导体器件120免于由热影响或外部机械冲击或外部化学冲击导致的任何损坏,通过形成用环氧模塑化合物(EMC)模塑的包络单元150,来完成封装件。
如图1B所示,除了芯片焊盘110和多个引线端子130中的每个上的一个表面之外,包络单元150可被形成为完全包络半导体器件120、其上设置有半导体器件120的芯片焊盘110的大部分以及多个引线端子130的大部分。在本发明的多个方面中,芯片焊盘110的未被包络的表面和多个引线端子130的未被包络的表面基本上共面,并且暴露于外部。
如图1B所示,多个槽160可分别形成在芯片焊盘110的表面上以及引线端子130的表面上,从而通过获得可用于粘合的增大的粘合(或表面)面积来提高其抗剪强度。如图1C所示,槽160可以沿着一个方向延伸地形成;如图1D所示,槽160可以形成为网状;或者如图1E所示,槽160可以形成为矩阵形状。如图1B所示,其上形成有多个槽160的表面基本上共面。
此外,在本发明的多个方面中,槽160的形状或截面轮廓可以按所期望地形成。也就是说,槽160的边缘可以形成为直角(如图1B所示)和曲面中的一种。在本发明的多个方面中,槽160也可以为其它形状,例如三角形或棱锥形。
在本发明的如图1C所示的槽160沿着一个方向延伸地形成的外观中,槽160的截面形状可以勾勒出方波图案的外形(如图1B所示),或者可以勾勒出三角波、正弦波或其它波图案。在这样的情况下,槽160的周期性可以是规则的,使得每个槽160之间的间隔可以相等,虽然这不是所要求的。因此,可以按照不规则的间隔或按照任何期望的间隔来形成槽160。
图1D示出了槽160的网状布置,图1E示出了槽160的矩阵形状的布置。也就是说,图1D示出了一组槽160垂直于另一组槽160延伸的布置,图1E示出了不连续地延伸的槽160的布置。虽然在图1D中的槽160之间形成方形的岸区,由图1E中的槽160形成方形的凹进,但这不是所要求的,可以由槽160形成的岸或凹进的形状可以是圆形、六边形、三角形或其它形状。
因此,本领域技术人员应该理解,在不脱离本发明的精神和范围的情况下,可以就这里的这些方面对槽160做出各种修改和改变。
在本发明的多个方面中,槽160可以形成在引线端子130和芯片焊盘110中的至少一个上(即,在芯片焊盘110上,在引线端子130上,或者在芯片焊盘110和引线端子130上)。此外,例如,可以在形成芯片焊盘110和引线端子130时形成槽160,或者可在芯片焊盘110和引线端子130上模塑环氧模塑化合物(EMC)从而完成封装件100之后形成槽160。因此,应该理解的是,为了在封装件的制造工艺中更加方便地且容易地形成槽160,可以相应地选择形成槽的时序。
另外,在本发明的多个方面中,将膏状焊料填充在槽160中。因此,可以扩大或增大粘合面积,从而可以提高芯片焊盘110和/或引线端子130相对于印刷电路板的抗剪强度,因此可以获得更大的焊点可靠性。
图2A至图2D是示出根据本发明多个方面的半导体封装件的安装方法的示图。图2A示出了在将印刷电路板300粘合到封装件100之前涂覆在PCB端子310上的膏状焊料200,其中,PCB端子310形成在印刷电路板(PCB)300上。
如图2A所示,例如,封装件100可包括芯片焊盘110和引线端子130。芯片焊盘110和引线端子130可具有在印刷电路板300所粘合到的表面上的多个槽160。例如,芯片焊盘110和引线端子130通过PCB端子310粘合到印刷电路板300。
图2B示出了为了将封装件100粘合到印刷电路板300而将封装件100设置在印刷电路板300上。这里,芯片焊盘110和引线端子130可分别被设置在PCB端子310和膏状焊200上,同时紧密接触。芯片焊盘110和引线端子130与印刷电路板300的端子310对准。
图2C示出了将封装件100粘合到印刷电路板300。这里,通过用热来熔化膏状焊料200,并将封装件100和印刷电路板300压制在一起,可使膏状焊200流到形成在封装件100的芯片焊盘110和引线端子130上的槽160中。
另外,一旦膏状焊料200硬化,根据本发明多个方面的填充到或侵入到槽160中的膏状焊200就使芯片焊盘110和/或引线端子130的岸部分(land)与膏状焊200连结(interlockmg),从而增大封装件100相对于印刷电路板300的抗剪强度。
在不同的方面中,“至少一个”表示从可用的元件中选择的替换物,从而包括元件中的一个或多个。例如,如果可用的元件包括元件X、Y和Z,则“至少一个”表示X、Y、Z或它们的任何组合。
虽然已经示出和描述了本发明的几个方面,但是本领域技术人员应该理解,在不脱离本发明的原理和精神的情况下,可以对这些方面做出修改,本发明的范围限定在权利要求及其等同物中。
Claims (24)
1、一种半导体封装件,包括:
芯片焊盘,在芯片焊盘上设置有半导体器件;
引线端子,其中,引线端子和芯片焊盘中的至少一个包括多个槽。
2、如权利要求1所述的半导体封装件,其中,半导体器件通过导线连接到引线端子。
3、如权利要求1所述的半导体封装件,其中,芯片焊盘由覆有金的镍制成。
4、如权利要求1所述的半导体封装件,其中,所述槽沿着一个方向延伸地形成。
5、如权利要求1所述的半导体封装件,其中,所述槽具有网状。
6、如权利要求1所述的半导体封装件,其中,所述槽具有矩阵形状。
7、如权利要求1所述的半导体封装件,其中,当形成芯片焊盘和引线端子时,形成所述槽。
8、如权利要求1所述的半导体封装件,其中,在完成半导体封装件之后,形成所述槽。
9、如权利要求1所述的半导体封装件,其中,半导体封装件还包括用于覆盖芯片焊盘和引线端子的包络单元。
10、一种半导体封装件的安装方法,包括以下步骤:
提供具有端子的印刷电路板;
将膏状焊料涂覆在印刷电路板的端子上;
将具有芯片焊盘和引线端子的半导体封装件设置在印刷电路板上,引线端子和芯片焊盘中的至少一个具有多个槽;
通过将半导体封装件和印刷电路板压制在一起,迫使膏状焊料进入所述多个槽中;
通过硬化膏状焊料,使半导体封装件粘合到印刷电路板上。
11、如权利要求10所述的半导体封装件的安装方法,其中,将半导体器件设置在芯片焊盘上。
12、如权利要求10所述的半导体封装件的安装方法,其中,沿着一个方向延伸地形成所述槽。
13、如权利要求10所述的半导体封装件的安装方法,其中,以网状形成所述槽。
14、如权利要求10所述的半导体封装件的安装方法,其中,以矩阵形状形成所述槽。
15、如权利要求10所述的半导体封装件的安装方法,其中,由覆有金的镍形成芯片焊盘。
16、如权利要求10所述的半导体封装件的安装方法,其中,当形成芯片焊盘和引线端子时,形成所述槽。
17、如权利要求10所述的半导体封装件的安装方法,其中,在完成半导体封装件之后,形成所述槽。
18、如权利要求1所述的半导体封装件,其中,所述多个槽包括在熔化的同时被迫进入所述多个槽中的硬化的膏状焊料。
19、一种半导体封装件,包括:
半导体器件;
芯片焊盘,在芯片焊盘上设置有所述半导体器件;
引线端子,通过相应的导线电连接到半导体器件;
包络单元,其中,除了引线端子和芯片焊盘中的每个的被暴露于外部的表面之外,包络单元被模塑成包络半导体器件、芯片焊盘和引线端子,芯片焊盘和引线端子包括形成在芯片焊盘的暴露的表面和引线端子的暴露的表面上的多个槽。
20、如权利要求19所述的半导体封装件,其中,所述多个槽包括在熔化的同时被迫进入所述多个槽中的硬化的膏状焊料。
21、如权利要求19所述的半导体封装件,其中,芯片焊盘的暴露的表面和引线端子的暴露的表面共面。
22、如权利要求19所述的半导体封装件,还包括硬化的膏状焊料,其中,所述多个槽增大硬化的膏状焊料能够利用的表面积,从而提高半导体封装件的抗剪强度和焊点可靠性。
23、一种半导体封装件的安装方法,包括以下步骤:
提供具有端子的印刷电路板;
将膏状焊料涂覆在印刷电路板的端子上;
将半导体封装件设置在印刷电路板上,半导体封装件包括半导体器件、芯片焊盘、引线端子和包络单元,其中,半导体器件设置在芯片焊盘上,引线端子通过相应的导线电连接到半导体器件,除了引线端子和芯片焊盘中的每个的被暴露于外部的表面之外,包络单元被模塑成包络半导体器件、芯片焊盘和引线端子,芯片焊盘和引线端子包括形成在芯片焊盘的暴露的表面和引线端子的暴露的表面上的多个槽,芯片焊盘和引线端子与印刷电路板的端子对准;
通过将半导体封装件和印刷电路板压制在一起,迫使膏状焊料进入所述多个槽中;
通过硬化膏状焊料,使半导体封装件粘合到印刷电路板上。
24、如权利要求23所述的安装方法,其中,芯片焊盘的暴露的表面和引线端子的暴露的表面共面。
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-
2007
- 2007-11-12 KR KR1020070114898A patent/KR100984132B1/ko not_active IP Right Cessation
-
2008
- 2008-02-28 JP JP2008048152A patent/JP2009124095A/ja active Pending
- 2008-09-23 US US12/235,739 patent/US8319319B2/en not_active Expired - Fee Related
- 2008-11-12 EP EP08168935.8A patent/EP2058856A3/en not_active Withdrawn
- 2008-11-12 CN CN2008101740332A patent/CN101436575B/zh not_active Expired - Fee Related
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CN102347304A (zh) * | 2010-07-29 | 2012-02-08 | Nxp股份有限公司 | 具有改进的可安装性的无引线芯片载体 |
US9418919B2 (en) | 2010-07-29 | 2016-08-16 | Nxp B.V. | Leadless chip carrier having improved mountability |
CN103779303A (zh) * | 2012-10-18 | 2014-05-07 | 英飞凌科技股份有限公司 | 凸点式封装及其形成方法 |
CN104021413A (zh) * | 2013-02-28 | 2014-09-03 | 英飞凌科技股份有限公司 | 芯片布置和用于制造芯片布置的方法 |
CN104659010A (zh) * | 2015-02-11 | 2015-05-27 | 江苏长电科技股份有限公司 | 一种四方扁平无引脚型态封装的引线框结构与封装体结构 |
CN106714451A (zh) * | 2016-12-19 | 2017-05-24 | 长沙牧泰莱电路技术有限公司 | 一种复合式印刷电路板及其制作方法 |
CN108987557A (zh) * | 2018-07-04 | 2018-12-11 | 佛山市国星半导体技术有限公司 | 一种倒装led芯片及其制作方法、led器件 |
CN109904125A (zh) * | 2019-03-06 | 2019-06-18 | 西安航思半导体有限公司 | 耐高温qfn封装结构的制备方法 |
CN109904124A (zh) * | 2019-03-06 | 2019-06-18 | 西安航思半导体有限公司 | 具有防短路功能的qfn封装结构 |
CN113015324A (zh) * | 2019-12-19 | 2021-06-22 | 华为技术有限公司 | 电路板组件、电子设备、加工电路板组件的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101436575B (zh) | 2010-10-13 |
US8319319B2 (en) | 2012-11-27 |
KR100984132B1 (ko) | 2010-09-28 |
KR20090048833A (ko) | 2009-05-15 |
EP2058856A2 (en) | 2009-05-13 |
EP2058856A3 (en) | 2014-08-27 |
JP2009124095A (ja) | 2009-06-04 |
US20090121362A1 (en) | 2009-05-14 |
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