CN104733417A - 半导体芯片及其制造方法 - Google Patents

半导体芯片及其制造方法 Download PDF

Info

Publication number
CN104733417A
CN104733417A CN201410674233.XA CN201410674233A CN104733417A CN 104733417 A CN104733417 A CN 104733417A CN 201410674233 A CN201410674233 A CN 201410674233A CN 104733417 A CN104733417 A CN 104733417A
Authority
CN
China
Prior art keywords
semiconductor chip
electrode
chip
conductive projection
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410674233.XA
Other languages
English (en)
Inventor
K·J·古德诺
R·S·格拉夫
C·R·奥格尔维
S·T·文特朗
C·S·伍德鲁夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN104733417A publication Critical patent/CN104733417A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29387—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开涉及一种半导体芯片及其制造方法。导热层沉积在半导体芯片的晶片的第一表面上。刻蚀导热层以形成在每个半导体芯片的第一表面上暴露贯通电极的过孔。导电凸块沉积在每个半导体芯片的第二表面上的贯通电极上。堆叠半导体芯片，其中半导体芯片中的第二半导体芯片的导电凸块通过半导体芯片中的第一半导体芯片的过孔电接触第一半导体芯片的贯通电极，以及半导体芯片中的第三半导体芯片的导电凸块通过第二半导体芯片的过孔电接触第二半导体芯片的贯通电极。

Description

半导体芯片及其制造方法
技术领域
本发明涉及一种半导体芯片及其制造方法。本发明也涉及一种这种芯片的封装体以及用于制造或组装该封装体的方法。
背景技术
如图1所示，半导体芯片100具有表面110，表面110具有用于连接至芯片100的电路装置的导电凸块124。提供导热板130以用于设置在表面110上，如图2所示。板130形成了对应于凸块120的过孔140，其中旨在使得凸块120并未接触或者更恶劣地与板130重叠。然而，在凸块120与板130之间避免接触和重叠需要合适的对准。如图2所示，板130的小量未对准可能导致板130与一个或多个凸块120之间的接触。
本发明的目的、优点和创新特征列出在以下描述中，并且从以下描述以及通过实践本发明，对于本领域技术人员将变得明显，其中通过在所附权利要求中指出的内容可以获得该目的、优点和特征。
发明内容
根据本发明的一个或多个实施例，一种半导体封装体包括衬底，该衬底具有第一表面、与第一表面相对的第二表面、以及设置在第二表面上的第一键合焊盘。封装体进一步包括第一半导体芯片，第一半导体芯片具有面向衬底的第二表面的第三表面、与第三表面相对的第四表面、以及在第三表面和第四表面之间延伸的第一贯通电极。第一贯通电极中的相应第一贯通电极对应于并且电连接至第一键合焊盘中的相应第一焊盘。第一导热层被镀制到第四表面上，由此提供第五表面。
在另一方面中，第一绝缘层形成在第一导热层的第五表面上，由此提供第六表面，其中第一导热层和第一绝缘层形成第一过孔，第一过孔中的相应第一过孔围绕第一贯通电极中的相应第一贯通电极。此外，封装体包括第二半导体芯片，第二半导体芯片具有面向第一半导体芯片的第一绝缘层的第六表面的第七表面、与第七表面相对的第八表面、以及在第七表面和第八表面之间延伸的第二贯通电极，其中第二贯通电极中的相应第二贯通电极对应于第一半导体芯片的第一贯通电极中的相应第一贯通电极，并且具有通过第一过孔至第一半导体芯片的第一贯通电极中的相应第一贯通电极的电连接。
根据本发明的一个或多个实施例，提供半导体芯片的封装体的方法包括在半导体芯片的晶片的第一表面上镀制导热层，晶片具有与第一表面相对的第二表面。晶片的第一表面和第二表面为每个半导体芯片提供第一相对表面和第二相对表面，以及其中对晶片的第一表面的镀制由此镀制相应半导体芯片的第一表面。方法进一步包括在导热层上形成绝缘层以及刻蚀导热层，其中每个半导体芯片具有在半导体芯片的第一表面和第二表面之间延伸的贯通电极，并且刻蚀包括刻蚀暴露每个半导体芯片的第一表面上的贯通电极的过孔。
在附加的方面，在每个半导体芯片的第二表面上在贯通电极上沉积导电凸块。从晶片划切半导体芯片，并且堆叠半导体芯片中的第一半导体芯片、第二半导体芯片和第三半导体芯片，其中第二半导体芯片的导电凸块通过第一半导体芯片的过孔电接触第一半导体芯片的贯通电极，以及第三半导体芯片的导电凸块通过第二半导体芯片的过孔电接触第二半导体芯片的贯通电极。
根据本发明的一个或多个实施例，方法包括将第一半导体芯片放置在衬底上，衬底具有第一表面、与第一表面相对的第二表面、以及在第二表面上的第一键合焊盘，其中第一半导体芯片具有第三表面、与第三表面相对的第四表面、在第三表面和第四表面之间延伸的第一贯通电极、以及在第三表面上的导电凸块。
在另一方面中，将第一半导体芯片放置在衬底上包括：放置第一半导体芯片以使得第一半导体芯片的相应导电凸块接触第一键合焊盘中的相应第一键合焊盘。此外，方法包括将第一半导体芯片的相应导电凸块附接至第一键合焊盘中的相应第一键合焊盘。将第二半导体芯片放置在第一半导体芯片上，其中第一半导体芯片进一步具有被镀制到第四表面上的第一导热层，由此提供第五表面，并且第一半导体芯片进一步具有形成在第一导热层的第五表面上的第一绝缘层，由此提供第六表面。
在另一方面，第一导热层和第一绝缘层形成第一过孔，第一过孔中的相应第一过孔暴露第一半导体芯片的第一贯通电极中的相应第一贯通电极，其中第二半导体芯片具有第七表面、与第七表面相对的第八表面、在第七表面和第八表面之间延伸的第二贯通电极、以及在第七表面上的导电凸块。将第二半导体芯片放置在第一半导体芯片上包括：放置第二半导体芯片以使得第二半导体芯片的相应导电凸块通过第一过孔与第一半导体芯片的贯通导体中的相应贯通导体电接触。
此外，方法包括将第二半导体芯片附接至第一半导体芯片，以使得第二半导体芯片的相应导电凸块保持通过第一过孔与第一半导体芯片的贯通导体中的相应贯通导体的固定电接触。
附图说明
本发明的确信为典型的创新性特征列出在所附权利要求中。然而，当结合附图阅读时通过参照示意性实施例的以下详细描述将最佳地理解本发明自身以及优选使用模式、其另外目的和优点，其中：
图1示出了根据现有技术的半导体芯片表面以及用于放置其上的导热板。
图2示出了根据现有技术的与在半导体芯片上设置导热板有关的对准问题。
图3A至图3F示出了根据本发明一个或多个实施例的在制造阶段中半导体芯片的结构并且示出了这些阶段的相关处理动作。
图3G提供了根据本发明一个或多个实施例的图3F的半导体芯片的一侧的视图。
图3H示出了根据本发明一个或多个实施例的图3F的半导体芯片的一侧的视图，其中层被分离为多个部分。
图4A至图4D示出了根据本发明的一个或多个实施例的在制造或组装阶段中半导体芯片封装体的结构并且示出了这些阶段的相关处理动作。
图4E示出了根据本发明的一个或多个实施例的图4A至图4D中所示封装体的半导体芯片之一的附加细节。
图5示出了根据本发明一个或多个实施例的利用了粘附膜的半导体芯片封装体。
图6示出了根据本发明的一个或多个实施例的利用了导电柱的半导体芯片封装体。
具体实施方式
为了说明的目的，在本文中呈现了对本发明的各个实施例的描述，但并非意在穷举或者限定与所公开的实施例。许多修改和改变对于本领域技术人员而言是明显的，而没有脱离所描述的实施例的范围和精神。选择在本文中使用的术语以最佳地解释实施例的原理、实际应用或者对于市场上找到技术的技术改进，或者使得本领域技术人员理解在本文中所公开的实施例。
在本文中所描述的方法方面用于制造集成电路芯片。得到的集成电路芯片可以由制造商分散为未加工晶片形式(也即作为具有多个未封装芯片的单个晶片)，作为裸片，或者以已封装的形式。在后者情形中，芯片安装在单个芯片封装体中(诸如塑料载体，具有贴至母板或其他更高层级载体的引线)或者在多芯片封装体中(诸如具有单面或双面互连或埋设互连的陶瓷载体)。在任何情形中，芯片随后与其他芯片、分立电路元件和/或其他信号处理装置集成，作为(a)诸如母板之类的中间产品或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，范围从玩具和其他低端应用至具有显示器、键盘或其他输入装置、以及中央处理器的先进计算机产品。
为了提供半导体芯片的封装体，根据本发明的实施例，如图3A至图3G所示制造个体半导体芯片。如图3A所示，提供完整厚度的晶片302，其可以包括诸如硅之类的一种或多种材料。例如，200mm晶片可以是725um厚，而300mm晶片可以是775um厚。晶片302具有第一表面330以及与表面330相对的第二表面332。可以具有基本上均匀的例如直径接近5至100um的圆截面的窄通道304形成在表面330或332中的一个表面上，并且向内延伸，也即朝向表面330或332中的另一个表面延伸，诸如形成在表面300上朝向表面332延伸10至100um，如由图3A所示的一个或多个实施例中所示。通道304可以包括一种或多种导电材料，诸如铜或钨，并且可以诸如通过刻蚀过孔以及沉积由绝缘材料所围绕的导电材料而形成。
如图3B所示，随后减薄晶片302，诸如减薄至10um至100um的厚度，以使得通道304暴露在表面332和表面330上，以提供从一个表面332全程延伸至另一表面332的导电硅通孔305。因此，硅通孔305的暴露端部形成了表面330和332的一部分。晶片302的减薄可以通过例如包括机械研磨或化学机械抛光的工艺来完成。
如图3C所示，导热层308形成在诸如图中所示表面中的一个表面(诸如表面332)上，其可以初始地覆盖硅通孔305，在硅通孔305中层308随后经由化学或等离子进行刻蚀以暴露过孔305。如图3G所示，刻蚀可以在导热层308中形成圆形过孔340。可以通过镀制包括铜、铝或类似导热材料的一种或多种材料而形成导热层308。电镀是执行镀制操作的一种方式。晶片302将最终被划切为个体半导体芯片。(换言之，将从晶片302划切半导体芯片。)因此，对晶片302的一个表面332的镀制由此镀制了从其划切的个体半导体芯片的表面中的一个表面。在图3A至图3G中仅示出了一个这样的芯片350。
本发明涉及如下认识：在表面332上镀制导热层308以及随后刻蚀过孔340以暴露硅通孔305允许更精确地控制过孔340相对于过孔305居中以及过孔340尺寸。如所示，硅通孔305可以直径均匀，以及开口340尽管更大但是可以对应地直径均匀。例如，对于5至100um直径的过孔305，导电层308中过孔340的直径可以是10至200um，也即过孔340可以近似过孔305的两倍尺寸。并且例如，刻蚀使得精确设置开口340，以使得每个开口340基本上在其相应硅通孔305的中心处，例如以1至5um精度在过孔305上居中。
如图3D所示，绝缘层312形成在刻蚀的导热层308上，例如诸如通过铜导热层308的氧化，其钝化了刻蚀的层308的铜。绝缘层312可以例如0.2至2um。在备选实施例中，可以在添加绝缘层312之后执行如上所述的过孔340的刻蚀。在本发明的一个或多个实施例中，其中上述刻蚀先于绝缘层312的形成，可以调整开口340的如上所述尺寸以导致添加层312，这使得开口340以基本上等于绝缘层312两倍厚度的因子在直径上更小。
如图3E所示，导电焊盘沉积在穿硅电极305的暴露端部上，也即在晶片302中每个芯片的表面330一侧上的导电焊盘320以及在表面332一侧上过孔340内的导电焊盘316(图3G)。导电焊盘316和320可以包括诸如铜、镍和金之类的一种或多种材料，并且可以通过诸如溅射和电镀之类的一种或多种工艺沉积至例如0.5至4um的厚度。过孔340内焊盘316可以在此称作“捕获焊盘”，因为它们提供了焊料可以回流并且与其接合以捕获放置在其上的半导体芯片的导电凸块的表面，如在下文中进一步所述。
尽管在图3G中示出了圆形焊盘316，但是焊盘316和320可以包括规则形状的焊盘、不规则形状的焊盘、或者规则和不规则形状的焊盘。同样地，尽管硅通孔305在平行于如图3G中的平面中可以具有圆形截面，但是过孔305可以包括规则形状的过孔、不规则形状的过孔、或者规则和不规则形状的过孔。例如，过孔例如可以是圆环形或条形。
导电凸块324沉积在导电焊盘320上，其在晶片302中每个半导体芯片的表面330的贯通电极305的暴露端部上，如图3F所示。凸块423可以包括一种或多种材料，诸如铅、铜、锡和银，并且可以通过诸如溅射和电镀之类的一种或多种工艺沉积至例如10至100um的厚度。这些焊料凸块可以包括附加的材料，称作凸块下金属层，其改进了焊料与晶片302之间的粘附。该凸块下金属层可以包括一种或多种材料，诸如钛、钨、铜和镍等。
如上文中针对图3A至图3G所述的动作导致了如图3F所示的半导体芯片350。应该知晓的是因为焊盘320、贯通电极305和焊盘316是导电的，根据芯片350的如上所述结构，半导体芯片350的导电凸块324与导电焊盘320、贯通电极305和导电焊盘316电接触，由此提供了穿过芯片350从一侧330至另一侧332的相应电路径。在本发明的一个或多个实施例中，焊盘316和320的一个或两个可以省略，而此时仍然维持了穿过芯片350的电路径。例如，导电凸块324可以直接形成在硅通孔305的导电材料上。
现在参照图4A至图4E，对于诸如图3F和图3G的芯片305之类的芯片而言，示出了根据本发明实施例的堆叠芯片的工艺和结构，其中图3F和图3G的半导体芯片350的第一个称作芯片350a，这些半导体芯片350的第二个称作芯片350b等等。同样地，图3F和图3G的半导体芯片350的各个部分在图4A至图4E中涉及由后缀“a”用于芯片350a、后缀“b”用于芯片350b等等。
概括地，由图4A至图4E所示的工艺和结构包括提供半导体芯片的第一半导体芯片350a并且在第一半导体芯片350a上堆叠半导体芯片的第二半导体芯片350b(图4C)。此外，在第二半导体芯片350b上堆叠半导体芯片的第三半导体芯片350c(图4D)等等。完成堆叠以使得第二半导体芯片350b的导电凸块324b通过第一半导体芯片350a的过孔340a电接触第一半导体芯片350a的贯通电极305a。也即，对于如图3F所示的其中导电焊盘316沉积在贯通电极305上的实施例，第二半导体芯片350b的导电凸块324b机械地接触第一半导体芯片350a的导电焊盘316a，其与第一半导体芯片350a的贯通电极305a、导电焊盘320a和导电凸块324a电接触。同样地，第三半导体芯片350c的导电凸块324c通过第二半导体芯片350b的过孔340b电接触第二半导体芯片350b的贯通电极305b等等。
同样概括地，图4A至图4E的示例包括将第一芯片的导电焊盘316a键合至第二芯片的导电凸块324b(图4C)，以及将第二芯片的导电焊盘316b键合至第三芯片的导电凸块324c等等(图4D)，其可以例如通过热压键合。备选地，键合例如可以是将一个芯片放置在另一芯片的顶部并且回流它们。此外，提供衬底402并且半导体芯片350a、350b、350c等等堆叠在衬底上。
现在参照图4E，示出了根据本发明一个或多个实施例的衬底402的细节。衬底402具有第一表面404，与第一表面404相对的第二表面406，设置在第一表面404上的键合表面410，以及设置在第二表面406上的键合表面412。如图4E所示，键合表面410和412具有不规则形状。然而，键合表面410可以具有规则形状、不规则形状、或者规则和不规则形状。同样地，键合表面412可以具有规则形状、不规则形状、或者规则和不规则形状。
衬底402包括核心，其第一和第二表面404和406是相对表面。键合表面410和412可以是涂覆焊料的铜，其中铜可以镀制在相应表面404和406上并且连接至镀铜贯通连接，例如连接414，其可以通过对穿过衬底402的孔来镀铜而形成，其中可以诸如通过激光或机械钻孔形成孔。衬底402也包括分别设置在键合表面410上的导电凸块408。
如图4D和图4E所示，所示的工艺可以进一步包括在衬底402上沉积键合焊盘412并且将第一芯片350a的导电凸块324a键合至键合焊盘412。衬底402的核心可以包括诸如纤维玻璃和树脂FR-4等等的一种或多种材料。衬底402可以是双层叠层，例如具有在顶部也即靠近表面406的铜布线层，以及在底部也即靠近表面404的另一铜布线层。衬底402可以包括附加的布线层以适应附加的布线复杂性。
特别地，图4A至图4E所示的工艺和结构包括在具有第一表面404、与第一表面404相对的第二表面406、以及在第二表面406上的键合焊盘412的衬底402上放置第一半导体芯片350a(图4A)。在该说明中，再次，图3F的半导体芯片350的第一个称作芯片350a，图3F的半导体芯片350的第二个称作芯片350b等等，并且图3F和图3G中所示半导体芯片350的各个部分涉及对于芯片350a的后缀“a”、对于芯片350b的后缀“b”等等。
第一半导体芯片350a具有第三表面330a，与第三表面330a相对的第四表面332a，在第三和第四表面330a和332a之间延伸的第一导电贯通电极305a，以及在第三表面330a上的导电凸块324a。在衬底402上放置第一半导体芯片350a(图4A)包括放置芯片350a以使得芯片350a的相应导电凸块324a接触键合焊盘412中的相应键合焊盘并且将相应导电凸块324a附接至键合焊盘412中的相应键合焊盘。
此外，第二半导体芯片350b放置在第一半导体芯片350a上(图4C)，其中芯片350a具有被镀制到第四表面332a上的第一导热层308a，由此提供了第五表面，以及芯片350a进一步具有形成在导热层/第五表面308a上的第一绝缘层312a，由此提供了第六表面。导热层308a和绝缘层312a形成了第一过孔340a，第一过孔340a中的相应第一过孔暴露了第一半导体芯片350a的第一贯通电极305a的相应第一贯通电极，其中第二半导体芯片350b具有第七表面330b、与第七表面330b相对的第八表面332b、在第七和第八表面330b和332b之间延伸的第二贯通电极305b、以及在第七表面330b上的导电凸块324b。
在第一半导体芯片350a上放置第二半导体芯片350b(图4C)包括放置第二半导体芯片350b以使得芯片350b的相应导电凸块324b通过第一过孔340a与第一半导体芯片的贯通导体305a中的相应贯通导体电接触。所公开的方法包括将第二半导体芯片350b附接至第一半导体芯片350a以使得第二芯片350b的相应导电凸块324b通过第一过孔340a保持与第一芯片的贯通导体305a中的相应贯通导体的固定电接触。
所公开的方法和结构进一步包括在第二半导体芯片350b上放置第三半导体芯片350c(图4D)，其中第二半导体芯片350b具有被镀制到第二半导体芯片350b的第八表面上的第二导热层308b，由此提供了第九表面，并且具有形成在第二导热层/第九表面308b上的第二绝缘层312b，由此提供了第十表面，其中第二导热层308b和第二绝缘层312b形成了第二过孔340b，第二过孔340b中的相应第二过孔围绕第二半导体芯片350b的第二贯通电极305b中的相应第二贯通电极。
第三半导体芯片350c具有第十一表面330c，与第十一表面330c相对的第十二表面332c，在第十一和第十二表面330c和332c之间延伸的第三贯通电极305c，以及在第十一表面332c上的导电凸块324c。在第二半导体芯片350b上放置第三半导体芯片350c包括放置第三芯片350c以使得第三芯片的导电凸块324c中的相应导电凸块与由第二过孔340b所暴露的第二半导体芯片的贯通电极305b中的相应贯通电极电接触。所公开的方法进一步包括将第三半导体芯片350c附接至第二半导体芯片350b，包括附接以使得第三半导体芯片的导电凸块324c中的相应导电凸块保持与由第二过孔340b所暴露的第二半导体芯片的贯通电极305b中的相应贯通电极固定电接触。
在一个或多个实施例中，第一半导体芯片350a进一步具有电连接至第一过孔340a中的相应第一贯通电极305a的相应导电焊盘316a，并且将第二半导体芯片350b附接至第一半导体芯片350a包括将第二芯片的导电凸块324b附接至第一半导体芯片的捕获焊盘316a中的相应捕获焊盘。此外，第二半导体芯片350b进一步具有电连接至第二过孔340b中的相应第二贯通电极305b的相应导电焊盘316b，并且将第三芯片350c附接至第二芯片350b包括将第三芯片的导电凸块324c附接至第二芯片的捕捉焊盘316b中的相应捕获焊盘。
在一个或多个实施例中，将第一芯片的导电凸块324a附接至衬底402的第一键合焊盘412中的相应第一键合焊盘、将第二芯片的导电凸块324b附接至第一芯片的捕获焊盘316a中的相应捕获焊盘以及将第三芯片的导电凸块324c附接至第二芯片的捕获焊盘316c中的相应捕获焊盘包括通过分别抵靠键合焊盘412和导电焊盘316a和316b热压缩导电凸块324a、324b和324c来附接。
在一个或多个实施例中，导电凸块324a具有焊料涂层，并且将第一芯片的导电凸块324a附接至衬底402的第一键合焊盘412中的相应第一键合焊盘、将第二芯片的导电凸块324b附接至第一芯片的捕获焊盘316a中的相应捕获焊盘以及将第三芯片的导电凸块324c附接至第二芯片的捕获焊盘316c中的相应捕获焊盘包括通过回流导电凸块324a、324b和324c的焊料来附接。
在一个或多个实施例中，所公开的方法和结构进一步包括在第一半导体芯片350a和衬底402之间施加底层填料420(图4B)，在半导体芯片350a和350b之间施加底层填料422(图4C)，在半导体芯片350b和350c之间施加底层填料424(图4D)等等。底层填料提供了芯片至芯片的粘附(对于芯片350b至芯片350a以及芯片350c至芯片350b等)以及芯片至衬底的粘附(对于芯片350a至衬底402)。底层填料可以包括诸如具有填充剂材料的环氧树脂的一种或多种材料，填充剂材料包括SiO2和其他材料。
在一个或多个实施例中，如图5所示，所公开的方法和结构进一步包括在放置芯片350a(图4A)、芯片350b(图4C)和350c(图4D)之前将相应的粘附材料膜512、514等施加至其上具有导电凸块324b和324c的相应表面330b和330c，以使得相应的膜提供了芯片至芯片粘附(用于芯片350b至芯片350a以及芯片350c至芯片350b等)并且在过孔340b内提供了空气间隙，也即在导电凸块324b和绝缘层312b之间、在导电凸块324c和绝缘层312c之间等等。在这些实施例中，如前所述可以由底层填料提供芯片至衬底粘附(用于芯片350a至衬底402)。
在一个或多个实施例中，如图6所示，例如，通过沉积铜柱形成贯通电极305。铜柱凸块324类似于传统的C4焊料凸块而被提供在电极305上，但是其中凸块金属层包括电镀或者类似沉积的铜至5um至50um的厚度，使得沉积在铜顶部上的焊料提供可以接合至下一层组件的表面。因为铜在比焊料更高的温度下回流，其提供了至凸块的附加支座，其可以改进可靠性和电性能。
现在参照图3F和图3H，并且在一个或多个实施例中，所公开的方法和结构包括诸如通过刻蚀来移除芯片350的导热层308的一部分以将层308分割为至少两个部分，诸如例如接地部分360以及源电压部分362，如所示情形中所述。也即，如图3H所示，层308的接地部分360和源电压部分362由已经移除的部分366所分隔。半导体芯片350的至少一个导电焊盘316连接至接地部分360，并且半导体芯片350的至少另一个导电焊盘316连接至源电压部分362。
尽管该说明书包含许多细节，但是其不应解释为限制可以请求保护的本发明的范围，而是相反地作为对于本发明特定实施方式的特征细节的描述说明。如上所述实施方式中各个部件的分隔不应理解为在所有实施方式中需要这种分隔。在独立的实施方式的上下文中在该说明书中描述的某些特征也可以在单个实施方式中组合实施。相反地，在单个实施方式的上下文中描述的各个特征也可以在多个实施方式中单独得实施或者以任何合适的子组合而实施。
此外，尽管特征如上可以被描述为以特定组合以及甚至如初始地请求保护的那样运作，但是来自请求保护的组合的一个或多个特征可以在一些情形中从组合分离，并且请求保护的组合可以引导至子组合或者子组合的变形。
权利要求中所述的动作可以以不同顺序执行并且至少在一些情形下仍然获得所需的结果。同样地，附图中所示的方法并非必需要求所示的特定顺序或依次顺序以获得所需结果，它们也无需执行所有所示操作以获得所需结果。
附图示出了根据本发明各个实施例的设备和方法的可能实施方式的体系结构、功能和操作。阅读了本公开的本领域技术人员将认识到可以不脱离本发明的范围而对实施例做出改变和修改。应该知晓的是在本文中所示和所述的特定实施方式是本发明的示意说明和其最佳模式，并且并非意在另外地以任何方式限制本发明的范围。其他变形也落入以下权利要求的范围内。
已经关于具体实施例如上描述了益处、其他优点以及对于问题的解决方案。然而，益处、优点、对于问题的解决方案、以及可以引起任何益处、优点或解决方案出现或者变得更明确的任何要素不应解释为任何或所有权利要求的关键性的或基本必需的特征或要素。
如在本文中使用的那样，术语包括、包含或其任何其他变形意在覆盖非排他性的包含，以使得包括了要素列表的过程、方法、制品或设备不仅包括这些要素而且还可以包括并未明确列出的或者对于这些过程、方法、制品或设备而言所固有的其他要素。此外，本发明的实施无需在本文中所述的要素，除非明确地描述作为基本的或者关键性的。
在本文中使用的术语仅是为了描述特定实施例的目的并且并非意在限定本发明。如在此使用的，单数形式“一”、“一个”和“该”意在也包括复数形式，除非上下文明确给出相反指示。应该进一步理解的是当在该说明书中使用时术语“包含”和/或“包括”指定了所述特征、整数、步骤、操作、要素和/或部件的存在，但是并非排除一个或多个其他特征、整数、步骤、操作、要素、部件和/或其群组的存在或添加。
以下权利要求中所有手段或步骤加上功能要素的对应的结构、材料、动作和等价形式意在包括用于执行如具体请求保护的与其他请求保护的要素相组合的功能的任何结构、材料或动作。
已经为了描述和说明的目的而呈现了本发明的说明书，但是并非意在穷举或者以所述形式限定于本发明。不脱离本发明的范围和精神的许多修改和变形对于本领域技术人员而言是明显的。选择并描述实施例以便于最佳地解释本发明的原理和实际应用，并且使得本领域技术人员对于适用于特定使用预期的各个修改例的各个实施例而理解本发明。

Claims (20)

1.一种半导体封装体，包括：
衬底，具有第一表面、与所述第一表面相对的第二表面、以及设置在所述第二表面上的第一键合焊盘；
第一半导体芯片，具有面向所述衬底的所述第二表面的第三表面、与所述第三表面相对的第四表面、以及在所述第三表面和所述第四表面之间延伸的第一贯通电极，其中所述第一贯通电极中的相应第一贯通电极对应于并且电连接至所述第一键合焊盘中的相应第一键合焊盘；
第一导热层，被镀制到所述第四表面上，由此提供第五表面；
第一绝缘层，形成在所述第一导热层的第五表面上，由此提供第六表面，其中所述第一导热层和所述第一绝缘层形成第一过孔，所述第一过孔中的相应第一过孔围绕所述第一贯通电极中的相应第一贯通电极；以及
第二半导体芯片，具有面向所述第一半导体芯片的所述第一绝缘层的所述第六表面的第七表面、与所述第七表面相对的第八表面、以及在所述第七表面和所述第八表面之间延伸的第二贯通电极，其中所述第二贯通电极中的相应第二贯通电极对应于所述第一半导体芯片的所述第一贯通电极中的相应第一贯通电极，并且具有通过所述第一过孔至所述第一半导体芯片的所述第一贯通电极中的相应第一贯通电极的电连接。
2.根据权利要求1所述的半导体封装体，包括：
第二导热层，被镀制到所述第二半导体芯片的所述第八表面上，由此提供第九表面；
第二绝缘层，形成在所述第二导热层的第九表面上，由此提供第十表面，其中所述第二导热层和第二绝缘层形成第二过孔，所述第二过孔中的相应第二过孔围绕所述第二半导体芯片的所述第二贯通电极中的相应第二贯通电极；以及
第三半导体芯片，具有面向所述第二绝缘层的所述第十表面的第十一表面、与所述第十一表面相对的第十二表面、以及在所述第十一表面和所述第十二表面之间延伸的第三贯通电极，其中所述第三贯通电极中的相应第三贯通电极具有通过所述第二过孔至所述第二半导体芯片的所述第二贯通电极中的相应第二贯通电极的电连接。
3.根据权利要求2所述的半导体封装体，包括：
第一导电凸块，键合至在所述第一半导体芯片的所述第三表面上的所述第一贯通电极中的相应第一贯通电极，其中所述第一半导体芯片的所述第一贯通电极至所述衬底的所述键合焊盘的电连接包括所述第一导电凸块至所述键合焊盘中的对应键合焊盘的键合；
第二导电凸块，键合至在所述第二半导体芯片的所述第七表面上的所述第二贯通电极中的相应第二贯通电极，其中所述第二半导体芯片的所述第二贯通电极至所述第一半导体芯片的所述第一贯通电极的电连接包括所述第二导电凸块通过所述第一过孔电接触至所述第一半导体芯片的所述第一贯通电极中的对应第一贯通电极的键合；
第三导电凸块，键合至在所述第二半导体芯片的所述第十一表面上的所述第三贯通电极中的相应第三贯通电极，其中所述第三半导体芯片的所述第三贯通电极至所述第二半导体芯片的所述第二贯通电极的电连接包括所述第三导电凸块通过所述第二过孔电接触至所述第二半导体芯片的所述第二贯通电极中的相应第二贯通电极的键合。
4.根据权利要求3所述的半导体封装体，其中，每个半导体芯片进一步具有电连接至所述半导体芯片的在每个贯通电极的相应过孔中的相应贯通电极的相应导电捕获焊盘。
5.根据权利要求3所述的半导体封装体，包括：
粘附材料膜，在所述半导体芯片的在其上具有所述导电凸块的相应表面上，其中相应的膜提供芯片至芯片以及芯片至衬底的粘附并且在所述导电凸块和所述过孔之间提供空气间隙。
6.根据权利要求3所述的半导体封装体，包括：
底层填料，在所述半导体芯片之间以及在所述第一半导体芯片与所述衬底之间，其中所述底层填料提供芯片至芯片以及芯片至衬底的粘附。
7.根据权利要求3所述的半导体封装体，其中，所述贯通电极包括铜柱。
8.根据权利要求3所述的半导体封装体，其中，在每个半导体芯片上的所镀制的导热层包括接地部分和源电压部分，其中每个半导体芯片的至少一个导电凸块连接至该半导体芯片的接地部分以及每个半导体芯片的一个导电凸块连接至该半导体芯片的源电压部分。
9.一种提供半导体芯片的封装体的方法，所述方法包括：
在半导体芯片的晶片的第一表面上镀制导热层，所述晶片具有与所述第一表面相对的第二表面，其中所述晶片的所述第一表面和所述第二表面为每个半导体芯片提供第一相对表面和第二相对表面，以及其中对所述晶片的所述第一表面的镀制由此镀制相应半导体芯片的所述第一表面；
在所述导热层上形成绝缘层；
刻蚀所述导热层，其中每个半导体芯片具有在所述半导体芯片的第一表面和第二表面之间延伸的贯通电极，并且所述刻蚀包括刻蚀过孔，所述过孔在每个半导体芯片的所述第一表面上暴露所述贯通电极；以及
在每个半导体芯片的所述第二表面上在所述贯通电极上沉积导电凸块；
从所述晶片划切所述半导体芯片；以及
堆叠所述半导体芯片中的第一半导体芯片、第二半导体芯片和第三半导体芯片，其中所述第二半导体芯片的所述导电凸块通过所述第一半导体芯片的所述过孔电接触所述第一半导体芯片的所述贯通电极，以及所述第三半导体芯片的所述导电凸块通过所述第二半导体芯片的所述过孔电接触所述第二半导体芯片的所述贯通电极。
10.根据权利要求9所述的方法，包括：
在每个半导体芯片的所述过孔内在所述贯通电极上沉积导电捕获焊盘；
在衬底上沉积键合焊盘；
在所述衬底上堆叠所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片；
将所述第一芯片的导电凸块键合至所述键合焊盘；以及
将所述第一半导体芯片的捕获焊盘键合至所述第二半导体芯片的导电凸块，以及将所述第二半导体芯片的捕获焊盘键合至所述第三半导体芯片的导电凸块。
11.一种方法，包括：
将第一半导体芯片放置在衬底上，所述衬底具有第一表面、与所述第一表面相对的第二表面、以及在所述第二表面上的第一键合焊盘，其中所述第一半导体芯片具有第三表面、与所述第三表面相对的第四表面、在所述第三表面和所述第四表面之间延伸的第一贯通电极、以及在所述第三表面上的导电凸块，以及其中将所述第一半导体芯片放置在所述衬底上包括：
放置所述第一半导体芯片以使得所述第一半导体芯片的相应导电凸块接触所述第一键合焊盘中的相应第一键合焊盘，
其中所述方法包括：
将所述第一半导体芯片的相应导电凸块附接至所述第一键合焊盘中的相应第一键合焊盘；
将第二半导体芯片放置在所述第一半导体芯片上，其中所述第一半导体芯片进一步具有被镀制到所述第四表面上的第一导热层，由此提供第五表面，并且所述第一半导体芯片进一步具有形成在所述第一导热层的第五表面上的第一绝缘层，由此提供第六表面，其中所述第一导热层和第一绝缘层形成第一过孔，所述第一过孔中的相应第一过孔暴露所述第一半导体芯片的所述第一贯通电极中的相应第一贯通电极，其中所述第二半导体芯片具有第七表面、与所述第七表面相对的第八表面、在所述第七表面和所述第八表面之间延伸的第二贯通电极、以及在所述第七表面上的导电凸块，以及其中将第二半导体芯片放置在所述第一半导体芯片上包括：
放置所述第二半导体芯片以使得所述第二半导体芯片的相应导电凸块通过所述第一过孔与所述第一半导体芯片的贯通导体中的相应贯通导体电接触，
其中所述方法包括：
将所述第二半导体芯片附接至所述第一半导体芯片，以使得所述第二半导体芯片的相应导电凸块保持通过所述第一过孔与所述第一半导体芯片的贯通导体中的相应贯通导体的固定电接触。
12.根据权利要求11所述的方法，包括：
将第三半导体芯片放置在所述第二半导体芯片上，其中所述第二半导体芯片具有被镀制到所述第二半导体芯片的所述第八表面上的第二导热层，由此提供第九表面，第二绝缘层形成在所述第二导热层的第九表面上，由此提供第十表面，其中所述第二导热层和第二绝缘层形成第二过孔，所述第二过孔中的相应第二过孔围绕所述第二半导体芯片所述的第二贯通电极中的相应第二贯通电极，其中所述第三半导体芯片具有第十一表面、与所述第十一表面相对的第十二表面、在所述第十一表面和所述第十二表面之间延伸的第三贯通电极、以及在第十一表面上的导电凸块，以及其中将所述第三半导体芯片放置在所述第二半导体芯片上包括：
放置所述第三半导体芯片以使得所述第三芯片的导电凸块中的相应导电凸块与由所述第二过孔暴露的所述第二半导体芯片的贯通导体中的相应贯通导体电接触，
其中所述方法进一步包括：
将所述第三半导体芯片附接至所述第二半导体芯片，包括附接以使得所述第三半导体芯片的导电凸块中的相应导电凸块保持与由所述第二过孔暴露的所述第二半导体芯片的贯通导体中的相应贯通导体的固定电接触。
13.根据权利要求11所述的方法，其中，所述方法包括将所述导热层镀制到所述半导体芯片的一个表面上，刻蚀以在所述导热层中形成所述过孔，以及在所述导热层上形成绝缘层。
14.根据权利要求12所述的方法，其中，所述第一半导体芯片进一步具有电连接至所述第一过孔中的相应第一贯通电极的相应导电捕获焊盘，以及其中将所述第二半导体芯片附接至所述第一半导体芯片包括：
将所述第二芯片的导电凸块附接至所述第一半导体芯片的捕获焊盘中的相应捕获焊盘；以及
其中，所述第二半导体芯片进一步具有电连接至所述第二过孔中的相应第二贯通电极的相应导电捕获焊盘，以及其中将所述第三半导体芯片附接至所述第二半导体芯片包括：
将所述第三芯片的导电凸块附接至所述第二半导体芯片的捕获焊盘中的相应捕获焊盘。
15.根据权利要求14所述的方法，其中，将所述第一芯片的导电凸块附接至所述衬底的所述第一键合焊盘中的相应第一键合焊盘、将所述第二芯片的导电凸块附接至所述第一芯片的捕获焊盘中的相应捕获焊盘以及将所述第三芯片的导电凸块附接至所述第二芯片的捕获焊盘中的相应捕获焊盘包括：通过对所述导电凸块进行热压缩来附接。
16.根据权利要求15所述的方法，其中，所述芯片的导电凸块具有焊料涂层，并且其中将所述第一芯片的导电凸块附接至所述衬底的所述第一键合焊盘中的相应第一键合焊盘、将所述第二芯片的导电凸块附接至所述第一芯片的捕获焊盘中的相应捕获焊盘以及将所述第三芯片的导电凸块附接至所述第二芯片的捕获焊盘中的相应捕获焊盘包括：通过回流所述导电凸块的焊料来附接。
17.根据权利要求13所述的方法，其中，所述方法进一步包括在放置所述半导体芯片之前，将相应的粘附材料膜施加至所述半导体芯片的其上具有所述导电凸块的相应表面，以使得相应的膜提供芯片至芯片以及芯片至衬底的粘附并且在所述导电凸块和所述过孔之间提供空气间隙。
18.根据权利要求13所述的方法，其中，所述方法进一步包括在所述半导体芯片之间以及在所述第一半导体芯片与所述衬底之间施加底层填料，其中所述底层填料提供芯片至芯片以及芯片至衬底的粘附。
19.根据权利要求11所述的方法，包括通过沉积铜柱来形成所述贯通电极。
20.根据权利要求13所述的方法，包括：
刻蚀镀制的所述导热层以将所述导热层分隔为至少接地部分和源电压部分，并且将每个半导体芯片的至少一个导电凸块连接至所述接地部分，以及将每个半导体芯片的一个导电凸块连接至所述源电压部分。
CN201410674233.XA 2013-12-21 2014-11-21 半导体芯片及其制造方法 Pending CN104733417A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/138,022 US20150179557A1 (en) 2013-12-21 2013-12-21 Semiconductor chips having heat conductive layer with vias
US14/138,022 2013-12-21

Publications (1)

Publication Number Publication Date
CN104733417A true CN104733417A (zh) 2015-06-24

Family

ID=52118419

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410674233.XA Pending CN104733417A (zh) 2013-12-21 2014-11-21 半导体芯片及其制造方法

Country Status (3)

Country Link
US (1) US20150179557A1 (zh)
CN (1) CN104733417A (zh)
GB (1) GB2523870A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111430336A (zh) * 2020-04-07 2020-07-17 长江存储科技有限责任公司 集成半导体器件及其制作方法、以及半导体器件

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10068181B1 (en) * 2015-04-27 2018-09-04 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030096441A1 (en) * 1999-08-31 2003-05-22 Lg.Philips Lcd Co., Ltd Fabrication method of thin film transistor substrate for X-ray detector
CN101312172A (zh) * 2007-05-22 2008-11-26 三星电子株式会社 具有增强的接点可靠性的半导体封装及其制造方法
CN101542726A (zh) * 2008-11-19 2009-09-23 香港应用科技研究院有限公司 具有硅通孔和侧面焊盘的半导体芯片
US20100187670A1 (en) * 2009-01-26 2010-07-29 Chuan-Yi Lin On-Chip Heat Spreader
US7781880B2 (en) * 2005-09-30 2010-08-24 Oki Semiconductor Co., Ltd. Semiconductor package
US20130001802A1 (en) * 2011-07-01 2013-01-03 Elpida Memory, Inc. Semiconductor device including insulating resin film provided in a space between semiconductor chips

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3655242B2 (ja) * 2002-01-04 2005-06-02 株式会社東芝 半導体パッケージ及び半導体実装装置
KR101078722B1 (ko) * 2008-03-13 2011-11-01 주식회사 하이닉스반도체 스택 패키지 및 그의 제조방법
JP4689704B2 (ja) * 2008-07-23 2011-05-25 日本電波工業株式会社 圧電部品及びその製造方法
US20110085304A1 (en) * 2009-10-14 2011-04-14 Irvine Sensors Corporation Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias
US8445918B2 (en) * 2010-08-13 2013-05-21 International Business Machines Corporation Thermal enhancement for multi-layer semiconductor stacks
KR102178826B1 (ko) * 2013-04-05 2020-11-13 삼성전자 주식회사 히트 스프레더를 갖는 반도체 패키지 및 그 형성 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030096441A1 (en) * 1999-08-31 2003-05-22 Lg.Philips Lcd Co., Ltd Fabrication method of thin film transistor substrate for X-ray detector
US7781880B2 (en) * 2005-09-30 2010-08-24 Oki Semiconductor Co., Ltd. Semiconductor package
CN101312172A (zh) * 2007-05-22 2008-11-26 三星电子株式会社 具有增强的接点可靠性的半导体封装及其制造方法
CN101542726A (zh) * 2008-11-19 2009-09-23 香港应用科技研究院有限公司 具有硅通孔和侧面焊盘的半导体芯片
US20100187670A1 (en) * 2009-01-26 2010-07-29 Chuan-Yi Lin On-Chip Heat Spreader
US20130001802A1 (en) * 2011-07-01 2013-01-03 Elpida Memory, Inc. Semiconductor device including insulating resin film provided in a space between semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111430336A (zh) * 2020-04-07 2020-07-17 长江存储科技有限责任公司 集成半导体器件及其制作方法、以及半导体器件

Also Published As

Publication number Publication date
GB2523870A (en) 2015-09-09
US20150179557A1 (en) 2015-06-25
GB201419302D0 (en) 2014-12-17

Similar Documents

Publication Publication Date Title
US10734249B2 (en) Package structure and method thereof
US9691739B2 (en) Semiconductor device and method of manufacturing same
CN102376595B (zh) 形成具有导电层和导电通孔的fo-wlcsp的方法和半导体器件
US20030214023A1 (en) Semiconductor device having multi-chip package
US7880285B2 (en) Semiconductor device comprising a semiconductor chip stack and method for producing the same
WO2013057867A1 (ja) 半導体装置
JP2011524647A (ja) ウェハレベルでの縁部の積重ね
KR101858954B1 (ko) 반도체 패키지 및 이의 제조 방법
US20110204511A1 (en) System and Method for Improving Reliability of Integrated Circuit Packages
JP2016012650A (ja) 半導体装置
CN102543920B (zh) 芯片尺寸封装方法及封装结构
CN104733417A (zh) 半导体芯片及其制造方法
KR101837514B1 (ko) 반도체 패키지, 이의 제조 방법 및 시스템 인 패키지
TW200411886A (en) An assembly method for a passive component
EP2557594B1 (en) Semiconductor device reducing risks of a wire short-circuit and a wire flow
CN101964333B (zh) 引线接合结构
JP2013030595A (ja) 半導体装置、マルチチップ半導体装置、デバイス、及び半導体装置の製造方法
KR102633431B1 (ko) 반도체 장치 및 이의 제조 방법
US20060170087A1 (en) Semiconductor device
JP2004363319A (ja) 実装基板及び半導体装置
JP2004288815A (ja) 半導体装置及びその製造方法
TW201332031A (zh) 用於一半導體封裝之基板製程、封裝方法、封裝結構及系統級封裝結構
CN101527292B (zh) 芯片封装结构
US20240055414A1 (en) Semiconductor package and method of manufacturing the semiconductor package
KR20230011659A (ko) 반도체 패키지 및 그의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150624