CN101312172A - 具有增强的接点可靠性的半导体封装及其制造方法 - Google Patents

具有增强的接点可靠性的半导体封装及其制造方法 Download PDF

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CN101312172A
CN101312172A CNA2008100985296A CN200810098529A CN101312172A CN 101312172 A CN101312172 A CN 101312172A CN A2008100985296 A CNA2008100985296 A CN A2008100985296A CN 200810098529 A CN200810098529 A CN 200810098529A CN 101312172 A CN101312172 A CN 101312172A
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top layer
semiconductor chip
encapsulation unit
substrate
connection element
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郑显秀
张东铉
金南锡
姜善远
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

所提供的是一种具有增强的接点可靠性的半导体封装及其制作方法。该方法包括：形成包括封装单元，该封装单元包括插入在底层与顶层之间的半导体芯片；以及，在衬底上顺序堆叠所述封装单元。所述底层和所述顶层由具有比半导体芯片模量低的模量的材料形成。所述半导体封装包括：布置在衬底上的至少一个封装单元，所述封装单元包括：具有焊盘的半导体芯片、基本包围所述半导体芯片的底层和顶层、以及覆盖在所述顶层上的再分布结构。所述再分布结构电连接到所述焊盘。

Description

具有增强的接点可靠性的半导体封装及其制造方法
相关申请的交叉引用
该美国非临时专利申请要求于2007年5月22日提交的韩国专利申请No.10-2007-0049766在35U.S.C.§119下的优先权，该韩国专利申请的全部内容通过引用结合于此。
技术领域
在此公开的本发明涉及一种半导体封装及其制造方法，且更具体地，涉及一种具有增强的接点可靠性的半导体封装及其制造方法。
背景技术
通常，半导体器件制造包括：前端工艺，其中集成电路(IC)芯片通过光刻、淀积和刻蚀工艺形成在晶片上；以及后端工艺，其装配并封装每个IC芯片。后端工艺中的封装具有以下四种重要功能：
1.保护芯片免受环境和操作的损坏；
2.在芯片上形成连接以传送输入/输出信号；
3.物理地支撑芯片；以及
4.提供对芯片的热耗散。
高度集成和便携式电子装置的激增正推动半导体封装技术以满足对改进的电性能、减少的成本、更轻的重量以及更薄的外形的需求。为了满足这些需求，引入了层叠封装(package on package)(POP)、芯片尺寸封装(chip scale packaging)(CSP)以及晶片级封装(wafer-levelpackaging)(WLP)技术。此外，提出了用于在衬底上堆叠半导体芯片的三维(3-D)堆叠技术以满足针对增加的封装密度的技术要求。
由于3-D堆叠技术能够极大地减小芯片间的互连长度，所以该技术被认为是一种能够克服例如信号延迟和功耗的技术局限的方法。此外，3-D堆叠技术提供了改进的技术方面，该技术方面包括电特性、形状因子(form factor)、尺寸和密度。
然而，通过典型的3-D堆叠技术制造的半导体封装易受热应力或机械应力的损坏，所述热应力由自半导体芯片所产生的热量或制造过程中所供给的热量引起，所述机械应力由外力引起。例如，由于热应力或机械应力集中在电连接半导体芯片的凸起(bump)上，所以凸起可能被损坏。因此，封装结构的接点可靠性可能劣化。
发明内容
本发明提供一种具有增强的接点可靠性的半导体封装及其制造方法。
根据本发明的一些实施例，一种半导体封装，包括：衬底；以及堆叠在该衬底上的至少一个封装单元，每个所述封装单元包括具有焊盘(pad)的半导体芯片、基本包围该半导体芯片的底层和顶层、以及覆盖在所述顶层上的再分布结构。该再分布结构电连接到所述焊盘。所述顶层和底层具有比所述再分布结构和半导体芯片的模量低的模量(modulus)。
附图说明
包括附图以提供对本发明更进一步的理解，并将附图结合到说明书中且组成说明书的一部分。所述附图示出了本发明的示例性实施例，并且和说明书一起用于解释本发明的原理。在附图中：
图1至6是示出了根据本发明的实施例的制造半导体封装的方法的剖视图；
图7和8是示出了根据本发明的其他实施例的制造半导体封装的方法的剖视图；以及
图9和10是示出了根据本发明的半导体封装及其制造方法的剖视图。
具体实施方式
以下将参考附图对本发明的优选实施例作更详细的描述。然而，本发明可以不同形式具体化，且不应被解释为限于此处提出的实施例。更确切地，这些实施例被提供以使得本公开全面且完整，并将本发明的范围完全传达给本领域的技术人员。
在附图中，层和区域的尺寸被扩大以便于清楚地描述。同样，将理解的是，当层(或膜)被提及为位于另一层或衬底之“上”时，该层(或膜)可以直接位于另一层或衬底之上，或者也可以存在中间层(intervening layer)。而且，将理解的是，当层被提及为位于另一层之“下”时，该层可以直接位于另一层之下，并且也可存在一个或多个中间层。此外，也将理解的是，当层被提及为位于两层“之间”时，该层可以是这两层之间的唯一层，或者也可以存在一个或多个中间层。相同的参考标记全部表示相同的元件。
图1至6是示出了根据本发明的实施例的制造半导体封装的方法的剖视图。
参考图1，半导体芯片20被附接在底层10上。半导体芯片20包括连接到内部电路的至少一个输入/输出焊盘(下文称作焊盘)25，且焊盘25的位置可以根据半导体芯片20的设计而变化。通过前端工艺来制造半导体芯片20，且多个半导体芯片可以附接在一个底层上。半导体芯片20可以例如是存储器芯片或逻辑电路芯片。
底层10可以由具有比半导体芯片20的模量更低的模量的材料形成。具体地，底层10可以由具有在大约10MPa与大约1GPa之间的杨氏模量的材料中的至少一种形成。更优选地，底层10由具有在大约10MPa与大约100MPa之间的杨氏模量的材料中的至少一种形成。例如，底层10可以由硅酮化合物、橡胶化合物、光敏树脂化合物和合成树脂化合物中的至少一种形成。
此外，半导体芯片20的厚度t2可以在大约10μm与大约100μm之间。根据实施例，半导体芯片20的厚度t2可以在大约30μm以下。当半导体芯片20具有这么小的厚度时，它很容易因热应力或机械应力而变形。然而，如果底层10由具有低模量的材料形成，则可以减小由于外部应力而导致的半导体芯片20的变形。根据实施例，底层10的厚度t1在从大约5μm至大约1000μm的范围内。
如果底层10由硅酮化合物、橡胶化合物、光敏树脂化合物和合成树脂化合物中的一种形成，则半导体芯片20可以不需另外的粘合层而附接在底层10上。然而，根据另一个实施例，粘合层(未示出)还可以形成在底层10与半导体芯片20之间，以提升其间的粘合。
参考图2，顶层30形成在具有半导体芯片20的底层10上。在此种情况下，半导体芯片20基本被顶层30和底层10包围或密封。
根据本发明，顶层30可以由具有比半导体芯片20的模量低的模量的材料形成。也就是说，顶层30可以由具有在大约10MPa与大约1GPa之间的杨氏模量的材料中的至少一种形成。更优选地，顶层30由具有在大约10MPa与大约100MPa之间的杨氏模量的材料中的至少一种形成。此外，顶层30可以由硅酮化合物、橡胶化合物、光敏树脂化合物和合成树脂化合物中的至少一种形成。根据一个实施例，顶层30可以由与底层10相同的材料形成。根据另一个实施例，顶层30可以由与底层10不同的材料形成。
顶层30的厚度t1在从大约5μm至大约1000μm的范围内。如上所述，由于半导体芯片20由低模量材料的顶层30和底层10密封，所以由于外部应力而导致的半导体芯片20的变形可以被进一步减小，且半导体芯片20将与顶层30或底层10分离开的可能性也被减小。例如，当仅有底层10和顶层30之一覆盖半导体芯片20时，由于半导体芯片20上施加的重力、半导体芯片20中产生的热量以及制造过程中供给的热量，所以半导体芯片20可能与顶层30或底层10分离开。然而，如上所述，当半导体芯片20由顶层30和底层10密封时，可以有效防止这种分离。
参考图3，顶层30和底层10被构图(pattern)以形成有穿透顶层30和底层10的通孔(via hole)34以及穿透顶层30以暴露焊盘25的焊盘开口部32。
所述构图工艺可以使用光刻和刻蚀工艺、激光钻孔工艺、机械钻孔工艺以及离子束钻孔工艺中的一种来完成。光刻和刻蚀工艺包括：形成光致抗蚀剂图案，以限定通孔34和顶层30上的焊盘开口部32；以及，通过使用光致抗蚀剂图案作为刻蚀掩模，刻蚀顶层30和底层10。这里，为了减少对焊盘25的刻蚀损坏，顶层30的刻蚀可以使用具有相对于焊盘25的刻蚀选择性(etching selectivity)的刻蚀配方来完成。根据本实施例，通孔34和焊盘开口部32被同时形成。
因为，与半导体芯片20(即，晶片)相比，底层10和顶层30可以被容易地刻蚀，所以，与包括形成通孔以穿透晶片的步骤的传统穿透衬底通孔(TSV)技术相比，本发明的技术更易制造半导体封装。因为刻蚀的这种简易性，所以，与传统技术相比，本发明可被用于制造具有更低成本、更高可靠性以及更高生产率的半导体封装。
此外，通孔34可以围绕半导体芯片20、自半导体芯片20的边缘间隔开而形成。这里，可选择形成通孔34的位置，从而使封装单元在之后堆叠封装单元的步骤中得以相互电连接。也就是说，可以通过考虑电连接来确定通孔34与半导体芯片20之间的间隔以及通孔34的位置。通孔34的宽度可以在从大约10μm至大约100μm的范围内。
参考图4，使用再分布工艺(redistribution process)形成与焊盘25的暴露的顶面(top surface)相连接的再分布结构40。
所述再分布工艺形成新的互连，该互连电连接到半导体芯片20的焊盘25以利于容易的封装处理。所述再分布结构40包括用于以上目的的新的互连。具体地，在封装结构包括堆叠的半导体芯片的情况下，该半导体芯片可以通过再分布结构而被电连接，而不必考虑焊盘25的位置。也就是说，当使用再分布结构40时，可以使用各种简单的连接技术，因为半导体芯片间的电连接不受焊盘位置的限制。
根据本发明的实施例，再分布结构40的形成还包括以下步骤：在具有通孔34和焊盘开口部32的得到的(resultant)结构上，形成具有模型开口部32的模型层(mold layer)，其限定了再分布结构40的形状；以及包括以下步骤：使用电镀技术形成金属层，以填充模型开口部32。可替换地，在电镀步骤中，将用作籽晶电极(seed electrode)的籽晶层(seed layer)可以在形成金属层之前形成。该籽晶层可以通过溅射或蒸发技术而形成。此处，模型层的厚度(即，再分布结构40的厚度)可以在大约1μm与大约50μm之间。更优选地，模型层的厚度在大约2μm与大约10μm之间。
然而，制造再分布结构40的方法不限于以上方法，且该再分布结构40可以通过各种其他方法来实现。例如，再分布结构40的制造可以包括形成籽晶层和金属层的步骤，以及使用光刻和刻蚀工艺来对金属层和籽晶层构图的步骤。
再分布结构40从焊盘25延伸以覆盖通孔34的内壁。如图4所示，再分布结构40可以不完全填充通孔34，或者可以沿着底层10的底面(bottom surface)扩展短的距离。根据另一个实施例，虽然再分布结构40可以覆盖通孔34的内壁，但该再分布结构40可以不沿底层10的底面延伸。
参考图5，连接元件50形成在再分布结构40上。连接元件50可以使用球凸起喷射(ball bump jet)技术、电镀技术和凸起印刷技术中的一种而形成。根据一个实施例，连接元件50可以使用形成再分布结构40的工艺而形成。也就是说，连接元件50和再分布结构40可以使用相同的工艺形成。
同时，连接元件50可以形成在通孔34的顶部或底部上。根据一个实施例，连接元件50延伸到通孔34内，以填充通孔34的一部分，如图5所示。在这种情况下，连接元件50与再分布结构40之间的接触面积增加，从而可以使接触阻抗减小。此外，当连接元件50填充通孔34的一部分时，该连接元件50可以与再分布结构40牢固地接合。
此外，由于底层10和顶层30由具有低模量的柔性材料形成，所以施加到连接元件50的机械应力可以通过通孔34的侧壁而被吸收到底层10和顶层30中。由于这种应力吸收，本发明的封装结构提供了增强的接点可靠性。
接下来，通过划片工艺(dicing process)切割底层10和顶层30，来分离单独的封装单元100。半导体芯片20、顶层30、底层10、再分布结构40以及连接元件50可以被称作封装单元100。
划片工艺包括：沿着围绕半导体芯片20的分离区域SR切割底层10和顶层30。这里，分离区域SR可以被布置在邻近半导体芯片20之间(即，在被连接到各自不同的半导体芯片20的再分布结构40之间)。划片工艺可以使用激光、锯和刀中的一种来实现。
参考图6，通过划片工艺而分离的封装单元100被顺序堆叠在衬底200上(尽管图6中示出了四个封装单元，但封装单元100的数量可以变化)。衬底焊盘210被布置在衬底200上，且封装单元100的连接元件50被连接到衬底焊盘210。封装单元100和衬底焊盘210可以通过衬底连接元件55连接。连接端子(未示出)可以形成在衬底200的预定区域上以电连接到外部电子装置。
被堆叠的封装单元100通过连接元件50和/或再分布结构40而彼此电连接。更具体地，如图6所示，一个封装单元100的连接元件50被电连接到另一个封装单元100的再分布结构40，所述另一个封装单元100被布置在连接元件50的顶部或底部。用于这种电连接的工艺可以包括以下步骤：通过熔融(melting)和冷却连接元件50，将该连接元件50结合(bond)到另一个封装单元的再分布结构40。
此外，因为连接元件50以熔融状态被压紧到另一个封装单元100，所以该连接元件50可以被插入到另一个封装单元的通孔34中。由于封装单元100在结构上由连接元件50支撑，因此施加到封装单元100上的应力可能会集中在连接元件50上。然而，由于底层10和顶层30由具有低模量的柔性材料形成，所以施加到连接元件50的应力可以通过通孔34的侧壁而被吸收到底层10和顶层30中。由于该应力的吸收，本发明的封装结构提供了增强的接点可靠性。
根据实施例，封装单元100包括具有各自不同熔点的连接元件50。更具体地，由于封装单元100的位置变得远离衬底200，所以封装单元100的连接元件50可以具有较低的熔点。当连接元件50具有不同的熔点时，有缺陷的封装单元可以被有选择地替换。由此，根据本实施例的封装结构的产率(yield)将提高。
根据本发明的一些实施例，可以在划片工艺后测试封装单元100，以便确定封装单元100是否是有缺陷的。只有通过该测试的封装单元100才能被顺序堆叠在衬底200上。另一方面，根据修改的实施例，可以堆叠如图5所示的多个封装，然后可执行划片工艺。更具体地，可以首先完成堆叠，然后可执行划片工艺。在这种情况下，由于封装单元在没有测试工艺的情况下被封装，所以与上述实施例相比，本实施例中的封装结构的最终产率可能会降低。
图7和图8是示出了根据本发明的其他实施例的制造半导体封装的方法的剖视图。这些实施例与图1至图6的实施例类似。因此，为了简明，将省略重复的描述。
参考图7，封装结构的封装单元100a、100b、100c和100d可以包括具有各自不同的尺寸或类型的半导体芯片20a、20b、20c和20d。换句话说，半导体芯片20a、20b、20c和20d中的至少一个可以与半导体芯片20a、20b、20c和20d中的至少另一个在尺寸、形状和功能中的一个或多个上不同。在这种情况下，使用存储器芯片和逻辑电路芯片的集成存储器逻辑可以被容易地实现。
参考图8，根据本实施例的封装结构，封装单元100相对于其他实施例地封装单元100是经过旋转的。具体地，与底层10相比，每个封装单元100的顶层30更为邻近地附接到衬底200。由此，图8中的封装结构的封装单元100被以与其他实施例中的封装单元100相反的取向(即被旋转约180度)堆叠在衬底200上。在这种情况下，封装单元100可以在不需衬底连接元件55的情况下被结合到衬底焊盘210。
图9和图10是示出了根据本发明的半导体封装及其制造方法的剖视图。
本实施例与上述实施例类似。因此，为了简明，将省略重复的描述。
参考图9和图10，在衬底200上形成有钝化层90，从而覆盖被堆叠的封装单元100。钝化层90保护封装单元100免受外部碰撞或杂质材料的损害。
此外，根据本实施例，底部填充层(underfill layer)80可以布置在每个封装单元100之间、以及衬底200与最底下的一个封装单元100之间。连接元件50、衬底200、顶层30和底层10可以具有各自不同的热膨胀系数，且由于所述热膨胀系数，应力可能被施加到连接元件50。为了减小由于不同的热膨胀系数而引起的应力，底部填充层80可以由具有中间热膨胀系数的材料形成。而且，底部填充层80可以在结构上支撑封装单元100。
根据本发明的实施例，底部填充层80可以由处于胶状或凝胶状态的材料形成，或者由具有低于或等于顶层30或底层10的模量的模量的材料形成。
参考图10，钝化层90被形成为覆盖被堆叠的封装单元100。然而，根据本实施例，与图9的实施例不同，底部填充层80没有形成在封装单元100之间。因此，封装单元100之间仍然留有空的空间。
根据一些实施例，图8中的封装结构可以用在图9或图10的任一实施例中，且图6和图7中的封装结构也可以被用在图9和图10的实施例中。
根据本发明，半导体芯片被具有低模量的材料的顶层和底层包围。于是，热应力或机械应力可以被顶层和/或底层吸收。因此，可以最小化由施加到连接半导体芯片的连接元件的应力而导致的接点可靠性的降低。
本发明的实施例提供了制造半导体封装的方法，该方法包括：形成封装单元，该封装单元包括插入在底层与顶层之间的半导体芯片；以及将所述封装单元顺序堆叠在衬底上。所述底层和顶层由具有比所述半导体芯片的模量低的模量的材料形成。
在一些实施例中，所述底层和顶层由具有在大约10MPa与大约1GPa之间的模量的材料形成。
在其他实施例中，所述底层和顶层是硅酮化合物、橡胶化合物、光敏树脂化合物和合成树脂化合物中的至少一种。
在另外的实施例中，所述底层和顶层具有在大约10μm与大约1000μm之间的厚度。
在另外的实施例中，所述半导体芯片具有在大约10μm与大约100μm之间的厚度。
在另外的实施例中，形成封装单元还包括：将具有焊盘的至少一个半导体芯片附接在底层上；在所述底层上形成顶层，从而覆盖所述半导体芯片；对所述顶层和所述底层构图以形成焊盘开口部和通孔，所述焊盘开口部暴露焊盘，所述通孔穿透所述顶层和所述底层；以及形成再分布结构，以接触所述焊盘并且至少覆盖所述通孔的内壁。
在进一步的实施例中，形成焊盘开口部和通孔使用了光刻和刻蚀工艺、激光钻孔工艺、机械钻孔工艺和离子束钻孔工艺中的一种。
在更进一步的实施例中，形成封装单元进一步包括形成连接元件，该连接元件在形成再分布结构后接触该再分布结构。
在更进一步的实施例中，使用球凸起喷射技术、电镀技术和凸起印刷技术中的一种，形成连接元件。
在更进一步的实施例中，连接元件形成在通孔的顶部或底部上，从而填充所述通孔的一部分。
在更进一步的实施例中，顺序堆叠封装单元进一步包括：将封装单元的连接元件结合到另一个封装单元的再分布结构。结合所述连接元件进一步包括：在熔融连接元件后，将封装单元的连接元件插入到另一个封装单元的通孔中。
在更进一步的实施例中，封装单元的连接元件的熔点随着对应封装单元的位置逐渐远离衬底而降低。
在更进一步的实施例中，形成封装单元进一步包括：在衬底上堆叠封装单元之前，执行划片工艺，该划片工艺分离封装单元。
在更进一步的实施例中，所述划片工艺使用激光、锯和刀中的一种，且包括在半导体芯片的再分布结构的外侧切割顶层和底层。
根据本发明的其他实施例，半导体封装包括：顺序堆叠在衬底上的封装单元，每个封装单元包括具有焊盘的半导体芯片；基本包围半导体芯片的底层和顶层；以及，再分布结构，该再分布结构穿透顶层以接触焊盘。半导体芯片被顶层和底层包围，该顶层和底层具有比再分布结构和半导体芯片的模量低的模量。
在其他实施例中，所述底层和顶层由具有在大约10MPa与大约1GPa之间的模量的材料形成。
在另外的实施例中，所述底层和顶层是硅酮化合物、橡胶化合物、光敏树脂化合物和合成树脂化合物中的至少一种。
在另外的实施例中，所述底层和顶层具有在大约10μm与大约1000μm之间的厚度。
在另外的实施例中，所述半导体芯片具有在大约10μm与大约100μm之间的厚度。
在进一步的实施例中，再分布结构覆盖通孔的内壁，该通孔从焊盘延伸并穿透顶层和底层，并且所述半导体封装进一步包括封装单元之间的连接元件，该连接元件使所述封装单元与所述封装单元之上和之下的其他封装单元的再分布结构电连接。
在更进一步的实施例中，所述连接元件被插入到该连接元件之上或之下的另一个封装单元的通孔中。
在更进一步的实施例中，连接元件的熔点随着对应封装单元的位置逐渐远离衬底而降低。
以上公开的主题被视为示例性的而非限制性的，且权利要求试图涵盖所有这种修改、增加以及落入本发明的本质精神和范围内的其他实施例。因此，在法律允许的最大范围内，本发明的范围由权利要求及其等价物的最广泛许可的解释所确定，且不应被之前的详细描述所约束或限定。

Claims (14)

1.一种半导体封装，包括：
衬底；以及
布置在所述衬底上的至少一个封装单元，该封装单元包括：
具有焊盘的半导体芯片；
布置在所述半导体芯片下的底层；
布置在所述半导体芯片上的顶层，所述底层和所述顶层基本包围所述半导体芯片；以及
覆盖在所述顶层上的再分布结构，该再分布结构电连接到所述焊盘，
其中所述顶层和所述底层每个均包括具有比所述再分布结构和所述半导体芯片的模量低的模量的材料。
2.根据权利要求1所述的半导体封装，其中所述顶层和所述底层每个均包括具有在大约10MPa与大约1GPa之间的模量的材料。
3.根据权利要求1所述的半导体封装，其中所述底层和所述顶层包括硅酮化合物、橡胶化合物、光敏树脂化合物和合成树脂化合物中的至少一种。
4.根据权利要求1所述的半导体封装，其中所述底层和所述顶层具有在大约10μm与大约1000μm之间的厚度。
5.根据权利要求1所述的半导体封装，其中所述半导体芯片具有在大约10μm与大约100μm之间的厚度。
6.根据权利要求1所述的半导体封装，其中，所述再分布结构从所述焊盘延伸，并且覆盖穿透所述顶层和所述底层的通孔的内壁。
7.根据权利要求6所述的半导体封装，其中，所述至少一个封装单元包括顺序堆叠在所述衬底上的多个封装单元，并且每个所述封装单元均包括布置在所述通孔中的连接元件，并且其中所述多个封装单元中的邻近封装单元的所述连接元件电连接所述邻近封装单元的再分布结构。
8.根据权利要求7所述的半导体封装，进一步包括衬底连接元件，该衬底连接元件将所述封装单元的所述连接元件电连接到所述衬底上的衬底焊盘。
9.根据权利要求7所述的半导体封装，其中，被堆叠在远离所述衬底的封装单元的所述连接元件具有比被堆叠在靠近所述衬底的封装单元的连接元件的熔点低的熔点。
10.根据权利要求7所述的半导体封装，其中，所述多个封装单元被顺序堆叠在所述衬底上，从而使每个所述封装单元的所述顶层比所述底层距离所述衬底远。
11.根据权利要求7所述的半导体封装，其中，所述多个封装单元被顺序堆叠在所述衬底上，从而使每个所述封装单元的所述底层比所述顶层距离所述衬底远。
12.根据权利要求7所述的半导体封装，其中，在尺寸、形状和功能中的一个或多个方面，所述半导体芯片中的至少一个半导体芯片不同于所述半导体芯片中的至少另一个半导体芯片。
13.根据权利要求1所述的半导体封装，其中所述顶层和所述底层每个均包括不同的材料。
14.根据权利要求1所述的半导体封装，其中所述顶层和所述底层包括相同的材料。
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