TW200901414A - Semiconductor packages with enhanced joint reliability and methods of fabricating the same - Google Patents

Semiconductor packages with enhanced joint reliability and methods of fabricating the same Download PDF

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Publication number
TW200901414A
TW200901414A TW097118683A TW97118683A TW200901414A TW 200901414 A TW200901414 A TW 200901414A TW 097118683 A TW097118683 A TW 097118683A TW 97118683 A TW97118683 A TW 97118683A TW 200901414 A TW200901414 A TW 200901414A
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Taiwan
Prior art keywords
package
layer
substrate
semiconductor
top layer
Prior art date
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TW097118683A
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English (en)
Inventor
Hyun-Soo Chung
Dong-Hyeon Jang
Nam-Seog Kim
Sun-Won Kang
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200901414A publication Critical patent/TW200901414A/zh

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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

200901414 28202pif.doc 九、發明說明: 本=請餘張於·7彳5月22號提出申請之韓國專利 ^案弟10-2007-0_766號的優先權,該專利申請案所揭 路之内容系完整結合於本說明書中。 【發明所屬之技術領域】 本發明所揭露之内容有關於半導體封裝以及其製造方 別是有關於具強化接點可靠度之半導體封裝以及 造方法。 【先前技術】 、通吊‘體件的製造包括前段製程(即通過微影、 沈積和糊製程在關上形成频電路(Ic)W )和後段製程 P、、且戒和封裝各積體電路晶片)。後段製程封裝的四個重 要功能如下: U呆護晶片免受環境和操作的損壞; 2. 在晶片上形成連接用於傳輸輪入/輸出信號; 3. 為晶片提供物理支樓;以及 4. 為晶片提供散熱。 问度積集和可攜式電子裝置的增長正推動半導體封裝技 術進展以滿足對改良的電氣性能、降低成本、更輕的重量和 ^薄的厚度的需求。爲了滿足這些需求,已經導人了堆疊封 衣(p ckage on package ; pop)、晶片尺度封裝(chip scale
PaCkage,CSP)和晶圓層次封裝(wafer-level packaging ; WLP) 7 200901414 28202pif.doc -D堆疊技術用於在基板上堆 ' 吃珉使用3-D堆疊技術月 .晶片以滿足增加封裝密度的技術需求_ 、π3~D堆疊技術能大幅降低晶片間的内連線長度,其 被認爲是—種能夠克服技術限制(如信號延遲和電力消^的^ Γ开此二Γ堆疊技術提供了改良的技術方面,包括電特 II、形狀因數、尺寸和密度。 〇
U 導雕㈣的3_D堆疊技術製造的半物封裝對於半 產生賴或製造過程中供躺熱所造成的_力, 應力卻是非常脆弱的。例如,由於熱應 m電性連接半導體晶片的凸塊―) 降低凸塊可能受損。結果,封裝結構的接點可靠度可能 【發明内容】 製造供—種具強化接點可靠度之半導體封裝以及其 根據本發明的-些實施例,半導體封裝包括: 至少-個堆疊於基板之上的封裝單元, ,的半導體晶片’實質上包圍著半導體晶片早:= 層,和覆蓋於頂層之上的重新配置結構。重新配置^性 頂層和底層具有比重新配置結構和半編片 【實施方式】 8 200901414 28202pif.doc 下文將茶考所附圖式對本發明的較佳實施例作詳細說明 如:。然而,本發明可以不同的形式實施,而不應理解爲僅 p艮疋於本文例舉的實施例。相反地,提供這些實施例是爲了 讓本揭露更全面和完整,並將本發明的范圍充分傳達給熟習 此技藝者。 Ο 在圖式中,爲了能作清楚的說明,將層和區域的尺寸放 大。士可以理解的是,當提到層(或薄膜)處於另-層或基板“之 ϋ’該層(或薄膜)可以是直接處於另一層或基板之上 α 3之下蚪,該層可以是直接處於另—層之下,也 介層…卜:也可以理解的是,當提二 ^ ’該層可以疋處於兩層之間的唯一—席, 二:子個或多個中介層。在整個說明書中,類似ή 考標記表示類似的元件。 、勺參 踔曰片將半導體晶片20附接在底層10之上。丰道 ::示爲焊;)ΐ少的輸入/輪出焊盤(下 的設計作變更。半導體1^據+導體晶片20 可以將多個半導體曰通過則段製程製造的,龙及 丁寻版日日片附接在—個底層之 < 丑 晶20可以是記億晶片或邏輯電路晶片。 ,半導發 9 200901414 28202pif.doc f : /、 可以是由比半導體晶片20具有更低模量 你1的材料構成。特別地’底層10可以是由具有介 ;、’、 Pa和大約lGPa之間的楊氏模量(Y〇ung,s m〇flUS 士的材料中的至少一種構成。更優選地,底層10可 以疋,、具;丨於大約】0Mpa和大約1 OOMPa之間的揚氏模量 Γ 的材料中的7至)—種構成。例如,底層1G可以是由梦樹月旨化 合物、橡膠化合物、練樹職合物和合成樹齡合物中的 至少一種構成。 另外,半導體晶片20的厚度t2可以是介於大約10 μιη 和大,力100 μιη之間。根據實施例,半導體晶片的厚度匕 可以是低於大約3〇 。當半導體晶片2〇具有這樣小的厚度 時,就容易受熱應力或顧應力而變形。然而,如果底層1〇 是由低模量的材料構成的,就可以減少外部應力造成的半導 體晶片2G的變形。根據實施例,底層1()的厚度在大約5 μιη到大約1000 μιη的範圍内變動。 如果底層10 S由石夕樹脂化合物、橡膠化合物、光敏樹脂 化合物和合賴脂化合物中的其中之1成的,可以將半導 體晶片2G在沒有額外的附著層的情况下附接在底層1〇之 上。然而’根據另i實施例’附著層(未示出)可以進一 步形成於底層H)和铸體^ 2〇之間W促進其間的附著。 參考圖2,頂層30形成在具有半導體晶片2〇的底層ι〇 之上。在這種情況下,半導體晶片2Q實質上麵層3〇和底 層10圍繞或密封著。 * 10 200901414 28202pif.doc 很m奉發明,頂層3〇可γ Β 低模量的材料構成。也就是說以了疋由,半導體晶月20具有更 約]OMPa和大約!GPa之門 、3 )0可以是由具有介於大 構成。更優選地,頂層3〇 氏模量的材料中的至少-種 Ο 大約!()_之_曰揚味^是^•有介於大約和 外,頂層30可以是由梦_旨化^1的至少一種構成。另 化合物和合成難化合物巾。物、橡膠化合物、光敏樹脂 例,頂層30可以是由鱼麻馬〉、一種構成。根據一個實施 個實施例,頂層30可以是二1二相同的材料構成。根據另-頂㈣的厚度底層1〇不同的材料構成。 變動。如上所述,由於半導體的範圍内 的頂層30和底層1G㈣㈤ 被由她a的材料構成 半導體晶片20的變形進一步降低外部應力造成的 η分離的可能性也降低了;^體二曰片20從頂層30或底層 20 ; 1〇 3〇 重力和半導體曰曰片如二τ ’由於貫施在半導體晶片20上的 埶,半導Μ曰^ 2Π内所產生的熱以及製造過程中所供應的 :上21、能從頂層3〇或底層1〇上分離。然而, 一—密封時,就 層30= 圖層US窗3G3=f J_化以形成貫穿於頂 焊盤開口部份32。 和貝牙頂層3〇以暴露焊盤25的 1] 200901414 28202pif.doc 可使用微影和蝕刻製程、雷 和離子束觀製歡-錢行_ =、機械鑽孔製程 程包括形成用於定義介層窗34和頂屉,私。微影和蝕刻製 份32的光阻圖案並通過使用光阻‘作=2,盤開口部 3〇和底層1〇。這時,爲了減少對般為㈣罩祕刻頂層 使用對焊盤25具有_選擇性的損害,可以 侧。根據這個實闕,介層窗3 22頂層30的 時形成的。 砰邱孟開口部份32是同 由於底層10和頂層30相較於 容易被_,因此,與__ 圓)报 substme^ ;Tfs;® 半導體封裝更容易製造。由於 )技衡相比’ 術,本發明可用於製造具更低成本、更高可技 力的半導體封裝。 罪又和更大生產
C ”’介,窗34可形成在半導體晶片加 =,使付在下-步料疊封裝單㈣封裝單元能相 = 接。也就是說,可通過考慮連接決定介層窗%和半導= 曰曰片20之間的間隔和介層f 34的位置。介層窗料的寬度w pt大約10 μιη到大約100 μπι的範圍内變動。 參考圖4 ’用重新配置製程(re— pr〇cess)形 成與焊盤25的暴露_面相連接的顏配置結構40。 12 200901414 28202pif.doc 重新配置製鄉成紐連制半導體“ 20的焊般25 的新的内連線以使封裝製程更加容易。重新配置結構4〇包括 用於上述目的之新的眺線。特別地,在封裝結構包括堆疊 •的半導體晶月的情況下,半導體晶片可通過重新配置結構電 ' 性連接,而不受焊盤25的位置的影響。也就是說,當使用重 新配置結構40時,可以使用多個和單個連接技術,因為半導 〇 體晶片之間的電性連接不受限於焊盤的位置。 根據本發_實施例,重聽置結構4G的職還包括在 具有介層窗34和焊盤開口部份32的合成結構上形成具有模 開口部份32的模層的步驟,此模層定義了重新配置結構4〇 的形狀,以及制賴技術形成金屬相填充模開口部份幻 的7驟或者’可在开> 成金屬層之前开多成在電鍍步驟中用作 晶種,鍍的晶種層。可通過濺散或蒸發技術形成晶種層。在 此,模層的厚度(如,重新配置結構4〇的厚度)可處於大約 1 μπι和大約50 Pm之間。更優選地,模層的厚度可在大約2 ^ μιη和大約1 〇 之間。 然而,製造重新配置結構40的方法不限定於上文的方 法,並且可通過其它多種法實現重新配置結構40。例如,重 新配置結構4〇的製造可包括形成晶種層和金屬層的步驟以及 使用微影和蝕刻製程使金屬層和晶種層圖案化的步驟。 重新配置結構40從焊盤25處延伸以覆蓋介層窗34的内 壁。如圖4所示,重新配置結構4〇不一定完全填充介層窗 Μ ’或者可能沿著底層40的底面延伸—小段距離。根據另— 13 200901414 28202pif.doc 们’、施例,雖然重新配置結構仙可覆蓋 但是其不—定沿底層Η)的絲延伸。 . :考® 5 ’連接件5()形成在顏配置結構*上 i=r射技術、電凸塊印刷技術的其中:: 40的°根據—個實施例,可使㈣成重新配置έ士構 40的U场成連接件% 、、,構
ϋ 連接件5^)和重新配置結構4()。以了使用相_製程形成 同時’連接件50可形成在介層窗34 據-個實施例,連接件5。延伸入介層 =二; 34的部份,如私-丄 ]a再凡"灣窗 如圖5所不。在這種情況下,連接件5〇 f匕間的接觸區域擴大了,因此可以降低接觸電: 入5舌广接件5G填充介層窗34的部份時,可以堅固扯接 合到重新配置結構4〇。 口乙接 題fr祕底層10和頂層30是由具有低模量的軟性材 、,細加於連接件50之上的機械應力可通過介芦窗34 ,内壁被吸收到底層1G和頂層3U。由於這種應力㈣, 本么明的封裝結構提供了強化的接點可靠度。 接下來’通過切割製程(dicing process)十刀斷底層1〇和 頂層30以分離個體封裝單元1〇〇。半導體晶片2〇、頂層 3〇、底層1〇、重新配置結構4〇和連接件5〇可表示爲封裝單 切奢]衣耘包括圍繞半導體晶片2〇沿分離區域SR切斷底 層1〇和頂層30。這時,可將分離區域(separation region) 14 Ο Ο 200901414 28202pif.doc SR置於相鄰的半導體晶片2〇之間 的半導體晶片20的重新配置結構4〇 ’迷接到各個不同 鋸和刀的其中之-實現切割製程。 °可使用雷射、 參考圖6,將通過切割製程分 疊在基板200 (雖然圖6顯示了 4個 #早^^依騎 】〇0的數量可以改變)之上。將基板焊盤^置裝單元 上,並且將封裝單元的連接件5 ,於基板200之 可通過基板連接件55連接封裝 焊盤210。 在基板綱的預定區域形成連和基反谭盤训。可 至外部電子元件。 接、知(未不出)以電性連接 堆疊的封裝單元1〇〇通 相互電性連接。更具體地妾和:重新配置結構 -個封裝單元100的重新配$ j接件的項部或底部的另 可包括通過_口冷卻連接件且種電性連接的製程 封裝=的重新配置結構4㈣步^接件5G焊接到另一個 單元100卜内因^連接件50在溶化狀態下被壓縮到另-個封裝 内。由於封將其插人另—個封裝單元的介層窗34 於封裝單元在結構上由連接件5G支撑,所以施加 底層H)和丁/^的^力二集中在連接件50上。然而,由於 於連接件50、Ll 有低模量的軟性材料構成的,施加 上的應力可通過介層窗34 _壁被吸收到底層 15 200901414 28202pif.doc 本發明的轉結構提供 10和頂層30内。由於這種應力吸收, 了強化的接點可靠度。 根據實施例,域單元100包括分別具 接件50。更具體地,當封裝單元100,立置遠點的連 時,封裝單元·的連接件料具有較齡馳。
50具有不同的熔點時,可選擇性地替換有缺陷的封^接件 結果,根據本實施例的封裝結構的良率將得到提升。早7 根據本發明的-些實施例,可在切割製程° 單元!〇〇以確定封裝單元是否有缺陷。只有通二 封裝單可依序堆疊到基板之上m根據 改良的只%例,可將圖:> 所示的多個封裝堆疊,然後執行切 割製程。更具體地,可先進行堆疊然後執行切割製程。在這 種情況下,由於在沒有測試製程的情况下進行封裝單元的^ 裝,與上述實施例相比,封裝結構的最終良率可能會降低。 圖7和圖8是顯示根據本發明的其它實施例的半導體封 裝製造方法的截面圖。這些實施例與圖丨到圖6的實施例相 似。因此,爲了簡潔將省略重復的說明。 根據圖7,封裝結構的封裝單元100a、1〇〇b、1〇〇c和 100d可包括分別具有不同的尺寸和類型的半導體晶片2〇a、 2〇b、2〇c和20d。換句話說’半導體晶片20a、20b、20c和 20d中的至少一個可以與半導體晶片20a、20b、20c和20d中 的至少另一個在尺寸、形狀和功能的一方面或多方面不同。 16 片和邏輯電路晶
Ο 因此,爲了簡潔將省略 200901414 28202pif.doc 在這種情況下,可以很容易實現使用記憶晶 片的積集記憶邏輯。 麥考圖8,根據本實施例的封裝結構,將封裝單元 相對於其它實關的封裝料⑽旋轉。具體地說,將各 裝單元100的賴30比絲10更加接近地附接在基板· 之上。結果,圖8的封裝結構的封裝單元100在與其它實施 例的封裝單元1GG相反的方向(如旋轉約18G度)堆 在基板細之上。在這種情况下,可在沒有基板連接;^ 情況下將封裝單元100焊接至基板焊盤21〇之上。 圖9和圖10是顯示根據本發明的半導體封裝及其製造方 法&截面圖。 這個實施例與上文實施例相似 重復的說明。 芩考圖9和圖丨〇,在基板2〇〇之上形成鈍化層 (pas^atiralayer) 9〇以覆蓋堆疊的封襄單元1〇〇。純化層 90保6蒦封裝單元免受外界因素或雜質的影響。 ,夕|,根據本實施例,可將填膠層(underfm _γ)8〇置於 各封衣單元100之間以及基板200和最底下的一個封裝單元 1〇〇之間。連接件50、基板2⑻、頂層30和底層10可分別 ,、有不同的熱膨脹系數,並且由於熱膨脹系數可將應力施加 在連接件50上。爲了降低不同熱膨脹系數造成的應力,填膠 層8〇可由具有中等熱膨脹系數的材料構成。此外,填膠層8〇 可在結構上支撐封裝單元100。 17 200901414 28202pif.doc 根據本發明的實施例,填膠層8〇 (colloid or jel】y state)的材料構 膠質狀或凍膠狀 10具有更低或相同模量的材料構成。’或由比7頁層30或底層 參考圖10,形成鈍化層9〇以 然而,與圖9的實施例不同,根二$的封裝單元100。 裝單元100之間形成。因此=貫施例,填膠80不在封 空間。 .1ίΚ)之間保留有空白 恨像 到δ的封梦会士姚
實施例的任—個中,並且圖6和圖圖9和圖100 和圖10的實施例中。 破、、、σ構也可用於圖I 根據本發明,半導體晶片被 !包圍。相應地,熱應力或機-=材^^層和肩 收。從而,可以將由浐4 U刀j破頂層和/或底層您 導致的接料靠度的降W的連接件的應力 形成== 供 依序將封裝單元在二”,-曰曰片的封裝單元;和 具有更低模量的射;^板上。底層和麟由比半導體晶片 中’底層和頂層由具有大約10廳和大 在^1"杈1的材料構成。 合物、光’底層和頂層是石夕樹脂化合物、橡膠化 颇月日化合物和合成樹脂化合物中的至少—種。 200901414 28202pif.doc 在其它貫施例中,底層和頂層具有介於大約10 約1000 μηι之間的厚度。 、、、'、 和大 在其它實施例中,半導體晶片具有介於大約 約1000 μπι之間的厚度。 ΗΏΐ和大 在=的其它實施例巾,封鮮元㈣錢 少-個具有焊盤的半導體晶片附接在底層上; 將至 Ο c 頂:二覆蓋半導體晶片;使頂層和底層圖案化以形::二 口箱和介層窗,焊盤開口部份暴露焊盤 開 壁並且形成重新配置結構以接觸焊盤鼓少 用微i:二實施 鑽孔製程的其中之- $機械鑽孔製程和離子束 新配括在形成重 技術、峨凸塊喷射 接件以填’在介層窗的_底部形成連 在仍進一步的實施例中, ,單元的連接件焊接至另一個=的順序堆疊還包括將 連接件的焊接還包括麵 重新配置諸構。 入到另―個封裝單元的介層 悛將封裝單細連接件插 19 200901414 28202pif.doc 在又進-步的實施例中,當相應的加 基板時,封裝單元的連接件的熔點降低。、早凡的位置遠離 在仍進一步的實施例中, _ • 板上堆疊封裝單元之前執行切^形成還包括在於基 元。 口,切割製程分離封裝單 〇 ^在又進—步的實施例中,切割製程使用*射、媳
Cl其中之-,並包括在半導體日κ^田射鑛和刀的 頂層和底層。 曰曰Μ重新配置結構的外面切斷 根據本發明的其它實施例 在基板上的封裝單元,各辦1 + ^封裝包括:依序堆疊 片,實質上包圍半導體晶心有焊盤的半導體晶 接觸焊盤的重新配置結構。半以層,以及貫穿頂層以 半導體晶片具有更低模量的虹曰曰片破比重新配置結構和 7負層和底層包圍。 ,其它實施例中,底層和頂 υ和大約脳之間的模量的材料構成的。 力 在還有的其它實施例中, 橡膠化合物、光敏項層是賴脂化合物、 種。 σ物和合成樹脂化合物中的至少一 , 在也有的其它實施例中,)^爲』 叫大約層㈣層具有介於大約10 叫在它實施例中:半導體“具㈣於大約1〇 μιη和大約100 μιη之間的厚度。 ,、行 20 200901414 28202pif.doc 在步的實施例中,重新配 芸入 穿·;二 在仍進一步的實施例t, Ο 下的另一個封裝單元的介層⑼ 蚕入連接件之上或之 f更t步的貧施例中,當相應的封穿單开的布η 基板%,連接件的熔點降低。 ί裝早兀的位置遲離 以上揭露的主旨當是說明性 所附申請專利範圍者、、7< 而不疋限定性的,並且 更、改良和其它實二一&明的精神和範_的所有的變 内,本發明的範固由以下 律所允許的最大範圍 容許的解釋决定,Μ應該一^圍及其等同物的最大可 定。 〜^又别义的詳細說明的限制或限 【圖式簡單說明】 圖1到圖6是顯示根據 造方法的截面圖。 月的只苑例的半導體封装製 圖7和圖8示根據本發明的 裝製造方法的截面圖。 ~匕,、允例的半導體封 圖9和圖10是顯示根據本 法的截面圖。 ' 、+¥肢封裝及其製造方 【主要元件符號說明】 200901414 28202pif.doc 10 ··底層 20 :半導體晶片 20a :半導體晶片 . 20b:半導體晶片 20c :半導體晶片 20d :半導體晶片
25 :焊盤 I I 30 :頂層 32 :開口部份 34 :介層窗 40 :重新配置結構 50 :連接件 55 :連接件 80 :填膠層 90 :鈍化層 〇 100 :封裝單元 100a :封裝單元 100b :封裝單元 ' 100c:封裝單元 • 100d:封裝單元 200 :基板 210 :基板焊盤 tl .厚度 200901414 28202pif.doc t2 :厚度 t3 :厚度 W :寬度

Claims (1)

  1. 所述封裝單元 f
    200901414 28202pif.doc 十、申請專利範圍· 1.一種半導體封裝,包括: 基板;以及 至少一個置於所述基板之上的封裝單元 包括: 具有焊盤的半導體晶片; 置於所述半導體晶片之下的底声· 』==士:所述底層和_ 連接;=層的重新配置結構’所述重新配置結構電性 其中,所述頂層和所述底層分別包括比所逑重新配置姓 構和所述半導體“具有更傾量的簡。 ° ' 2.如申明專利範圍第丨項所述之半導體封裝,其中 ^層和所述底層分別包括具有介於1 OMPa和廳之間的 挺11:的封料。 【如_請專利範圍第〗項所述之半導體封裝,其中,所 所述頂層包括㊉細旨化合物、橡膠化合物、光敏樹 月曰化合物和合成樹脂化合物中的至少一種。 、+、」·如中請專利朗第1獅述之半導體封裝,其中,所 a & e和所述頂層具有介於】心m和】卿,之間的厚度。 、5.如申請專利範圍第!項所述之半導體封裝,其中,所 U導體晶片具有介於ΙΟμηι和lOOjum之間的厚度。 24 200901414 28202pif.doc 6·如申請專利範圍第1項所述之半導體封裝,其中,所 述重新酉己置結構*戶斤述焊盤處延伸並覆蓋貫穿戶斤述頂層和戶斤 述底層的介層窗的内壁。
    7. 如申請專利範圍第6項所述之半導體封裝,其中,所 述f"少—鋪裝單元包括依序堆®在所述基板之上的多個封 裝單70,且所述各個封裝單元包括置於所述介層窗内的連接 件’其中’所述多_料元的相鄰單元賴述連接件電性 連接所述相鄰封裝單元的所述重新配置結構。 8. 如申請專職圍第7項所述之半導體封裝,還包括將 所述封裝單元的所述連接件紐連接_述絲上的基板谭 盤的基板連接件。 9,如申請專利範圍第7項所述之半導體封裝,其中 遇離所述基板堆疊_裝單元的所述連接件的雜比 所述基板堆疊騎裝單㈣連接件的熔點低。 ^ '· 10.如申請翻範圍第7項所述之半導體封裝,其 所述多個縣單元依料疊在所述基板上, 、 單元的所述頂層比所輕層離所述基板更遠。&封裝 11·如申請專利範圍第7項所述之半導體 =述多個封裝單讀序堆疊在所述基板上,使得中’將 單元的所述底層比所述頂層離所述基板更遠。 <各封裝 、12.如申請專纖㈣7項職之半導· 逑半導體W的至少—個在尺寸、形狀和功^力、中,所 方面與所述半導體晶片的至少另一個不同。 方面或多 25 200901414 28202pif.doc 13. 如申請專利範圍第1項所述之半導體封裝,其中,所 述頂層和所述底層分別包括不同的材料。 14. 如申請專利範圍第1項所述之半導體封裝,其中,所 述頂層和所述底層包括相同的材料。
    26
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