CN101252092A - 多芯片封装结构及其制作方法 - Google Patents
多芯片封装结构及其制作方法 Download PDFInfo
- Publication number
- CN101252092A CN101252092A CNA2008100835725A CN200810083572A CN101252092A CN 101252092 A CN101252092 A CN 101252092A CN A2008100835725 A CNA2008100835725 A CN A2008100835725A CN 200810083572 A CN200810083572 A CN 200810083572A CN 101252092 A CN101252092 A CN 101252092A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon chip
- chip
- packaging structure
- multichip packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 91
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 89
- 239000010703 silicon Substances 0.000 claims abstract description 89
- 238000005520 cutting process Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 140
- 239000002184 metal Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 230000004888 barrier function Effects 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 239000003292 glue Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229920000297 Rayon Polymers 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001652 electrophoretic deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
本发明一种多芯片封装结构的制作方法,其于第一硅片的一预定的切割线上,形成多个局部移除第一硅片以及第一金属层所产生的凹穴,并使第一线路层的导电壁与显露于凹穴中的第一金属层的切割剖面电性连接。此外,第二硅片以其导电凸块压合于一覆盖层中,并与第一线路层电性连接。接着,图案化第一金属层,以形成具有多个第二接垫的一第二线路层。最后,沿着预定的切割线切割第一硅片以及第二硅片,以形成多个分离的多芯片封装结构。
Description
技术领域
本发明涉及一种半导体封装工艺,且特别是关于一种多芯片封装结构的制作方法。
背景技术
随着半导体工艺的进步,球格阵列式构装(Ball Grid Array,BGA)、芯片尺寸构装(Chip-Scale Package,CSP)、覆晶构装(Flip Chip package,F/C package)与多芯片模块(Multi-Chip Module,MCM)等高密度集成电路封装技术也应运而生。对于高密度集成电路封装而言,缩短连结线路的长度将有助信号传递速度的提升,因此凸块(bump)的应用已逐渐成为高密度封装的主流。
图1为现有技术的一种多芯片封装结构的剖面示意图。请参照图1,多芯片封装结构100由一承载器110、一第一芯片120、一第二芯片130、多条焊线140及一封装胶体150所构成。其中,承载器110上具有多个接垫112、114与116。第一芯片120具有一主动表面S1与一背面S2。主动表面S1上配置有多个凸块122。第一芯片120是通过凸块122与接垫112电性连接。此外,第二芯片130配置于第一芯片120上,具有一主动表面S3与一背面S4。第二芯片130的主动表面S3通过多条焊线140与承载器110的接垫116电性连接。封装胶体150包覆第一芯片120、第二芯片130与焊线140,并填充于第一芯片120与承载器110之间。
然而,上述的多芯片封装结构100的整体厚度与大小不易缩小,不但不符合封装技术朝向微型化发展的趋势,更会降低产品在市场上的竞争力。
发明内容
本发明目的是提供一种多芯片封装结构的制作方法,其于第一硅片的预定的切割线上形成多个凹穴,以制作导电壁于凹穴中。
本发明提供一种多芯片封装结构的制作方法,其通过第一线路层的导电壁与显露于凹穴中的第一金属层的切割剖面电性连接。
本发明提供一种多芯片封装结构的制作方法,其于第一硅片的切割剖面上覆盖一隔离层,以提高绝缘性。
本发明提出一种多芯片封装结构的制作方法,包括:提供一第一硅片,该第一硅片具有一主动表面以及相对的一背面,该主动表面上设有多个焊垫;贴附一第一金属层以及一基板于该第一硅片的该背面,该第一金属层位于该第一硅片与该基板之间,该第一金属层以一背胶层与该第一硅片的背面相粘,而该基板以一胶片与该第一金属层相粘;图案化位于该主动表面上的一第一绝缘层,以使该第一绝缘层形成多个显露所述焊垫的开孔;在该第一硅片的一预定的切割线上,形成多个局部移除该第一绝缘层、该第一硅片以及该第一金属层所产生的凹穴;形成一隔离层于所述凹穴中的硅片切割剖面上;形成一具有多个第一接垫的第一线路层于该绝缘层上,且该第一线路层的导电壁与显露于所述凹穴中的该第一金属层的切割剖面电性连接;形成一覆盖层于该第一线路层上以及所述凹穴中;提供一第二硅片,该第二硅片贴附于一载板上,且多个导电凸块形成于该第二硅片上;该第二硅片以所述导电凸块压合于该覆盖层中,并与该第一线路层电性连接;移除该基板以及该胶片,以显露该第一金属层;图案化该第一金属层,以形成具有多个第二接垫的一第二线路层;以及沿着该预定的切割线切割该第一硅片以及该第二硅片,以形成多个分离的多芯片封装结构。
在本发明的一实施例中,在切割第一硅片以及第二硅片的步骤之前,更包括形成一焊罩层于第二线路层上,并显露所述第二接垫。
在本发明的一实施例中,在形成焊罩层的步骤之后,更包括形成一保护层于所述第二接垫上。
在本发明的一实施例中,在形成保护层的步骤之后,更包括形成多个焊球于所述第二接垫上。
在本发明的一实施例中,在切割第一硅片以及第二硅片的步骤之前或之后,更包括移除载板。
本发明提出一种多芯片封装结构,包括一第一芯片、一第二芯片、多个导电凸块、多个导电壁以及一覆盖层。第一芯片具有位于其主动表面上的第一线路层以及位于其背面的第二线路层。第二芯片配置于该第一芯片上,该第二芯片具有位于其主动表面上的第三线路层。多个导电凸块电性连接于该第一线路层与该第三线路层之间。多个导电壁位于该第一芯片的侧缘,并电性连接于该第一线路层与该第二线路层之间。覆盖层位于该第一芯片与该第二芯片之间,且覆盖该第一线路层与所述导电壁。
在本发明的一实施例中,第一芯片还具有一第一绝缘层,经图案化而配置于该第一线路层之下。。
在本发明的一实施例中,第一芯片还具有一背胶层,配置于该第二线路层之下。
在本发明的一实施例中,第二芯片还具有一第二绝缘层,经图案化而配置于该第三线路层之下。
在本发明的一实施例中,一隔离层配置于第一芯片的侧缘与所述导电壁之间。
在本发明的一实施例中,多个焊球配置于第一硅片的背面,并与第二线路层电性连接。
本发明将第一硅片与第二硅片以面对面的方式进行堆叠,不需以焊线与外部的承载器进行打线接合工艺,进而缩小多芯片封装结构的整体厚度与大小。同时,由于第一芯片与第二芯片之间不需经由承载器上的线路,而是以导电壁进行信号传递,因此可简化承载器的电路布局。
为了让本发明的上述特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。
附图说明
图1为现有技术一种多芯片封装结构的剖面示意图;
图2A~图2G分别是本发明一实施例的多芯片封装结构的制作方法之前段流程示意图;
图3A~图3G分别是本发明一实施例的多芯片封装结构的制作方法之后段流程示意图;
图4A~4D是本发明一实施例的第二硅片的制作流程示意图;
图5是图2F的俯视示意图。
【主要组件符号说明】
100:多芯片封装结构
110:承载器
112、114、116:接垫
120:第一芯片
122:凸块
130:第二芯片
140:焊线
150:封装胶体
S1、S2、S3、S4:主动表面
200:第一硅片
202:主动表面
204:背面
206:焊垫
208:防护层
210:第一金属层
212:背胶层
220:基板
222:胶片
230:第一绝缘层
232:开孔
200a:第一硅片的切割剖面
210a:第一金属层的切割剖面
234:隔离层
240:第一线路层
242:第一接垫
244:导电壁
250:覆盖层
260:第二线路层
262:第二接垫
264:保护层
266:焊球
270:焊罩层
300:第二硅片
310:载板
312:粘胶
302:主动表面
304:背面
306:焊垫
308:防护层
330:第二绝缘层
332:开孔
340:第三线路层
342:第三接垫
344:导电凸块
400:多芯片封装结构
200’:第一芯片
300’:第二芯片
C:凹穴
L:切割线
具体实施方式
图2A~图2G分别是本发明一实施例的多芯片封装结构的制作方法的前段流程示意图。在此前段流程中,主要是在第一硅片200上进行,请先参考图2A及图2B的实施例。首先,第一步骤是提供完成集成电路布局及制作的第一硅片200。第一硅片200具有一主动表面202以及相对的一背面204。多个焊垫206配置于主动表面202上,并可显露于覆盖主动表面202的一防护层(passivation layer)208中。接着,第二步骤是贴附一第一金属层210以及一基板220于第一硅片200的背面204。第一金属层210位于第一硅片200与基板220之间。第一金属层210以一背胶层212与第一硅片200的背面204相粘。基板220以一胶片222与第一金属层210相粘。
在本实施例中,第一金属层210例如是背胶铜箔(resin coatedcopper,RCC),其由一胶膜与一铜箔压合而成。基板220例如是玻璃基板、金属基板或含玻纤材料的塑料基板。胶片222例如是离形膜(releasefilm),其可经由加热或紫外线照射而与基板220的粘着力降低来掀离。第一金属层210以背胶层212贴附于第一硅片200的背面204,而基板220以胶片222贴附于第一金属层210上。
接着,请参考图2C及图2D的实施例,第三步骤是图案化位于主动表面202上的一第一绝缘层230,以使第一绝缘层230形成多个显露各个焊垫206的开孔232。之后,第四步骤是在一预定的切割线L上,形成多个局部移除第一绝缘层230、第一硅片200以及第一金属层210所产生的凹穴C。第一绝缘层230例如是环氧树脂或聚酰亚胺等高分子层,其以热压、旋转涂布(spin coating)、喷雾涂布(spray coating)或滚筒涂布(rollcoating)等方式形成于主动表面202上,再经由激光蚀刻或曝光、显影感光性绝缘层等方式形成预定尺寸的开孔232,以显露其下方的焊垫206。此外,凹穴C则是以等离子蚀刻、激光烧蚀或划片刀片(dicing blade)等方式形成在第一硅片200的预定切割线L上,其由第一绝缘层230往下深入至胶片222,因而显露第一硅片的切割剖面200a与第一金属层的切割剖面210a于各个凹穴C中。
接着,请参考图2E及图2F的实施例,第五步骤是形成一隔离层234于这些凹穴C中的第一硅片的切割剖面200a上。第六步骤是形成一具有多个第一接垫242的第一线路层240于第一绝缘层230上。第一线路层240与显露于这些凹穴C中的第一金属层的切割剖面210a电性连接。隔离层234例如是氮化硅或二氧化硅等绝缘沉积材料,或是以电泳沉积法(electrophoretic deposition method)形成的隔离物。此外,第一线路层240例如以溅镀、无电电镀、化学气相沉积技术或其它物理气相沉积技术形成所需的导电物,再经由导电物以电镀方式增厚、蚀刻而形成预定的线路图案。第一线路层240以其上方的第一接垫242与第一硅片200的焊垫206电性连接。第一线路层240更以其导电壁244与显露于各个凹穴C中的第一金属层的切割剖面210a电性连接。有关第一线路层240的线路及第一接垫的排列方式、凹穴的形状及位置,请参考图5的俯视示意图。
接着,请参考图2G的实施例,第七步骤是形成一覆盖层250于第一线路层240上以及各个凹穴C中。覆盖层250例如是异方性导电膜(anisotropic conductive film,ACF)或是与第一线路层240接合性良好的非导电胶。覆盖层250可以是半固化的树脂片,以作为第一硅片200与第二硅片300(见图3A)之间的接合胶。
在完成第一硅片200上的制作流程之后,后续介绍将第二硅片300以覆晶方式配置于第一硅片200上的制作流程,以完成整个多芯片封装结构。
图3A~图3G分别是本发明一实施例的多芯片封装结构的制作方法的后段流程示意图。首先,请参考图3A及图3B的实施例,第一步骤是提供一第二硅片300。第二硅片300贴附于一载板310上,且第二硅片300具有多个导电凸块344,例如是电镀的金凸块、铜凸块或印刷的凸块等。有关第二硅片300的制作方法在后续内容中再详加描述。接着,第二硅片300以导电凸块344合于覆盖层250中,并与第一线路层240电性连接。当覆盖层250为异方性导电膜时,导电凸块344可通过导电膜内的金属微粒与第一线路层240电性连接,而当覆盖层250为非导电胶时,导电凸块344则是刺穿非导电胶而直接与第一线路层240电性连接。相互堆叠的第一硅片200与第二硅片300更可通过热压接合(thermal compression)步骤使覆盖层250(半固化树脂)受热而固化成形。
接着,请参考图3C及图3D的实施例,第三步骤是移除位于第一金属层210下方的基板220及胶片222,以显露第一金属层210。第四步骤是图案化第一金属层210,以形成具有多个第二接垫262的第二线路层260。由于基板220与第一金属层210之间的胶片222经由加热或紫外线照射之后可轻易地掀离,因此不会残留于第一金属层210。此外,第一金属层210可经由曝光、显影以及蚀刻等图案化工艺,来形成具有多个第二接垫262的第二线路层260。第二接垫262可通过各个导电壁244与第一接垫242电性连接,而第一线路层240可通过导电凸块344与第二硅片300电性连接,以达到电性传输的目的。
最后,请参考图3E~图3G。在一实施例中,当完成上述第二线路层260的步骤之后,可沿着预定的切割线L直接切割第一硅片200以及第二硅片300,以形成多个分离的多芯片封装结构;在另一实施例中,当完成上述第二线路层260的步骤之后,先形成图3E中的焊罩层270于第二线路层260上,并显露第二接垫262,接着,于第二接垫262上形成图3F中的一保护层264,例如是镍金层或其它抗氧化层,之后,形成图3F中的多个焊球266于第二接垫262上,最后再沿着预定的切割线L切割第一硅片200以及第二硅片300,并移除载板310及粘胶312,以形成图3G中的多个分离的多芯片封装结构400。在本实施例中,载板310亦可于第一硅片200以及第二硅片300切割之前移除。
以下介绍在第二硅片300上的制作流程,请参考图4A~4D。首先,第一步骤是将第二硅片300贴附于一载板310上。第二硅片300具有一主动表面302以及相对的一背面304。多个焊垫306配置于主动表面302上,并可显露于覆盖主动表面302的一防护层308中。载板以一粘胶312与第二硅片300的背面304相粘,以加强结构的强度。
第二步骤是图案化位于主动表面302上的一第二绝缘层330,以使第二绝缘层330形成多个显露焊垫306的开孔332。接着,第三步骤是形成一具有多个第三接垫342的第三线路层340于第二绝缘层330上,并以第三接垫342与焊垫306电性连接。第四步骤是形成多个导电凸块344于第三接垫342上,例如以电镀或印刷方式形成。在上述的步骤中,第二绝缘层330形成的方式及材料与第一硅片200上的第一绝缘层230形成的方式及材料相似,在此不再赘述。第三线路层340的形成方式及材料与第一硅片200上的第一线路层240的形成方式及材料相似,在此不再赘述。
由以上的工艺可知,在图3G中完成切割之后的多芯片封装结构包括一第一芯片200’、第二芯片300’、多个导电凸块344、多个位于该第一芯片200’侧缘的导电壁244以及一覆盖层250。第一芯片200’具有位于主动表面上的第一线路层240以及位于背面的第二线路层260,而第一线路层240与第二线路层260通过导电壁244电性连接。第二芯片300’具有位于主动表面的第三线路层340,而第三线路层340通过导电凸块344与第一线路层240电性连接。覆盖层250位于第一芯片200’与第二芯片300’之间,且覆盖第一线路层240与这些导电壁244,予以保护。
综上所述,本发明将第一硅片与第二硅片以面对面的方式进行堆叠,不需以焊线与外部的承载器进行打线接合工艺,进而缩小多芯片封装结构的整体厚度与大小。同时,由于第一芯片与第二芯片之间不需经由承载器上的线路,而是以导电壁进行信号传递,因此可简化承载器的电路布局。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附的申请专利范围所界定者为准。
Claims (13)
1.一种多芯片封装结构的制作方法,其特征在于包括:
提供一第一硅片,该第一硅片具有一主动表面以及相对的一背面,该主动表面上设有多个焊垫;
贴附一第一金属层以及一基板于该第一硅片的该背面,该第一金属层位于该第一硅片与该基板之间,该第一金属层以一背胶层与该第一硅片的背面相粘,而该基板以一胶片与该第一金属层相粘;
图案化位于该主动表面上的一第一绝缘层,以使该第一绝缘层形成多个显露所述焊垫的开孔;
在该第一硅片的一预定的切割线上,形成多个局部移除该第一绝缘层、该第一硅片以及该第一金属层所产生的凹穴;
形成一隔离层于所述凹穴中的硅片切割剖面上;
形成一具有多个第一接垫的第一线路层于该第一绝缘层上,且该第一线路层的导电壁与显露于所述凹穴中的该第一金属层的切割剖面电性连接;
形成一覆盖层于该第一线路层上以及所述凹穴中;
提供一第二硅片,该第二硅片贴附于一载板上,且多个导电凸块形成于该第二硅片上;
该第二硅片以所述导电凸块压合于该覆盖层中,并与该第一线路层电性连接;
移除该基板以及该胶片,以显露该第一金属层;
图案化该第一金属层,以形成具有多个第二接垫的一第二线路层;以及
沿着该预定的切割线切割该第一硅片以及该第二硅片,以形成多个分离的多芯片封装结构。
2.如权利要求1所述的多芯片封装结构的制作方法,其特征在于,所述在切割该第一硅片以及该第二硅片的步骤之前,还包括形成一焊罩层于该第二线路层上,并显露所述第二接垫。
3.如权利要求2所述的多芯片封装结构的制作方法,其特征在于,所述在形成该焊罩层的步骤之后,还包括形成一保护层于所述第二接垫上。
4.如权利要求3所述的多芯片封装结构的制作方法,其特征在于,所述在形成该保护层的步骤之后,还包括形成多个焊球于所述第二接垫上。
5.如权利要求1所述的多芯片封装结构的制作方法,其特征在于,所述在切割该第一硅片以及该第二硅片的步骤之前或之后,还包括移除该载板。
6.如权利要求1所述的多芯片封装结构的制作方法,其特征在于,所述覆盖层为异方性导电膜。
7.如权利要求1所述的多芯片封装结构的制作方法,其特征在于,所述覆盖层为非导电胶。
8.一种多芯片封装结构,其特征在于包括:
一第一芯片,具有位于其主动表面上的第一线路层以及位于其背面的第二线路层;
一第二芯片,配置于该第一芯片上,该第二芯片具有位于其主动表面上的第三线路层;
多个导电凸块,电性连接于该第一线路层与该第三线路层之间;
多个导电壁,位于该第一芯片的侧缘,并电性连接于该第一线路层与该第二线路层之间;以及
一覆盖层,位于该第一芯片与该第二芯片之间,且覆盖该第一线路层与所述导电壁。
9.如权利要求8所述的多芯片封装结构,其特征在于,还包括多个焊球,其配置于该第一硅片的背面,并与该第二线路层电性连接。
10.如权利要求8所述的多芯片封装结构,其特征在于,该第一芯片还具有一第一绝缘层,经图案化而配置于该第一线路层之下。
11.如权利要求8所述的多芯片封装结构,其特征在于,该第一芯片还具有一背胶层,配置于该第二线路层之下。
12.如权利要求8所述的多芯片封装结构,其特征在于,该第二芯片还具有一第二绝缘层,经图案化而配置于该第三线路层之下。
13.如权利要求8所述的多芯片封装结构,其特征在于,还包括一隔离层,配置于该第一芯片的侧缘与所述导电壁之间。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008100835725A CN101252092B (zh) | 2008-03-12 | 2008-03-12 | 多芯片封装结构及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008100835725A CN101252092B (zh) | 2008-03-12 | 2008-03-12 | 多芯片封装结构及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101252092A true CN101252092A (zh) | 2008-08-27 |
CN101252092B CN101252092B (zh) | 2011-07-06 |
Family
ID=39955408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008100835725A Active CN101252092B (zh) | 2008-03-12 | 2008-03-12 | 多芯片封装结构及其制作方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101252092B (zh) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7906377B2 (en) | 2008-12-24 | 2011-03-15 | Via Technologies, Inc. | Fabrication method of circuit board |
CN101866895B (zh) * | 2009-04-20 | 2012-03-21 | 日月光半导体制造股份有限公司 | 芯片结构及其形成方法 |
CN102543868A (zh) * | 2010-12-10 | 2012-07-04 | 台湾积体电路制造股份有限公司 | 切割半导体结构的方法 |
CN101510515B (zh) * | 2008-12-24 | 2012-09-05 | 威盛电子股份有限公司 | 线路板及其制作方法及芯片封装结构 |
CN103779303A (zh) * | 2012-10-18 | 2014-05-07 | 英飞凌科技股份有限公司 | 凸点式封装及其形成方法 |
CN104008982A (zh) * | 2013-02-23 | 2014-08-27 | 南茂科技股份有限公司 | 芯片封装工艺及芯片封装 |
CN104701197A (zh) * | 2013-12-10 | 2015-06-10 | 半导体元件工业有限责任公司 | 半导体器件的制造方法及其结构 |
CN108117042A (zh) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及制备方法、电子装置 |
WO2022161247A1 (zh) * | 2021-01-29 | 2022-08-04 | 中芯集成电路(宁波)有限公司 | 一种晶圆级系统封装结构及封装方法 |
-
2008
- 2008-03-12 CN CN2008100835725A patent/CN101252092B/zh active Active
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7906377B2 (en) | 2008-12-24 | 2011-03-15 | Via Technologies, Inc. | Fabrication method of circuit board |
CN101510515B (zh) * | 2008-12-24 | 2012-09-05 | 威盛电子股份有限公司 | 线路板及其制作方法及芯片封装结构 |
CN101866895B (zh) * | 2009-04-20 | 2012-03-21 | 日月光半导体制造股份有限公司 | 芯片结构及其形成方法 |
CN102543868A (zh) * | 2010-12-10 | 2012-07-04 | 台湾积体电路制造股份有限公司 | 切割半导体结构的方法 |
CN103779303A (zh) * | 2012-10-18 | 2014-05-07 | 英飞凌科技股份有限公司 | 凸点式封装及其形成方法 |
US9373609B2 (en) | 2012-10-18 | 2016-06-21 | Infineon Technologies Ag | Bump package and methods of formation thereof |
CN104008982A (zh) * | 2013-02-23 | 2014-08-27 | 南茂科技股份有限公司 | 芯片封装工艺及芯片封装 |
CN104008982B (zh) * | 2013-02-23 | 2017-11-24 | 南茂科技股份有限公司 | 芯片封装工艺及芯片封装 |
CN104701197A (zh) * | 2013-12-10 | 2015-06-10 | 半导体元件工业有限责任公司 | 半导体器件的制造方法及其结构 |
CN104701197B (zh) * | 2013-12-10 | 2019-07-16 | 半导体元件工业有限责任公司 | 半导体器件的制造方法及其结构 |
CN108117042A (zh) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及制备方法、电子装置 |
WO2022161247A1 (zh) * | 2021-01-29 | 2022-08-04 | 中芯集成电路(宁波)有限公司 | 一种晶圆级系统封装结构及封装方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101252092B (zh) | 2011-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101252092B (zh) | 多芯片封装结构及其制作方法 | |
US20200251422A1 (en) | Semiconductor device having emi shielding structure and related methods | |
CN101252096B (zh) | 芯片封装结构以及其制作方法 | |
CN105047652B (zh) | 半导体器件的封装结构及制作方法 | |
CN107845625A (zh) | 芯片封装结构 | |
CN103367321B (zh) | 芯片装置及形成芯片装置的方法 | |
CN107331625A (zh) | 半导体器件的封装结构及其制作方法 | |
TW200939428A (en) | Multi-chip package structure and method of fabricating the same | |
US9338886B2 (en) | Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device | |
JP5615936B2 (ja) | パネルベースのリードフレームパッケージング方法及び装置 | |
JP5942823B2 (ja) | 電子部品装置の製造方法、電子部品装置及び電子装置 | |
CN106711105A (zh) | 覆盖金属层填充孔或槽的封装结构及制作方法 | |
US7192803B1 (en) | Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint | |
CN101944519A (zh) | 具备密封层的半导体器件及半导体器件的制造方法 | |
TWI465163B (zh) | 具有內建加強層之凹穴基板及其製造方法 | |
US7811863B1 (en) | Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment | |
US7494843B1 (en) | Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding | |
CN101673790A (zh) | 发光二极管及其制造方法 | |
CN110473853A (zh) | 一种dfn器件的封装结构、无引线框架载体及dfn器件的封装方法 | |
CN101800184B (zh) | 具凹穴结构的封装基板及其制作方法 | |
CN108962764A (zh) | 半导体结构的形成方法、半导体芯片、封装方法及结构 | |
CN103779245B (zh) | 芯片封装方法及封装结构 | |
KR20090071444A (ko) | 반도체 장치의 제조 방법 | |
JP4420965B1 (ja) | 半導体装置内蔵基板の製造方法 | |
CN102446775A (zh) | 无载具的半导体封装件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |