CN104701197A - 半导体器件的制造方法及其结构 - Google Patents

半导体器件的制造方法及其结构 Download PDF

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CN104701197A
CN104701197A CN201410539418.XA CN201410539418A CN104701197A CN 104701197 A CN104701197 A CN 104701197A CN 201410539418 A CN201410539418 A CN 201410539418A CN 104701197 A CN104701197 A CN 104701197A
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projection
conductor
protective layer
semiconductor
layer
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CN104701197B (zh
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R·D·莫叶丝
萨德哈玛·C·沙斯特瑞
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本发明涉及半导体器件的制造方法及其结构。在一个实施例中，导体凸块形成在半导体器件的凸块下导体上，从凸块下导体的表面延伸第一距离，包括在导体凸块外表面上形成保护层，其中多个半导体管芯随后通过用刻蚀剂刻蚀贯通半导体衬底切单，以及其中保护层保护导体凸块不受刻蚀剂刻蚀。

Description

半导体器件的制造方法及其结构
背景技术
本发明一般涉及电子设备，更具体来说，涉及半导体及其结构，以及半导体器件的制造方法。
过去，半导体工业采用各种方法和结构来在半导体管芯上形成金属凸块。典型地，金属凸块被施加于半导体管芯的连接区域上并且用于将半导体管芯上的区域互连至半导体管芯外的其他结构，如其他半导体管芯、印刷电路板、陶瓷衬底或其他类型的结构。在一个实施例中，金属凸块由焊料或其他沉积在半导体管芯上的材料形成。在一些情况下，在管芯从半导体晶圆单片化之前，焊料已经施加到管芯上。
在一些应用中，部分金属凸块可能在从半导体晶圆单片化半导体管芯的工艺期间脱落，这使得半导体管芯很难贴附到其他结构上。
因此，需要具有在半导体管芯上形成凸块的方法，使其降低在管芯单片化期间脱落的凸块材料的量，和/或具有更易于贴附至另一个结构的半导体管芯上的凸块结构。
附图简要说明
图1示出了依照本发明的、包括多个半导体管芯的半导体晶圆的示例实施例的平面图；
图2示出了依照本发明的、图1的部分半导体晶圆的示例实施例的放大平面图；以及
图3示出了依照本发明的、图1的部分半导体晶圆的示例实施例的放大截面图。
为了说明的简单和清楚起见，图中的元件未必按比例绘制，一些元件可能由于说明的目的而被夸大了，并且除非另有说明，否则不同图中的相同参考标记代表相同的元件。另外，为了描述的简单起见而省略了公知的步骤和元件的描述和细节。本文所使用的电流载流电极意味着通过器件载运电流的器件元件，如MOS晶体管的源极或漏极，或双极晶体管的发射极或集电极，或二极管的阴极或阳极，并且控制电极意味着通过器件控制电流的器件元件，如MOS晶体管的栅极，或双极晶体管的基极。尽管本文将器件解释为某些N-沟道或P-沟道器件，或某些N型或P型掺杂区域，但是本领域技术人员将了解依照本发明的互补器件也是可能的。本领域技术人员应理解，导电类型指的是例如通过传导空穴或电子发生导电所用的机制，因此，导电类型并非指的是掺杂浓度而指的是掺杂类型，如P-型或N-型。本领域技术人员将了解，，本文所使用的期间、同时和当......时与电路操作有关的词并非意味着在启动动作后立即发生动作的精确的术语，而是意味着可能会有某一小的但合理的延迟，如在由初始动作启动的反应之间的各种传播延迟。此外，术语和......同时意味着至少在启动动作的持续时间的某一部分内发生某一动作。词语大约或基本上的使用意味着具有预期接近规定的值或位置的参数的元素值。然而，如本领域所熟知的，总是存在不能使值或位置被精确叙述的小方差。本领域已经确证，根据精确描述的理想的目标，高达至少百分之十(10％)(对于半导体掺杂浓度而言高达百分之二十(20％))的方差都是合理的方差。当参照信号状态使用时，术语“确立(asserted)”意味着信号的有效状态，且术语“取消(negated)”意味着信号的非有效状态。信号的实际电压值或逻辑状态(如“1”或“0”)取决于使用正逻辑还是负逻辑。因此，取决于使用正逻辑还是负逻辑，确定可以是高电压或高逻辑(high logic)或低电压或低逻辑(low logic)，并且取决于使用正逻辑还是负逻辑，否定可以是低电压或低状态(low state)或高电压或高逻辑。本文使用正逻辑公约，但是本领域技术人员应理解，也可以使用负逻辑公约。权利要求和/或具体实施方式中在元件名称的一部分中使用的术语第一、第二、第三等用于区分类似的元件，并且未必用于以排序或任何其他方式描述时间、空间上的顺序。应理解，这样使用的术语在适当的情况下可互换，并且本文所描述的实施例能够以不同于本文描述或说明的顺序操作。为了附图的清楚起见，器件结构的掺杂区域显示为通常具有直线边缘和精确的拐角。然而，本领域技术人员应理解，由于掺杂剂的扩散和活化，掺杂区域的边缘通常不会是直线，且拐角也不会是精确的角度。
具体实施方式
图1示出了包括多个半导体管芯的半导体晶圆10的示例实施例的平面图，如形成在半导体衬底上的管芯12、14和16。典型地，半导体管芯经由管芯将被彼此切割分离的半导体晶圆的切单区域(singulation regions)被彼此分离，例如通过穿过晶圆10的底层部分形成切单开口或通过切割贯穿晶圆10。一般来说，术语切单指的是将结合在一起作为晶圆的管芯从晶圆分离成各个单元或各个管芯，或者从晶圆分离一个管芯或多个管芯。一般地，晶圆10的一些切单区域通过切单线示出，如线13和15，管芯由此在那里被彼此切割开来。本领域技术人员将理解，线13和15未必是在晶圆10上画的线，而是代表晶圆10的管芯将被彼此切割开来的区域。本领域技术人员也应理解，切单线下方的部分半导体晶圆和半导体衬底典型地并不是最终切割后的半导体管芯的部分。
图2示出了包括部分切单线13和部分管芯12和14的部分晶圆10的示例实施例的放大平面图。典型地，管芯12和14包括用于将管芯12和14互连至其他结构的连接区域。例如，管芯12可包括促进在管芯12的区域和其他结构之间形成电连接的凸块结构20和21。管芯14可包括类似于结构20和21的凸块结构23和24。本领域技术人员应懂得，尽管管芯12和14被显示为包括两个凸块结构，但是其他管芯实施例可仅具有一个或可具有多于两个的凸块结构。尽管凸块结构20-21和23-24被显示为具有长方形形状，但是在其他实施例中它们可具有其他形状，包括圆形或其他形状。
图3示出了沿图2示出的横截面线3-3的晶圆10的部分管芯12的示例实施例的放大截面图。该描述参考图2和图3。
典型地，管芯12和14形成在通常是晶圆10的一部分的半导体衬底27上。本领域技术人员应懂得，在一些实施例中，衬底27可包括在其上形成有其他半导体层的体半导体衬底。例如，衬底27可包括在其上形成有一个或多个外延层的体半导体衬底，或可包括键合至另一个体衬底的一个体衬底晶圆，或可包括其他半导体材料。在一些实施例中，管芯12和14可包括用于在衬底27上形成有源器件的有源区域(未示出)。管芯12和14可任选地包括其他掺杂区域，如管芯12的掺杂区域29和30，例如其可用于在管芯12和14的元件与管芯12和14外部的结构之间形成低电阻电连接。
管芯12和14可在可以形成凸块结构(例如管芯12的结构20和21)的位置包括可选择的凸块下导体。例如，凸块下导体34可形成在将形成凸块结构20的位置，且凸块下导体44可形成在将形成凸块结构21的位置。本领域技术人员应当懂得，凸块下导体34和44可由与衬底27或衬底27上形成的区域(例如区域29和30)形成低电阻接触(例如欧姆接触)的材料形成。用于形成导体34和44的材料是本领域公知的，且可包括如铝、铝-硅合金、铜、铝-铜合金、铜-硅合金的材料和其他公知的导体材料。在一些实施例中，可选择的阻挡层，如阻挡层37和46，可形成在导体34和44各自的表面上以防止导体材料从各自的结构20和21向导体34和44扩散，且反之亦然。用于层37和46的材料可以为镍、钛、钨、钛-钨合金、或其他最小化导体材料扩散的公知材料。在一个实施例中，层37和46可被认为是导体34和44的一部分。
在一些实施例中，半导体晶圆的至少一些半导体管芯可通过使用刻蚀技术从半导体晶圆切单，该刻蚀技术形成贯穿可能位于切单线下面的至少部分晶圆10材料的开口。这类用于管芯切单的刻蚀技术的例子在美国专利7,781,310，7,989,319和8,012,857中有描述，其被引用在本文作为参考。这类刻蚀技术可指的是等离子切单或干法划片。在这种切单工艺期间，由前述方法或前述凸块结构形成的一些凸块材料会脱落是有可能的。
在下文中将进一步看到，形成凸块结构20-21和23-24，以便于在各个管芯12和14的元件与其他外部结构之间形成低电阻电连接，并保护该凸块结构或可选地最小化可能脱落的凸块导体的量。在一些实施例中，衬底27的表面可具有绝缘体或电介质，如绝缘体32，其可形成在衬底27的部分表面上。例如，绝缘体32的一些实施例可包括覆盖管芯12特定区域的其他类型绝缘体或场氧化层。典型地，在结构20和23将形成的区域中形成贯穿绝缘体32的开口。凸块下导体34和44可形成在这些开口中，例如在衬底27的表面上或相应的区域29和30上。在非限制性实例中，导体材料可施加到衬底27的表面且被图案化以形成导体34和44。
在一些实施例中，可选择的钝化层35可形成在晶圆10上且覆盖管芯12和14的至少一部分以减少管芯12和14外部的材料对管芯12和14的污染。本领域技术人员应懂得，钝化层与用于隔开管芯12和14的导体的绝缘体不同，如和层间绝缘体不同，以及和场氧化区域不同，并且和绝缘体32不同，以及在一些示例实施例中，钝化层可包括氮化硅。实施例可包括，钝化层35可形成在衬底27的表面上，且被图案化以形成暴露部分凸块下导体34和44的开口。在图案化层35期间，可去除或不去除可能位于切单区域(如切单线13内)内的部分层35。在一个非限制性示例实施例中，层35可与导体34或44邻接。在其他实施例中，可略去层35或可位于不同的位置。在一个非限制性实施例中，绝缘体32的一部分或另一个相似的绝缘体可与导体34和44的一个或两个邻接。
导体凸块可形成在凸块下导体上。例如，导体凸块38和47可分别形成在导体34和44上。典型地，凸块38和47形成为分别从导体34和44的表面延伸一段距离41。在一个实施例中，距离41可大约在5到30微米(5-30μ)。在另一个实施例中，距离41可大约为25微米(25μ)左右，有大约百分之十(10％)的公差。另一个实施例可包括从导体34和44的表面形成不少于10微米(10μ)的距离41。在另一个实施例中，凸块38和47可形成在管芯12的另外部分上或其他材料上，而不是在导体34和44上。凸块38和47可由便于将管芯12附着到管芯12外部的其他结构上的导体材料形成。凸块38和47可由金属、金属合金、或其他导体材料形成。在一个非限制性示例实施例中，凸块38和47可由金-锡合金形成。保护层，如保护层39和48，可分别形成在部分凸块38和47上。用于层39和48的材料可以为导体，并且可以是如下材料，其蚀刻速率低于使用干法划片切单方法从晶圆10切单管芯(如管芯12和14)的刻蚀剂刻蚀凸块38和47的材料。在一个非限制性示例实施例中，凸块38和47的材料可以比层39和48的材料快大约二到一百(2-100)倍被刻蚀。一个非限制性示例实施例可包括刻蚀剂可以是氟基等离子体。实施例可包括，用于层39和48的材料可以是这样的材料，其刻蚀速率低于使用干法划片切单方法用于从晶圆10切单管芯12和/或14的刻蚀剂刻蚀硅的速率。一个非限制性示例实施例中，衬底27的材料可以比层39和48的材料快大约十(10)倍被刻蚀。
随后，管芯12和14可通过刻蚀贯穿晶圆10的开口，如在由切单线13标识的区域中，从晶圆10切单。层39和48的材料被认为在用于切单管芯12和14的刻蚀操作中期间可比凸块38和47的材料刻蚀速率低。本领域技术人员应当懂得，在用于切单管芯12和14的刻蚀操作之前或之后，可使用其他刻蚀操作来清洗晶圆10。典型地，层39和48的厚度选择为在从晶圆10切单管芯12和14后保留一部分层39和48。在一个非限制性示例实施例中，凸块38和47的材料可由包含大约百分之十到九十五(10％-95％)重量比的锡的金-锡合金形成。在一个实施例中，每个层39和48的材料均可为具有大约25到100纳米(25-100nm)厚度的金层。在一个实施例中，层39和48的材料可包括合金。在另一个非限制性示例实施例中，凸块38和47的材料可由包含大约百分之十五到二十(15-20％)重量比的金的金-锡合金形成。在一个示例实施例中，在管芯12贴附到其他结构后，由层39和48残留的金可改变金-锡合金的结构20和21的成分。在另一个实施例中，金与锡的比例可不同且层39和48的厚度也可不同。在一个非限制性示例实施例中，在切单操作中，大约30纳米(30nm)的层39和48的材料会被移除。在另一个实施例中，层39和48可在切单操作期间完全被移除。
其他实施例可包括，用于凸块38和47的材料和用于层39和48的材料一起形成结构20和21，以具有大约200到350(200-350)摄氏度的液相温度。在另一个实施例中，层39和48可由包括铂或钯的其他实质上惰性材料形成。在另外的实施例中，凸块38和47可由如锡-锑合金的其他材料形成。一个非限制性示例实施例可包括锡-锑合金的锑含量可为大约百分之五到二十(5-20％)重量比。一个实施例可包括包含锡-银合金的凸块38和47。
在另一个示例实施例中，阻挡层39和48可由锡形成。锡被认为是其刻蚀速率可快于金但仍比凸块38和47的材料或衬底27的硅的刻蚀速率慢。锡的厚度足够厚，以致于切单工艺不会移除所有的锡材料或可移除所有的锡材料以及少量的凸块38和47的材料，例如小于百分之十(10％)且优选少于百分之一(1％)。
在一个实施例中，管芯12(或管芯14)可为倒装，这样结构20就放置于管芯12所贴附的结构上。可加热管芯12和其他结构的组合，从而结构20的材料贴附于其他结构。在一个实施例中，热回流结构20的材料使得结构20与其他结构的一部分形成共熔键合(bond)。在回流操作中，层39的材料与凸块38的材料混合以形成得到的合金中的导体的结果比例。阻挡层39和/或48最小化在切单操作期间从凸块38和47被移除的材料量，这促进了凸块结构与其他结构形成牢固的机械连接和低电阻电连接。
本领域技术人员应当懂得，在一个实施例中，形成半导体器件的方法可包括：
提供半导体晶圆(如以晶圆10为例)，其包括半导体衬底(如以衬底27为非限制性例子)，半导体晶圆具有形成在半导体衬底上且通过切单区域(如以区域13为例)彼此分离的多个半导体管芯(例如12和/或14中的一个或两个)，其中多个半导体管芯包括凸块下导体(如以导体34和/或44为例)并且其中多个半导体管芯还包括绝缘体(如绝缘体32)或钝化层(如以钝化层35为例)中的一个，其邻接凸块下导体且覆盖半导体晶圆的部分表面；
在凸块下导体上形成导体凸块(以凸块38和/或47为例)，并从凸块下导体的表面延伸离开第一距离；以及
在所述导体凸块的外表面上形成保护层，包括形成作为第一材料的保护层，所述保护层对于用于切单所述半导体管芯的刻蚀剂保护所述导体凸块。
方法的另一个实施例包括形成作为金属合金的导体凸块，且其中形成保护层包括形成保护层的第一材料以包括金属合金的一种材料。
一个实施例可包括由包含金的材料形成保护层且保护层覆盖导电凸块。
在一个实施例中，所述方法可包括形成覆盖导电凸块且具有25到150纳米之间的厚度的金层作为保护层。
一个实施例可包括形成作为金属合金的导体凸块，且其中形成保护层包括形成第一材料的保护层，第一材料包括不是金属合金组分的金属。
另一个实施例可包括形成大于凸块下导体的厚度的导体凸块的第一距离。
方法的一个实施例可包括由第二材料形成导体凸块，第二材料与凸块下导体的第三材料不同。
在一个实施例中，方法还可包括在凸块下导体上形成阻挡层，其中阻挡层是凸块下导体的一部分。
一个实施例可包括由第一材料形成保护层，第一材料以低于导体凸块的刻蚀速率被刻蚀半导体衬底的刻蚀剂刻蚀，其中刻蚀剂用于从半导体晶圆切单多个半导体管芯。
本领域技术人员应当懂得，半导体器件可包括：
半导体衬底，具有形成在所述半导体衬底上的有源元件；凸块下导体，用于形成与所述有源元件的电连接；导电凸块，形成在所述凸块下导体上，所述导电凸块包括第一材料；以及保护层，形成在所述导电凸块的表面上，其中所述保护层包括第二材料，所述第二材料以低于所述第一材料的刻蚀速率被刻蚀所述半导体衬底的半导体材料的刻蚀剂刻蚀。
在另一个实施例中，半导体器件可包括：所述第一材料可以是合金，且所述第二材料可以是所述合金中的一种材料。
另一个实施例可包括，所述合金包括具有大约百分之十五到百分之二十的锡的金锡合金或具有大约百分之五到百分之十五的锡的锑锡合金之一的合金。
一个实施例可包括，所述凸块下导体包括所述第一材料上的阻挡层。
在一个实施例中，半导体器件可包括包含惰性导体材料的保护层。
本领域技术人员应当懂得，形成半导体器件的方法可包括：
提供包含半导体衬底的半导体晶圆，所述半导体晶圆具有形成在所述半导体晶圆上且通过至少一个切单区域彼此隔开的多个半导体管芯；在所述半导体管芯上形成导体凸块，并从所述半导体管芯的表面延伸离开第一距离；以及在所述导体凸块的外表面上形成保护层，其中所述多个半导体管芯随后通过利用刻蚀剂刻蚀贯穿所述半导体衬底被切单，并且其中所述保护层相对于所述刻蚀剂保护所述导体凸块。
方法的一个实施例可包括，形成所述保护层包括形成覆盖所述导体凸块的锡层作为所述保护层。
方法的一个实施例可包括提供半导体管芯，所述半导体管芯包含凸块下导体，以及包括邻接凸块下导体的钝化层或绝缘体之一，并且其中所述钝化层覆盖所述半导体衬底的部分表面。
一个实施例可包括形成保护层，其中保护层的厚度被刻蚀剂减小。
考虑到上述所有内容，显然公开了新颖的器件和方法。除了其他特征之外，包括形成凸块结构，其包括导体凸块上的阻挡层。阻挡层以低于凸块材料的速率被可用于从半导体晶圆切单半导体管芯的刻蚀剂刻蚀。得到的凸块结构便于在管芯12和/或14的元件与管芯12和/或14将被附接到的其他结构之间形成坚固的机械连接和低电阻电连接。
虽然使用特别优选实施例和示例实施例描述说明书的主题内容，但是前述附图及其说明仅描述了主题内容的典型示例实施例，并不因此被认为是对其范围的限制，显然对本领域技术人员来说，可进行多种替换和变化是明显的。本领域技术人员将懂得，结构20和21的示例形状可与所描述的示例实施例不同，只要层39和48的材料降低在管芯切单操作中从凸块38和47移除的材料的量即可。
如下文权利要求所反映的，创造性方面可在于少于单个上述公开的实施例的所有特征。因此，下文表达的权利要求据此明确并入附图的详细说明中，其中每个权利要求独立地作为本发明的单独实施例。此外，本领域技术人员应当理解，虽然本文所描述的一些实施例包括一些特征但是不包含在其他实施例中的其他特征，但是不同的实施例的特征的组合意欲在本发明的范围内，并且形成不同的实施例。

Claims (20)

1.一种形成半导体器件的方法，包括：
提供包括半导体衬底的半导体晶圆，所述半导体晶圆具有形成在所述半导体衬底上且通过切单区域彼此分离的多个半导体管芯，其中所述多个半导体管芯包括凸块下导体，并且其中所述多个半导体管芯还包括绝缘体或钝化层之一，其邻接所述凸块下导体且覆盖半导体晶圆的部分表面；
在所述凸块下导体上形成导体凸块，并从所述凸块下导体的表面延伸离开第一距离；以及
在所述导体凸块的外表面上形成保护层，包括形成作为第一材料的保护层，所述保护层对于用于切单所述半导体管芯的刻蚀剂保护所述导体凸块。
2.如权利要求1所述的方法，其中形成所述导体凸块包括形成作为金属合金的导体凸块，且其中形成所述保护层包括形成保护层的第一材料以包括金属合金的一种材料。
3.如权利要求2所述的方法，其中形成所述保护层包括由包含金的材料形成所述保护层，且所述保护层覆盖所述导电凸块。
4.如权利要求3所述的方法，其中形成所述保护层包括形成覆盖所述导电凸块且具有25到150纳米之间厚度的金层作为所述保护层。
5.如权利要求1所述的方法，其中形成所述导体凸块包括形成作为金属合金的导体凸块，并且其中形成所述保护层包括形成所述第一材料的保护层，所述第一材料包括不是所述金属合金组分的金属。
6.如权利要求1所述的方法，其中形成所述导体凸块包括形成大于所述凸块下导体的厚度的所述导体凸块的第一距离。
7.如权利要求1所述的方法，其中形成所述导体凸块包括由第二材料形成所述导体凸块，所述第二材料与所述凸块下导体的第三材料不同。
8.如权利要求1所述的方法，进一步包括在所述凸块下导体上形成阻挡层，其中所述阻挡层是所述凸块下导体的一部分。
9.如权利要求1所述的方法，其中形成所述保护层包括由第一材料形成所述保护层，所述第一材料以低于所述导体凸块的刻蚀速率被刻蚀所述半导体衬底的刻蚀剂刻蚀，其中所述刻蚀剂用于从所述半导体晶圆切单所述多个半导体管芯。
10.一种半导体器件，包括：
半导体衬底，具有形成在所述半导体衬底上的有源元件；
凸块下导体，用于形成与所述有源元件的电连接；
导电凸块，形成在所述凸块下导体上，所述导电凸块包括第一材料；以及
保护层，形成在所述导电凸块的表面上，其中所述保护层包括第二材料，所述第二材料以低于所述第一材料的刻蚀速率被刻蚀所述半导体衬底的半导体材料的刻蚀剂刻蚀。
11.如权利要求10所述的半导体器件，其中所述第一材料是合金，且所述第二材料是所述合金中的一种材料。
12.如权利要求11所述的半导体器件，其中所述合金包括具有大约百分之十五到百分之二十的锡的金锡合金或具有大约百分之五到百分之十五的锡的锑锡合金之一的合金。
13.如权利要求10所述的半导体器件，其中所述凸块下导体包括所述第一材料上的阻挡层。
14.如权利要求10所述的半导体器件，其中所述刻蚀剂包括氟基刻蚀剂。
15.如权利要求10所述的半导体器件，其中所述刻蚀剂包括氟等离子体。
16.如权利要求10所述的半导体器件，其中所述保护层包括惰性导体材料。
17.一种形成半导体器件的方法，包括：
提供包含半导体衬底的半导体晶圆，所述半导体晶圆具有形成在所述半导体晶圆上且通过至少一个切单区域彼此隔开的多个半导体管芯；
在所述半导体管芯上形成导体凸块，并从所述半导体管芯的表面延伸离开第一距离；以及
在所述导体凸块的外表面上形成保护层，其中所述多个半导体管芯随后通过利用刻蚀剂刻蚀贯穿所述半导体衬底被切单，并且其中所述保护层相对于所述刻蚀剂保护所述导体凸块。
18.如权利要求17所述的方法，其中形成所述保护层包括形成覆盖所述导体凸块的锡层作为所述保护层。
19.如权利要求17所述的方法，其中提供包含所述半导体衬底的所述半导体晶圆包括提供半导体管芯，所述半导体管芯包含凸块下导体，以及包括邻接凸块下导体的钝化层或绝缘体之一，并且其中所述钝化层覆盖所述半导体衬底的部分表面。
20.如权利要求17所述的方法，其中形成所述保护层包括形成其中所述保护层的厚度被所述刻蚀剂减小的保护层。
CN201410539418.XA 2013-12-10 2014-09-16 半导体器件的制造方法及其结构 Active CN104701197B (zh)

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