US20230005807A1 - Zinc Layer For A Semiconductor Die Pillar - Google Patents

Zinc Layer For A Semiconductor Die Pillar Download PDF

Info

Publication number
US20230005807A1
US20230005807A1 US17/931,828 US202217931828A US2023005807A1 US 20230005807 A1 US20230005807 A1 US 20230005807A1 US 202217931828 A US202217931828 A US 202217931828A US 2023005807 A1 US2023005807 A1 US 2023005807A1
Authority
US
United States
Prior art keywords
layer
tiw
semiconductor device
copper
semiconductor die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US17/931,828
Inventor
Nazila Dadvand
Keith Edward Johnson
Christopher Daniel Manack
Salvatore Frank Pavone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US17/931,828 priority Critical patent/US20230005807A1/en
Publication of US20230005807A1 publication Critical patent/US20230005807A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Definitions

  • This invention relates to the fabrication of a pillar over a via of a semiconductor die.
  • FIG. 1 is a cross-sectional view of a packaged semiconductor device in accordance with the present invention.
  • FIG. 2 is a method for fabricating the packaged semiconductor device of FIG. 1 .
  • FIGS. 3 - 11 are cross-sectional diagrams of selected steps of the method of FIG. 2 .
  • FIG. 12 is a cross-sectional view of an alternative packaged semiconductor device in accordance with the present invention.
  • FIG. 13 is a method for fabricating the alternative packaged semiconductor device of FIG. 12 .
  • FIGS. 14 - 24 are cross-sectional diagrams of selected steps of the alternative method of FIG. 13 .
  • FIG. 1 is a cross-sectional view of a packaged semiconductor device 10 in accordance with an example embodiment.
  • the packaged semiconductor device 10 contains a semiconductor die 20 that has copper vias 30 connected to electrical circuitry (not shown) within the semiconductor die 20 .
  • the copper vias 30 may be formed with a conventional process, such as etching via holes into the surface of the semiconductor die 20 , coating the surface of the semiconductor die 20 with titanium tungsten (TiW), coating the TiW surface with copper, using an electroplating process to fill the via holes with copper, and then polishing the TiW and Cu off the surface of the semiconductor die 20 .
  • the vias may be formed by depositing tungsten (W) instead of Cu into the via holes (over the coating of TiW).
  • the semiconductor die 20 is electrically and physically attached to a multi-layered solder resist printed circuit board (PCB) 40 .
  • the PCB 40 contains multiple layers of electrical traces that properly direct electrical signals within the PCB.
  • the PCB 40 contains leads 50 that electrically connect the PCB 40 and the semiconductor die 20 to other electrical devices (not shown) within an electrical system.
  • the semiconductor die 20 is attached to pads 35 of the PCB through a layer of TiW 60 , a copper pillar 70 , and solder resist 80 . Molding compound 90 encapsulates the semiconductor die 20 and portions of the PCB 40 . Note that the surface of leads 50 is often left unencapsulated to facilitate their electrical interconnection to other electrical devices.
  • the copper pillar 70 has a bottom portion 75 that includes interdiffused zinc (the top portion is pure copper). Therefore, the bottom portion 75 of the copper pillar 70 may contain brass (as explained more fully below).
  • FIG. 1 it is within the scope of the invention to create a layer of TiW and a copper pillar 70 / 75 that has a perimeter 100 that extends beyond the location of vias 30 .
  • This extended perimeter of elements 60 , 70 / 75 may increase the likelihood that the entire surface of each via 30 is in electrical contact with elements 60 , 70 / 75 (which may improve the reliability of the packaged semiconductor device 10 ).
  • FIG. 2 shows an example method 200 for fabricating the packaged semiconductor device 10 of FIG. 1 .
  • FIGS. 3 - 11 illustrate selected steps of method 200 .
  • the example method 200 is exemplary but not restrictive of alternative ways of implementing the principles of the invention. Moreover, features and procedures whose implementations are well known to those skilled in the art are omitted for brevity. For example, the implementation of common fabrication steps lies within the ability of those skilled in the art and accordingly any detailed discussion thereof may be omitted.
  • Step 210 is the provision of a fully processed semiconductor wafer 110 , as shown in FIG. 3 .
  • the semiconductor wafer 110 contains numerous completed semiconductor dies 20 .
  • the semiconductor dies 20 may contain any combination of active and passive electrical circuitry, such as CMOS, BiCMOS and bipolar junction transistors - as well as capacitors, optoelectronic devices, inductors, resistors, and diodes.
  • the semiconductor dies 20 include vias 30 that are connected to the electrical circuitry (not shown) within the semiconductor die 20 .
  • the vias include copper; however, the vias may contain other suitable materials such as tungsten.
  • the semiconductor dies 20 are spaced apart from each other on the semiconductor wafer 110 by zones 120 of unprocessed semiconductor material. These zones 120 of unprocessed semiconductor material are mostly destroyed by a rotating saw blade during the singulation process (as explained below). Therefore, the zones 120 of unprocessed semiconductor material are often called “saw streets” because they form a grid between all of the semiconductor dies 20 on the semiconductor wafer 110 that is largely destroyed by the saw during the dicing process.
  • the next step in the fabrication process is the formation of a layer of TiW 60 over the semiconductor wafer 110 .
  • a layer of TIW is coated over the semiconductor wafer in step 220 .
  • the layer of TiW 60 is formed by sputtering; however, any acceptable method of deposition may be used.
  • the thickness of the layer of TiW 60 may range from 100-400 nm. It is within the scope of the invention to use other acceptable materials that are a diffusion barrier and adhesion promoter.
  • a layer of Ti or TaN may be used instead of TiW 60 .
  • step 230 is the formation of a layer of Zn 130 over the layer of TiW 60 .
  • Step 230 is shown in FIG. 5 .
  • the thickness of the layer of Zn 130 may range from 100 nm-20 ⁇ m.
  • Zn 130 is sputtered over the layer of TiW 60 in step 230 ; however, another acceptable coating method may be used (such as electroplating).
  • a patterned photoresist 140 is formed in step 240 .
  • the patterned photoresist 140 has openings 150 over the vias 30 . These openings 150 will be used to create the copper pillars 70 in the next step of the fabrication process.
  • the openings 150 are large enough to create copper pillars 70 with a perimeter 100 that exceeds the width of vias 30 .
  • copper pillars 70 having a perimeter 100 that exceeds the width of vias 30 may improve the reliability of the packaged semiconductor device 10 .
  • Step 250 is the formation of copper pillars 70 .
  • the copper pillars 70 are formed over vias 30 . More specifically, the copper pillars 70 are formed on the exposed layers of Zn 130 by a standard electroplating process and then the patterned photoresist 140 is removed (using solvent or a plasma etch).
  • Method 200 continues with an anneal of the semiconductor wafer 110 .
  • the annealing process will cause the layer of Zn 130 to interdiffuse with the adjoining copper pillar 70 .
  • the diffusion process is likely to result in the formation of brass (Cu-20 wt % Zn) in the majority of the bottom portion 75 of the copper pillar 70 , as illustrated in FIG. 8 . (The top portion of copper pillar 70 will remain pure cupper.)
  • step 270 the remaining layer of zinc 130 is removed, as shown in FIG. 9 .
  • the remaining layer of Zn 130 may be removed by any acceptable process such as a wet etch using diluted hydrochloric acid.
  • the layer 60 of TiW located outside the perimeter 100 of the copper pillars 70 is also removed by any acceptable process such as a wet etch using hydrogen peroxide. It is to be noted that there will be minimal undercutting below the outer corners of portion 75 of the copper pillar 70 during the wet etch of the layer of Zn 130 . However, there may be a slight amount of undercutting (less than 3%) under the copper pillar 70 / 75 during the wet etch of the layer of TiW 60 .
  • the semiconductor wafer 110 is singulated in step 290 , as shown in FIG. 11 .
  • a rotating saw blade 160 is typically used to cut through the saw street zones 120 during the dicing process.
  • This singulation process creates individual semiconductor dies 20 that can be further fabricated into a packaged semiconductor die 10 using conventional manufacturing steps.
  • the individual semiconductor dies 20 may be connected to the PCB 40 using any acceptable conventional manufacturing process.
  • solder resist 80 such as SnAg
  • a robotic pick-and-place machine may be used to attach the copper pillars 70 to the pads 35 of the PCB 40 .
  • the semiconductor die 20 and portions of the PCB 40 are encapsulated with molding compound to create the packaged semiconductor device 10 shown in FIG. 1 .
  • the formation of brass at the interface 75 between the copper pillar 70 and the layer of TiW 60 may provide desired corrosion resistance for the copper pillar 70 .
  • the presence of brass at the interface 75 between the copper pillar 70 and the layer of TiW 60 may provide electromigration improvements; thereby increasing the electrical reliability of the packaged semiconductor device 10 .
  • FIG. 12 is a cross-sectional view of a packaged semiconductor device 10 in accordance with an alternative embodiment.
  • the semiconductor die 20 has copper vias 30 that are connected to electrical circuitry (not shown) within the semiconductor die 20 .
  • the copper vias 30 may be formed with a conventional process, such as etching via holes into the surface of the semiconductor die 20 , coating the surface of the semiconductor die 20 with TiW, coating the TiW surface with copper, using an electroplating process to fill the via holes with copper, and then polishing the TiW and Cu off the surface of the semiconductor die 20 .
  • the vias may be formed by depositing W instead of Cu into the via holes (over the coating of TiW).
  • the semiconductor die 20 of FIG. 12 is electrically and physically attached to a multi-layered solder resist PCB 40 .
  • the PCB 40 contains multiple layers of electrical traces that properly direct electrical signals within the PCB.
  • the PCB 40 contains leads 50 that electrically connect the circuitry of the PCB 40 and the semiconductor die 20 to other electrical devices (not shown) within an electrical system.
  • the semiconductor die 20 is attached to the pads 35 of the PCB 40 through a layer of TiW 60 , a copper pillar 70 , and solder resist 80 .
  • Molding compound 90 encapsulates the semiconductor die 20 and portions of the PCB 40 .
  • the copper pillar 70 in the alternative embodiment is pure copper throughout (therefore, there is no bottom portion 75 that includes interdiffused zinc).
  • the use of both positive tone photoresist and negative tone photoresist during the fabrication process 300 may prevent the formation of a layer of Zn at the interface between the layer of TiW 60 and the copper pillar 70 .
  • FIG. 12 it is within the scope of the invention to create a layer of TiW and a copper pillar 70 that has a perimeter 100 that extends beyond the location of vias 30 .
  • This extended perimeter of elements 60 , 70 may increase the likelihood that the entire surface of each via 30 is in electrical contact with elements 60 , 70 (which may improve the reliability of the packaged semiconductor device 10 ).
  • FIG. 13 shows an alternative method 300 for fabricating the packaged semiconductor device 10 of FIG. 12 .
  • FIGS. 14 - 24 illustrate selected steps of method 300 .
  • the example method 300 is exemplary but not restrictive of alternative ways of implementing the principles of the invention.
  • Step 310 is the provision of a fully processed semiconductor wafer 110 , as shown in FIG. 14 .
  • the semiconductor wafer 110 contains numerous completed semiconductor dies 20 .
  • the semiconductor dies may contain any combination of active and passive electrical circuitry (not shown), such as CMOS, BiCMOS and bipolar junction transistors - as well as capacitors, optoelectronic devices, inductors, resistors, and diodes.
  • the semiconductor dies 20 include vias 30 that are connected to the electrical circuitry within the semiconductor die 20 .
  • the vias include copper; however, the vias may contain other suitable materials such as tungsten.
  • the semiconductor dies 20 are spaced apart from each other on the semiconductor wafer 110 by zones 120 of unprocessed semiconductor material. These zones 120 of unprocessed semiconductor material are mostly destroyed by a rotating saw blade during the singulation process.
  • the next step in the fabrication process is the formation of a layer of TiW 60 over the semiconductor wafer 110 .
  • a layer of TIW is coated over the semiconductor wafer in step 320 .
  • the layer of TiW 60 is formed by sputtering; however, any acceptable method of deposition may be used.
  • the thickness of the layer of TiW 60 may range from 100-400 nm. It is within the scope of the invention to use other acceptable materials that are a diffusion barrier and adhesion promoter.
  • a layer of Ti or TaN may be used instead of TiW 60 .
  • step 330 is the formation of a first patterned photoresist 170 over the vias 30 .
  • negative tone photoresist 170 is formed over the vias 30 of the semiconductor wafer 110 .
  • negative tone photoresist 170 becomes crosslinked (polymerized) when exposed to light. Therefore, negative tone photoresist 170 more difficult to dissolve in photoresist developer.
  • step 335 the semiconductor wafer 110 is coated with a layer of Zn 130 .
  • the thickness of the layer of Zn 130 may range from 100 nm-20 ⁇ m.
  • the layer of Zn 130 is sputtered over the layer of TiW 60 in step 335 ; however, another acceptable coating method may be used (such as electroplating).
  • step 340 is the removal of the first patterned photoresist 170 (using solvent or a plasma etch).
  • the next step 350 is the formation of a second patterned photoresist 180 over the layer of Zn 130 .
  • the second patterned photoresist 180 is positive tone photoresist.
  • the portion of positive tone photoresist that is exposed to light becomes soluble to the photoresist developer.
  • the unexposed portion of the positive tone photoresist remains insoluble to the photoresist developer. Therefore, a single mask (reticle) can be used for steps 330 and 350 , which may reduce the cost of manufacturing the packaged semiconductor device 10 .
  • Step 355 is the formation of copper pillars 70 .
  • the copper pillars 70 are formed over vias 30 . More specifically, the copper pillars 70 are formed on the exposed layers of TiW 60 by a standard electroplating process and then the patterned photoresist 140 is removed (using solvent or a plasma etch) in step 360 , as shown in FIG. 21 .
  • the next step 365 in the alternative method 300 is the removal of the layer of Zn 130 , as shown in FIG. 22 .
  • the layer of Zn 130 may be removed by any acceptable process such as a wet etch using diluted hydrochloric acid. Because the layer of Zn 130 is in contact with the copper pillar 70 , the layer of Zn 130 will act as a cathodic protection component. As a result, the copper pillar 70 will not dissolve before the complete dissolution of the layer of Zn 130 . Therefore, the layer of Zn 130 is a sacrificial layer that may prevent any corrosion of the copper pillar 70 . Moreover, the use of the layer of Zn 130 instead of the copper seed layer that is currently used during the fabrication of copper pillars 70 results in minimal undercutting below the outer corners of the copper pillar 70 during the wet etch of the layer of Zn 130 .
  • the layer 60 of TiW located outside the perimeter 100 of the copper pillars 70 is removed in step 370 by any acceptable process such as a wet etch using hydrogen peroxide. It is to be noted that there may be a slight amount of undercutting (less than 3%) under the outer corners of the copper pillar 70 during the wet etch of the layer of TiW 60 .
  • the semiconductor wafer 110 is singulated in step 380 , as shown in FIG. 24 .
  • a rotating saw blade 160 is typically used to cut through the saw street zones 120 during the dicing process.
  • This singulation process creates individual semiconductor dies 20 that can be further fabricated into a packaged semiconductor die 10 using conventional manufacturing steps.
  • the individual semiconductor dies 20 may be connected to the PCB 40 using any acceptable conventional manufacturing process.
  • solder resist 80 such as SnAg
  • a robotic pick-and-place machine may be used to attach the copper pillars 70 to the pads 35 of the PCB 40 .
  • the semiconductor die 20 and portions of the PCB 40 are encapsulated with molding compound to create the packaged semiconductor device 10 , as shown in FIG. 12 .
  • the semiconductor wafer 110 may be desirable to clean the semiconductor wafer 110 after the copper leads 30 have been exposed in while patterning the photoresist layer 140 .
  • the wafer clean may be used to remove any copper oxide that may have formed on the copper leads 30 before the sputtering the copper pillars 70 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A device includes a semiconductor die including a via, a layer of titanium tungsten (TiW) in contact with the via, and a copper pillar including a top portion and a bottom portion. The bottom portion is in contact with the layer of TiW. The copper pillar includes interdiffused zinc within the bottom portion.

Description

    CLAIM TO PRIORITY OF NONPROVISIONAL APPLICATION
  • This application is a division of patent application Ser. No. 15/909,679, filed Mar. 1, 2018 (now U.S. Pat. No. 11,443,996), which claims the benefit under 35 U.S.C. 119(e) of U.S. Provisional Application No. 62/568,484, filed Oct. 5, 2017, Attorney Docket No. TI-78926PS, the content of which is incorporated by reference.
    • BACKGROUND OF THE INVENTION
  • This invention relates to the fabrication of a pillar over a via of a semiconductor die.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a packaged semiconductor device in accordance with the present invention.
  • FIG. 2 is a method for fabricating the packaged semiconductor device of FIG. 1 .
  • FIGS. 3-11 are cross-sectional diagrams of selected steps of the method of FIG. 2 .
  • FIG. 12 is a cross-sectional view of an alternative packaged semiconductor device in accordance with the present invention.
  • FIG. 13 is a method for fabricating the alternative packaged semiconductor device of FIG. 12 .
  • FIGS. 14-24 are cross-sectional diagrams of selected steps of the alternative method of FIG. 13 .
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • Referring to the drawings, FIG. 1 is a cross-sectional view of a packaged semiconductor device 10 in accordance with an example embodiment. In this example, the packaged semiconductor device 10 contains a semiconductor die 20 that has copper vias 30 connected to electrical circuitry (not shown) within the semiconductor die 20. The copper vias 30 may be formed with a conventional process, such as etching via holes into the surface of the semiconductor die 20, coating the surface of the semiconductor die 20 with titanium tungsten (TiW), coating the TiW surface with copper, using an electroplating process to fill the via holes with copper, and then polishing the TiW and Cu off the surface of the semiconductor die 20. Alternatively, the vias may be formed by depositing tungsten (W) instead of Cu into the via holes (over the coating of TiW).
  • The semiconductor die 20 is electrically and physically attached to a multi-layered solder resist printed circuit board (PCB) 40. The PCB 40 contains multiple layers of electrical traces that properly direct electrical signals within the PCB. In addition, the PCB 40 contains leads 50 that electrically connect the PCB 40 and the semiconductor die 20 to other electrical devices (not shown) within an electrical system. The semiconductor die 20 is attached to pads 35 of the PCB through a layer of TiW 60, a copper pillar 70, and solder resist 80. Molding compound 90 encapsulates the semiconductor die 20 and portions of the PCB 40. Note that the surface of leads 50 is often left unencapsulated to facilitate their electrical interconnection to other electrical devices.
  • In accordance with the example embodiment, the copper pillar 70 has a bottom portion 75 that includes interdiffused zinc (the top portion is pure copper). Therefore, the bottom portion 75 of the copper pillar 70 may contain brass (as explained more fully below).
  • As shown in FIG. 1 , it is within the scope of the invention to create a layer of TiW and a copper pillar 70/75 that has a perimeter 100 that extends beyond the location of vias 30. This extended perimeter of elements 60, 70/75 may increase the likelihood that the entire surface of each via 30 is in electrical contact with elements 60, 70/75 (which may improve the reliability of the packaged semiconductor device 10).
  • FIG. 2 shows an example method 200 for fabricating the packaged semiconductor device 10 of FIG. 1 . FIGS. 3-11 illustrate selected steps of method 200. The example method 200 is exemplary but not restrictive of alternative ways of implementing the principles of the invention. Moreover, features and procedures whose implementations are well known to those skilled in the art are omitted for brevity. For example, the implementation of common fabrication steps lies within the ability of those skilled in the art and accordingly any detailed discussion thereof may be omitted.
  • Step 210 is the provision of a fully processed semiconductor wafer 110, as shown in FIG. 3 . The semiconductor wafer 110 contains numerous completed semiconductor dies 20. The semiconductor dies 20 may contain any combination of active and passive electrical circuitry, such as CMOS, BiCMOS and bipolar junction transistors - as well as capacitors, optoelectronic devices, inductors, resistors, and diodes. In addition, the semiconductor dies 20 include vias 30 that are connected to the electrical circuitry (not shown) within the semiconductor die 20. In method 200 the vias include copper; however, the vias may contain other suitable materials such as tungsten.
  • The semiconductor dies 20 are spaced apart from each other on the semiconductor wafer 110 by zones 120 of unprocessed semiconductor material. These zones 120 of unprocessed semiconductor material are mostly destroyed by a rotating saw blade during the singulation process (as explained below). Therefore, the zones 120 of unprocessed semiconductor material are often called “saw streets” because they form a grid between all of the semiconductor dies 20 on the semiconductor wafer 110 that is largely destroyed by the saw during the dicing process.
  • The next step in the fabrication process is the formation of a layer of TiW 60 over the semiconductor wafer 110. As shown in FIG. 4 , a layer of TIW is coated over the semiconductor wafer in step 220. In the example method 200, the layer of TiW 60 is formed by sputtering; however, any acceptable method of deposition may be used. The thickness of the layer of TiW 60 may range from 100-400 nm. It is within the scope of the invention to use other acceptable materials that are a diffusion barrier and adhesion promoter. For example, a layer of Ti or TaN may be used instead of TiW 60.
  • In accordance with the example method 200, step 230 is the formation of a layer of Zn 130 over the layer of TiW 60. Step 230 is shown in FIG. 5 . The thickness of the layer of Zn 130 may range from 100 nm-20 μm. Zn 130 is sputtered over the layer of TiW 60 in step 230; however, another acceptable coating method may be used (such as electroplating).
  • Next, a patterned photoresist 140 is formed in step 240. As shown in FIG. 6 , the patterned photoresist 140 has openings 150 over the vias 30. These openings 150 will be used to create the copper pillars 70 in the next step of the fabrication process. In the example method 200, the openings 150 are large enough to create copper pillars 70 with a perimeter 100 that exceeds the width of vias 30. As stated previously, copper pillars 70 having a perimeter 100 that exceeds the width of vias 30 may improve the reliability of the packaged semiconductor device 10.
  • Step 250 is the formation of copper pillars 70. As shown in FIG. 7 , the copper pillars 70 are formed over vias 30. More specifically, the copper pillars 70 are formed on the exposed layers of Zn 130 by a standard electroplating process and then the patterned photoresist 140 is removed (using solvent or a plasma etch).
  • Method 200 continues with an anneal of the semiconductor wafer 110. In step 260, the annealing process will cause the layer of Zn 130 to interdiffuse with the adjoining copper pillar 70. The diffusion process is likely to result in the formation of brass (Cu-20 wt % Zn) in the majority of the bottom portion 75 of the copper pillar 70, as illustrated in FIG. 8 . (The top portion of copper pillar 70 will remain pure cupper.)
  • In step 270 the remaining layer of zinc 130 is removed, as shown in FIG. 9 . The remaining layer of Zn 130 may be removed by any acceptable process such as a wet etch using diluted hydrochloric acid. As shown in FIG. 10 , the layer 60 of TiW located outside the perimeter 100 of the copper pillars 70 is also removed by any acceptable process such as a wet etch using hydrogen peroxide. It is to be noted that there will be minimal undercutting below the outer corners of portion 75 of the copper pillar 70 during the wet etch of the layer of Zn 130. However, there may be a slight amount of undercutting (less than 3%) under the copper pillar 70/75 during the wet etch of the layer of TiW 60.
  • The semiconductor wafer 110 is singulated in step 290, as shown in FIG. 11 . A rotating saw blade 160 is typically used to cut through the saw street zones 120 during the dicing process. This singulation process creates individual semiconductor dies 20 that can be further fabricated into a packaged semiconductor die 10 using conventional manufacturing steps. For example, the individual semiconductor dies 20 may be connected to the PCB 40 using any acceptable conventional manufacturing process. In the example step 295, solder resist 80 (such as SnAg) is placed on the exposed top portion of the copper pillar 70 and then a robotic pick-and-place machine may be used to attach the copper pillars 70 to the pads 35 of the PCB 40. Later, the semiconductor die 20 and portions of the PCB 40 are encapsulated with molding compound to create the packaged semiconductor device 10 shown in FIG. 1 .
  • The formation of brass at the interface 75 between the copper pillar 70 and the layer of TiW 60 (that is located above the vias 30) may provide desired corrosion resistance for the copper pillar 70. In addition, the presence of brass at the interface 75 between the copper pillar 70 and the layer of TiW 60 may provide electromigration improvements; thereby increasing the electrical reliability of the packaged semiconductor device 10.
  • Referring again to the drawings, FIG. 12 is a cross-sectional view of a packaged semiconductor device 10 in accordance with an alternative embodiment. As noted above, like reference numerals are used throughout the figures to designate similar or equivalent elements. As with the embodiment shown in FIG. 1 , the semiconductor die 20 has copper vias 30 that are connected to electrical circuitry (not shown) within the semiconductor die 20. The copper vias 30 may be formed with a conventional process, such as etching via holes into the surface of the semiconductor die 20, coating the surface of the semiconductor die 20 with TiW, coating the TiW surface with copper, using an electroplating process to fill the via holes with copper, and then polishing the TiW and Cu off the surface of the semiconductor die 20. Alternatively, the vias may be formed by depositing W instead of Cu into the via holes (over the coating of TiW).
  • Also similar to the embodiment shown in FIG. 1 , the semiconductor die 20 of FIG. 12 is electrically and physically attached to a multi-layered solder resist PCB 40. The PCB 40 contains multiple layers of electrical traces that properly direct electrical signals within the PCB. In addition, the PCB 40 contains leads 50 that electrically connect the circuitry of the PCB 40 and the semiconductor die 20 to other electrical devices (not shown) within an electrical system.
  • In accordance with the alternative embodiment shown in FIG. 12 , the semiconductor die 20 is attached to the pads 35 of the PCB 40 through a layer of TiW 60, a copper pillar 70, and solder resist 80. Molding compound 90 encapsulates the semiconductor die 20 and portions of the PCB 40.
  • The copper pillar 70 in the alternative embodiment is pure copper throughout (therefore, there is no bottom portion 75 that includes interdiffused zinc). The use of both positive tone photoresist and negative tone photoresist during the fabrication process 300 (described more fully below) may prevent the formation of a layer of Zn at the interface between the layer of TiW 60 and the copper pillar 70.
  • As shown in FIG. 12 , it is within the scope of the invention to create a layer of TiW and a copper pillar 70 that has a perimeter 100 that extends beyond the location of vias 30. This extended perimeter of elements 60, 70 may increase the likelihood that the entire surface of each via 30 is in electrical contact with elements 60, 70 (which may improve the reliability of the packaged semiconductor device 10).
  • FIG. 13 shows an alternative method 300 for fabricating the packaged semiconductor device 10 of FIG. 12 . FIGS. 14-24 illustrate selected steps of method 300. The example method 300 is exemplary but not restrictive of alternative ways of implementing the principles of the invention.
  • Step 310 is the provision of a fully processed semiconductor wafer 110, as shown in FIG. 14 . The semiconductor wafer 110 contains numerous completed semiconductor dies 20. The semiconductor dies may contain any combination of active and passive electrical circuitry (not shown), such as CMOS, BiCMOS and bipolar junction transistors - as well as capacitors, optoelectronic devices, inductors, resistors, and diodes. In addition, the semiconductor dies 20 include vias 30 that are connected to the electrical circuitry within the semiconductor die 20. In method 300 the vias include copper; however, the vias may contain other suitable materials such as tungsten.
  • The semiconductor dies 20 are spaced apart from each other on the semiconductor wafer 110 by zones 120 of unprocessed semiconductor material. These zones 120 of unprocessed semiconductor material are mostly destroyed by a rotating saw blade during the singulation process.
  • The next step in the fabrication process is the formation of a layer of TiW 60 over the semiconductor wafer 110. As shown in FIG. 15 , a layer of TIW is coated over the semiconductor wafer in step 320. In the example method 300, the layer of TiW 60 is formed by sputtering; however, any acceptable method of deposition may be used. The thickness of the layer of TiW 60 may range from 100-400 nm. It is within the scope of the invention to use other acceptable materials that are a diffusion barrier and adhesion promoter. For example, a layer of Ti or TaN may be used instead of TiW 60.
  • In accordance with the alternative method 300, step 330 is the formation of a first patterned photoresist 170 over the vias 30. As shown in FIG. 16 , negative tone photoresist 170 is formed over the vias 30 of the semiconductor wafer 110. As known in the art, negative tone photoresist 170 becomes crosslinked (polymerized) when exposed to light. Therefore, negative tone photoresist 170 more difficult to dissolve in photoresist developer.
  • In step 335, shown in FIG. 17 , the semiconductor wafer 110 is coated with a layer of Zn 130. The thickness of the layer of Zn 130 may range from 100 nm-20 μm. The layer of Zn 130 is sputtered over the layer of TiW 60 in step 335; however, another acceptable coating method may be used (such as electroplating). As shown in FIG. 18 , step 340 is the removal of the first patterned photoresist 170 (using solvent or a plasma etch).
  • The next step 350, shown in FIG. 19 , is the formation of a second patterned photoresist 180 over the layer of Zn 130. In accordance with the alternative method 300, the second patterned photoresist 180 is positive tone photoresist. As known in the art, the portion of positive tone photoresist that is exposed to light becomes soluble to the photoresist developer. (The unexposed portion of the positive tone photoresist remains insoluble to the photoresist developer). Therefore, a single mask (reticle) can be used for steps 330 and 350, which may reduce the cost of manufacturing the packaged semiconductor device 10.
  • Step 355 is the formation of copper pillars 70. As shown in FIG. 20 , the copper pillars 70 are formed over vias 30. More specifically, the copper pillars 70 are formed on the exposed layers of TiW 60 by a standard electroplating process and then the patterned photoresist 140 is removed (using solvent or a plasma etch) in step 360, as shown in FIG. 21 .
  • The next step 365 in the alternative method 300 is the removal of the layer of Zn 130, as shown in FIG. 22 . The layer of Zn 130 may be removed by any acceptable process such as a wet etch using diluted hydrochloric acid. Because the layer of Zn 130 is in contact with the copper pillar 70, the layer of Zn 130 will act as a cathodic protection component. As a result, the copper pillar 70 will not dissolve before the complete dissolution of the layer of Zn 130. Therefore, the layer of Zn 130 is a sacrificial layer that may prevent any corrosion of the copper pillar 70. Moreover, the use of the layer of Zn 130 instead of the copper seed layer that is currently used during the fabrication of copper pillars 70 results in minimal undercutting below the outer corners of the copper pillar 70 during the wet etch of the layer of Zn 130.
  • As shown in FIG. 23 , the layer 60 of TiW located outside the perimeter 100 of the copper pillars 70 is removed in step 370 by any acceptable process such as a wet etch using hydrogen peroxide. It is to be noted that there may be a slight amount of undercutting (less than 3%) under the outer corners of the copper pillar 70 during the wet etch of the layer of TiW 60.
  • The semiconductor wafer 110 is singulated in step 380, as shown in FIG. 24 . A rotating saw blade 160 is typically used to cut through the saw street zones 120 during the dicing process. This singulation process creates individual semiconductor dies 20 that can be further fabricated into a packaged semiconductor die 10 using conventional manufacturing steps. The individual semiconductor dies 20 may be connected to the PCB 40 using any acceptable conventional manufacturing process. In the example step 390, solder resist 80 (such as SnAg) is placed on the exposed top portion of the copper pillar 70 and then a robotic pick-and-place machine may be used to attach the copper pillars 70 to the pads 35 of the PCB 40. Later, the semiconductor die 20 and portions of the PCB 40 are encapsulated with molding compound to create the packaged semiconductor device 10, as shown in FIG. 12 .
  • Various additional modifications to the invention as described above are within the scope of the claimed invention. As an example, it may be desirable to clean the semiconductor wafer 110 after the copper leads 30 have been exposed in while patterning the photoresist layer 140. The wafer clean may be used to remove any copper oxide that may have formed on the copper leads 30 before the sputtering the copper pillars 70. Similarly, it may be desirable to clean the semiconductor wafer 110 following the etching steps 270, 280 to remove any unwanted debris created by those etching processes.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims (18)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor die including a via;
a layer of titanium tungsten (TiW) in contact with the via; and
a copper pillar including a top portion and a bottom portion, the bottom portion in contact with the layer of TiW, the copper pillar including zinc within the bottom portion.
2. The semiconductor device of claim 1, wherein the layer of TiW contacts portions of the semiconductor die.
3. The semiconductor device of claim 1, wherein the via includes copper.
4. The semiconductor device of claim 1, wherein a lateral width of the layer of TiW is more than a lateral width of the via.
5. The semiconductor device of claim 1 further including mold compound in contact with the semiconductor die, the layer of TiW, and the copper pillar.
6. The semiconductor device of claim 1, wherein the via includes copper.
7. A packaged semiconductor device, comprising:
a semiconductor die including a via;
a layer of titanium tungsten (TiW) coupled to the via;
a copper pillar including a top portion and a bottom portion, the bottom portion in contact with the layer of TiW;
a substrate coupled to the copper pillar; and
molding compound covering portions of the semiconductor die, the copper pillar, the layer of TiW, and the substrate.
8. The packaged semiconductor device of claim 7, wherein the layer of TiW contacts portions of the semiconductor die.
9. The packaged semiconductor device of claim 7, wherein the via includes copper.
10. The packaged semiconductor device of claim 7, wherein the copper pillar includes interdiffused zinc within the bottom portion.
11. A semiconductor device, comprising:
a semiconductor die including a via;
a layer of titanium tungsten (TiW) in contact with the via; and
a copper pillar including a top portion and a bottom portion, the bottom portion in contact with the layer of TiW.
12. The semiconductor device of claim 11, wherein the layer of TiW contacts portions of the semiconductor die.
13. The semiconductor device of claim 11, wherein the via includes copper.
14. The semiconductor device of claim 11, wherein a lateral width of the layer of TiW is more than a lateral width of the via.
15. The semiconductor device of claim 11 further including mold compound in contact with the semiconductor die, the layer of TiW, and the copper pillar.
16. The semiconductor device of claim 11, wherein the via includes copper.
17. The packaged semiconductor device of claim 11, wherein the copper pillar includes zinc within the bottom portion.
18. The packaged semiconductor device of claim 17, wherein the zinc is interdiffused zinc.
US17/931,828 2017-10-05 2022-09-13 Zinc Layer For A Semiconductor Die Pillar Pending US20230005807A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/931,828 US20230005807A1 (en) 2017-10-05 2022-09-13 Zinc Layer For A Semiconductor Die Pillar

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762568484P 2017-10-05 2017-10-05
US15/909,679 US11443996B2 (en) 2017-10-05 2018-03-01 Zinc layer for a semiconductor die pillar
US17/931,828 US20230005807A1 (en) 2017-10-05 2022-09-13 Zinc Layer For A Semiconductor Die Pillar

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/909,679 Division US11443996B2 (en) 2017-10-05 2018-03-01 Zinc layer for a semiconductor die pillar

Publications (1)

Publication Number Publication Date
US20230005807A1 true US20230005807A1 (en) 2023-01-05

Family

ID=65994030

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/909,679 Active 2039-03-07 US11443996B2 (en) 2017-10-05 2018-03-01 Zinc layer for a semiconductor die pillar
US17/931,828 Pending US20230005807A1 (en) 2017-10-05 2022-09-13 Zinc Layer For A Semiconductor Die Pillar

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US15/909,679 Active 2039-03-07 US11443996B2 (en) 2017-10-05 2018-03-01 Zinc layer for a semiconductor die pillar

Country Status (1)

Country Link
US (2) US11443996B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032340A1 (en) * 2010-08-06 2012-02-09 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
US20140264843A1 (en) * 2013-03-14 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Circuit Structure Having Dies with Connectors
US20160379947A1 (en) * 2015-06-29 2016-12-29 Infineon Technologies Ag Semiconductor Device with Metal Structure Electrically Connected to a Conductive Structure
US20180130759A1 (en) * 2016-11-10 2018-05-10 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor manufacturing process

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US20090197114A1 (en) * 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US10410988B2 (en) * 2016-08-09 2019-09-10 Semtech Corporation Single-shot encapsulation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032340A1 (en) * 2010-08-06 2012-02-09 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
US20140264843A1 (en) * 2013-03-14 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Circuit Structure Having Dies with Connectors
US20160379947A1 (en) * 2015-06-29 2016-12-29 Infineon Technologies Ag Semiconductor Device with Metal Structure Electrically Connected to a Conductive Structure
US20180130759A1 (en) * 2016-11-10 2018-05-10 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor manufacturing process

Also Published As

Publication number Publication date
US20190109062A1 (en) 2019-04-11
US11443996B2 (en) 2022-09-13

Similar Documents

Publication Publication Date Title
TWI659512B (en) Semiconductor device and method of encapsulating semiconductor die
TWI262537B (en) Semiconductor device with crack prevention ring and method of manufacture thereof
TWI334170B (en) Methods of die sawing and structures formed thereby
US9293371B2 (en) Method for processing a semiconductor workpiece with metallization
US10153266B2 (en) Semiconductor device
US8163629B2 (en) Metallization for chip scale packages in wafer level packaging
US20080303154A1 (en) Through-silicon via interconnection formed with a cap layer
US10262959B2 (en) Semiconductor devices and methods of forming thereof
US20080070379A1 (en) Method of fabricating semiconductor device
US8129835B2 (en) Package substrate having semiconductor component embedded therein and fabrication method thereof
US8741764B2 (en) Semiconductor device and method of forming conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate
US20140252571A1 (en) Wafer-level package mitigated undercut
US20120211884A1 (en) Wafer chip scale package connection scheme
KR20180059747A (en) Semiconductor device and method for manufacturing same
US20190259717A1 (en) Nickel Alloy for Semiconductor Packaging
US20150194398A1 (en) Conductive Lines and Pads and Method of Manufacturing Thereof
CN108122855B (en) Semiconductor structure and semiconductor manufacturing method
US20230005807A1 (en) Zinc Layer For A Semiconductor Die Pillar
CN110060958B (en) Semiconductor structure and semiconductor process
WO2018142976A1 (en) Csp-type semiconductor device and method for manufacturing same
JP2004296812A (en) Semiconductor device and method of manufacturing the same
KR100896841B1 (en) Method for forming bond pad on fabricating a semiconductor device
US9093505B2 (en) Integrated circuit chip and fabrication method
JP2006173153A (en) Manufacturing method of semiconductor device
JP2010245571A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED