CN108962764A - 半导体结构的形成方法、半导体芯片、封装方法及结构 - Google Patents

半导体结构的形成方法、半导体芯片、封装方法及结构 Download PDF

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Publication number
CN108962764A
CN108962764A CN201710363969.9A CN201710363969A CN108962764A CN 108962764 A CN108962764 A CN 108962764A CN 201710363969 A CN201710363969 A CN 201710363969A CN 108962764 A CN108962764 A CN 108962764A
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Prior art keywords
opening
passivation layer
semiconductor chip
layer
substrate
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CN201710363969.9A
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CN108962764B (zh
Inventor
陆丽辉
费春潮
江博渊
王亚平
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201710363969.9A priority Critical patent/CN108962764B/zh
Priority to US15/985,272 priority patent/US10522479B2/en
Publication of CN108962764A publication Critical patent/CN108962764A/zh
Priority to US16/697,552 priority patent/US11335648B2/en
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Abstract

一种半导体结构的形成方法、一种半导体芯片、一种封装方法及一种封装结构，通过在第二钝化层中形成第三开口，以提高所述第二钝化层的粗糙度。因此在填充所述半导体芯片与布线基板之间的空隙时，增强了填充介质与所述半导体芯片的粘合度，从而使形成的封装结构更加稳定，性能更加优良。

Description

半导体结构的形成方法、半导体芯片、封装方法及结构
技术领域
本发明涉及集成电路领域，尤其涉及一种半导体结构的形成方法、一种半导体芯片、一种封装方法及一种封装结构。
背景技术
集成电路的封装工艺是集成电路芯片转化为实用电子产品过程中必不可少的一步，起到电子模块互连、机械支撑、保护等作用，可以显著地提高芯片的可靠性。
针对高性能要求的集成电路封装体系，倒装封装开始成为高密度集成电路封装的主流方法；同时,三维封装的出现也为更高密度的电子封装提供可能。在集成电路封装体系中，由于芯片、基板、焊球、下填料等材料的热膨胀系数不同，在封装工艺中很容易引入应力，对芯片的性能及可靠性产生不良的影响。因此，提高封装结构的性能成为亟待解决的问题。
发明内容
本发明解决的问题是提供一种半导体结构的形成方法、一种半导体芯片、一种封装方法及一种封装结构，以改善所形成的半导体芯片及封装结构的性能。
为解决上述问题，本发明实施方式提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有连接层；在所述基底上形成第一钝化层，所述第一钝化层具有露出所述连接层的第一开口；形成第二钝化层，所述第二钝化层填充所述第一开口且覆盖所述第一钝化层；在所述第二钝化层中形成第二开口和第三开口；所述第二开口位于第一开口内且露出所述连接层，所述第三开口位于第一开口外；在所述第二开口中形成导电凸起。
可选的，所述第三开口的开口尺寸大于或等于20μm。
可选的，所述第三开口沿平行于衬底方向的截面呈六边形。
可选的，所述基底布有多条切割道，切割道相交位置处构成拐角区域，形成第三开口的步骤包括：在所述拐角区域形成第三开口。
可选的，在所述切割道交叉的拐角区域形成一个或多个第三开口。
可选的，所述第三开口底部位于所述第一钝化层内部；或者，所述第三开口露出所述第一钝化层表面。
可选的，所述第二钝化层的材料是氧化硅、氧化铝、氮化硅、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、聚酰亚胺、聚硅氧烷或硅酮橡胶。
可选的，在所述第二钝化层中形成第二开口以及第三开口的步骤包括：形成填充所述第一开口且覆盖所述第一钝化层的第二钝化层；在所述第二钝化层上形成第一图形层；以所述第一图形层为掩膜刻蚀所述第二钝化层，形成第二开口以及第三开口。
可选的，在所述第二开口中形成导电凸起的步骤包括：在所述第二开口侧壁及底部形成金属膜，所述金属膜还覆盖所述第二钝化层且覆盖所述第三开口的侧壁及底部；在所述金属膜上形成第二图形层，所述第二图形层在所述第二开口区域形成有第四开口，所述第四开口露出所述金属膜；在所述第四开口内填充金属介质形成金属柱；在所述金属柱上形成金属帽；去除所述第二图形层及所述第二图形层下的所述金属膜，露出所述第二钝化层及所述第三开口；位于所述第四开口内的所述金属膜为导电凸起下金属膜；所述金属帽、所述金属柱及所述导电凸起下金属膜共同构成导电凸起。
本发明还提供一种半导体芯片，包括：基底，所述基底上形成有连接层；位于所述连接层上的导电凸起；位于所述基底上及所述导电凸起之间的第一钝化层，所述第一钝化层具有露出所述导电凸起的第一开口；位于所述第一钝化层上的第二钝化层，所述第二钝化层中具有露出所述导电凸起且位于第一开口内的第二开口，所述第二钝化层还具有位于所述第一开口外的第三开口。
可选的，所述第三开口的开口尺寸大于或等于20μm。
可选的，所述第三开口沿平行于基底方向的截面为正六边形结构。
可选的，所述第三开口位于所述半导体芯片的拐角区域。
可选的，在所述半导体芯片的拐角区域有一个或多个第三开口。
可选的，所述第二钝化层的材料是氧化硅、氧化铝、氮化硅、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、聚酰亚胺、聚硅氧烷或硅酮橡胶。
可选的，所述第三开口底部位于所述第一钝化层内部；或者，所述第三开口露出所述第一钝化层表面。
本发明还提供一种封装方法，包括：提供前述的半导体芯片，所述半导体芯片具有导电凸起和第三开口的面为连接面；提供布线基板；在所述半导体芯片的连接面与所述布线基板之间形成粘合层，使所述半导体芯片的连接面与所述布线基板接合固定。
可选的，所述粘合层的材料是环氧树脂胶水。
可选的，在所述半导体芯片的连接面与所述布线基板之间形成粘合层的步骤包括：将所述半导体芯片与所述布线基板进行对位；将对位后的所述半导体芯片与所述布线基板进行焊接；将焊接后的所述半导体芯片与所述布线基板进行底部填充工艺，在所述半导体芯片的连接面与所述布线基板之间形成粘合层。
本发明还提供一种封装结构，包括：前述的半导体芯片，所述半导体芯片具有导电凸起和第三开口的面为连接面；布线基板；位于所述半导体芯片的连接面与所述布线基本之间的粘合层。
与现有技术相比，本发明实施方式的技术方案具有以下优点：
本发明实施方式的方案中，所述第二钝化层中形成有第三开口，提高了所述第二钝化层的粗糙度，因此在填充所述半导体芯片与布线基板之间的空隙时，增强了填充介质与所述半导体芯片的粘合度，从而使形成的封装结构更加稳定，性能更加优良。
可选方案中，所述第三开口位于所述半导体芯片的拐角处。由于所述半导体芯片形成的封装结构拐角处的应力较大，容易引起分层断裂。因此，所述第三开口的引入使得填充介质与所述半导体芯片的粘合度更强，避免了分层现象，提高了所形成的封装结构的性能。
附图说明
图1及图2是一种封装结构的示意图；
图3至图5、图8至图11是本发明半导体结构形成方法一实施例各个步骤对应的剖面结构示意图；
图6为图5的俯视图；
图7为图6的局部放大图；
图12为本发明半导体芯片一实施例的俯视图；
图13为本发明封装结构一实施例的剖面结构示意图。
具体实施方式
参考图1，是一种封装结构的俯视图，图2是图1沿AA1剖线的剖面结构示意图，参考图1及图2，所述封装结构包括半导体芯片10和布线基板20，所述半导体芯片10具有相对的第一表面11和第二表面12，所述第一表面11上具有导电凸起14；位于第一表面11与所述布线基板20之间的粘合层15。
参考图1所示，本申请的发明人发现，由于所述半导体芯片10形成的封装结构四个拐角区域I、区域II、区域III和区域IV，由于位于拐角处，拐角处的粘合层对芯片的应力不均匀，容易引起分层断裂，对半导体芯片的性能及可靠性产生不良的影响。
为解决所述技术问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有连接层；在所述基底上形成第一钝化层，所述第一钝化层具有露出所述连接层的第一开口；形成第二钝化层，所述第二钝化层填充所述第一开口且覆盖所述第一钝化层；在所述第二钝化层中形成第二开口和第三开口；所述第二开口位于第一开口内且露出所述连接层，所述第三开口位于第一开口外；在所述第二开口中形成导电凸起。
本发明通过在第二钝化层中形成开口，提高了所述第二钝化层的粗糙度，因此在填充所述半导体芯片与布线基板之间的空隙时，增强了填充介质与所述半导体芯片的粘合度，从而使形成的封装结构更加稳定，性能更加优良。另外，本发明方案中钝化层中的开口还可以位于所述半导体芯片的拐角处。由于所述半导体芯片形成的封装结构拐角处的应力较大，容易引起分层断裂。因此，所述开口的引入使得填充介质与所述半导体芯片的粘合度更强，避免了分层现象，提高了所形成的封装结构的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图5、图8至图11为本发明半导体结构形成方法一实施例各个步骤对应的剖面结构示意图；图6为图5的俯视图，图7为图6的局部放大图。
参考图3，提供基底100，所述基底100上具有连接层101。所述基底100内形成有电路图形，所述电路图形用于实现电路功能。
所述连接层101用于所述电路图形的电连接。具体的，形成所述连接层101的步骤包括：在所述基底100上形成连接材料层，图形化所述连接材料层形成连接层101。本实施例中，所述连接层101的材料是金属铝；在其他实施例中，所述连接层的材料还可以是铜、金、钼、镍、钛等材料。
继续参考图3，在所述基底100上形成第一钝化层102，所述第一钝化层102具有露出所述连接层101的第一开口103。所述第一钝化层102用于器件之间以及布线之间的电气隔离，所述第一开口103用于为后续的电连接结构提供工艺窗口。
具体的，形成所述第一钝化层102的步骤包括：在所述基底100上形成第一钝化材料层，图形化所述第一钝化材料层形成所述第一钝化层102，所述图形化第一钝化材料层的同时形成露出所述连接层101的第一开口103。
本实施例中，所述第一钝化层102的材料是氧化硅。在其他实施例中，还可以是无机玻璃，例如：氧化铝、氮化硅、磷硅玻璃、硼硅玻璃、硼磷硅玻璃等，或者有机高分子材料，例如：聚酰亚胺、聚硅氧烷、硅酮橡胶等。
形成所述第一钝化材料层的工艺采用的是热生长SiO2膜。
参考图4，形成第二钝化层104，所述第二钝化层104填充所述第一开口103且覆盖所述第一钝化层102；填充于所述第一开口103中的第二钝化层104所对应区域为导电凸起区I，覆盖所述第一钝化层102的第二钝化层104所对应区域为非导电凸起区II。
所述第二钝化层104用于进一步保护所述基底100及位于所述基底100上的其他介质膜。所述导电凸起区I用于后续形成导电凸起，所述非导电凸起区用于为后续形成的第三开口提供工艺窗口。
具体的，本实施例中，所述第二钝化层104的材料是磷硅玻璃。在其他实施例中，所述第二钝化层的材料还可以是无机玻璃，例如：氧化硅、氧化铝、氮化硅、硼硅玻璃、硼磷硅玻璃等或者有机高分子材料，例如：聚酰亚胺、聚硅氧烷、硅酮橡胶等。
形成所述第二钝化层104的工艺采用的是贴膜(Dry film lamination)或涂膜(Coating)。
参考图5，在所述第二钝化层104中形成第二开口105和第三开口106；所述第二开口105位于第一开口103(参考图3)内且露出所述连接层101，所述第三开口106位于第一开口103外。
所述第二开口105用于形成导电凸起以实现电路图形的电连接。所述第三开口106用于提高所述第二钝化层104的粗糙度，因此所述半导体结构所形成的的半导体芯片的粗糙度也增大了，在填充所述半导体芯片与布线基板之间的空隙时，增强了填充介质与所述半导体芯片的粘合度，从而使形成的封装结构更加稳定，性能更加优良。
具体的，形成所述第二开口105与所述第三开口106的步骤包括：形成填充所述第一开口103且覆盖所述第一钝化层102的第二钝化层104，在所述第二钝化层104上形成第一图形层，以所述第一图形层为掩膜刻蚀所述第二钝化层104，形成导电凸起区I第二钝化层104中露出所述连接层101的第二开口105以及非导电凸起区II第二钝化层104中的第三开口106。
参考图6，为图5的俯视图。所述基底100布有多条切割道，如图中所示，切割道201、切割道202、切割道203及切割道204，切割道相交位置处构成拐角区域。形成所述第三开口106的步骤包括：在所述拐角区域形成所述第三开口106。具体的，在所述切割道交叉的拐角区域形成一个或多个所述第三开口106。
所述第三开口106位于所述拐角区域，因此由所述半导体结构形成的半导体芯片的拐角区域具有所述第三开口106。由于所述半导体芯片形成的封装结构拐角处的应力较大，容易引起分层断裂。因此，所述第三开口106的引入使得填充介质与所述半导体芯片的粘合度更强，避免了分层现象，提高了所形成的封装结构的性能。
所述切割道201、切割道202、切割道203及切割道204相交形成区域300。
参考图7，为图6中区域300的局部放大图。所述第三开口106的面积不能过小，如果开口面积过小，会增加填充介质填入开口的难度，使得与所述半导体芯片的粘合度变差，因此，在本发明实施例中，所述第三开口106的开口尺寸大于或等于20μm。所述第三开口106的面积不能过大，如果开口面积过大，同样会造成粗糙度不够的问题，无法增强与所述半导体芯片的粘合度，因此，所述开口尺寸的面积小于等于所述区域300面积的三分之一。
所述第三开口106沿平行于基底方向的截面的形状要使得填充介质的应力比较分散，并且工艺实现比较简单，因此，在本发明实施例中，所述第三开口106沿平行于基底方向的截面呈六边形。在其他实施例中，所述第三开口的截面形状还可以是圆形、规则多边形或者不规则多边形。
由于所述第三开口106的深度不能太深，也不能太浅。如果太深，则容易穿透所述第一钝化层102，使得第一钝化层102对所述基底100的保护作用降低，影响所述半导体结构的性能；如果太浅，则使第二钝化层的粗糙度增大的不够显著。因此，所述第三开口106底部位于所述第一钝化层102内部；或者，所述第三开口106露出所述第一钝化层102表面。在本发明实施例中，所述第三开口106的深度大于等于5μm。
后续在所述第二开口105中形成导电凸起。下面结合图8至图11详细说明在所述第二开口105中形成导电凸起的步骤。
参考图8，在所述第二开口105侧壁及底部形成金属膜107，所述金属膜107还覆盖所述第二钝化层104且覆盖所述第三开口106的侧壁及底部。
所述金属膜107用于形成导电凸起下金属层(UBM,Under Bump Metal)，与所述连接层101具有很强的粘附性，并且能有效阻止导电凸起与所述连接层101及所述基底100之间的相互扩散。
本实施例中，所述金属膜107的材料是铜；在其他实施例中，所述金属膜的材料还可以是铝、钛、铬、镍等金属材料。具体的，采用溅射工艺形成所述金属膜107。所述金属膜可以是单层结构也可以是多层结构。
参考图9，在所述金属膜107上形成第二图形层108，所述第二图形层108在所述第二开口105区域形成有第四开口109，所述第四开口109露出所述金属膜107。
所述第四开口109为后续形成导电凸起提供工艺窗口。
参考图10，在所述第四开口109内填充金属介质形成金属柱110；在所述金属柱110上形成金属帽111。
本实施例中，所述金属柱110与所述金属帽111的材料是Au；在其他实施例中，所述金属柱和所述金属帽的材料还可以是Sn/Pb合金或无铅焊料等。形成所述金属柱110与所述金属帽111的工艺方法为电镀法。
参考图11，去除所述第二图形层108(图10所示)及所述第二图形层108下的所述金属膜107(图10所示)，露出所述第二钝化层104及所述第三开口106；位于所述第四开口109内的所述金属膜107为导电凸起下金属膜112；所述金属帽111、所述金属柱110及所述导电凸起下金属膜112共同构成导电凸起。
所述导电凸起用于与布线基板进行电连接。
在所述第二开口105中形成导电凸起的步骤中，仅在所述第二开口105中形成导电凸起，所述第三开口106中不形成所述导电凸起。
相应的，本发明还提供一种半导体芯片。参考图11，示出了本发明半导体芯片一实施例的剖面结构示意图。
所述半导体芯片包括：基底100，所述基底100上形成有连接层101；位于所述连接层101上的导电凸起；位于所述基底100上及所述导电凸起之间的第一钝化层102，所述第一钝化层102具有露出所述导电凸起的第一开口103；位于所述第一钝化层102上的第二钝化层104，所述第二钝化层104中具有露出所述导电凸起且位于第一开口103内的第二开口103，所述第二钝化层104还具有位于第一开口103外的第三开口106。
本发明实施例中，所述第三开口106的开口尺寸大于或等于20μm，所述第三开口106的开口面积小于或等于所述半导体芯片拐角面积的三分之一。
参考图12，为半导体芯片的俯视图。本发明实施例中，所述第三开口106沿平行于基底100方向的截面为正六边形结构；在其他实施例中，所述第三开口的截面为规则多边形或不规则多边形。
本发明实施例中，所述第三开口106位于所述半导体芯片的拐角区域。位于所述半导体芯片的拐角区域的有益效果请见上述半导体结构方法中的描述，此处不再赘述。
本发明实施例中，在所述半导体芯片的拐角区域有一个或多个所述第三开口106。
本发明实施例中，所述第二钝化层104的材料是氧化硅；在其他实施例中，所述第二钝化层的材料还可以是氧化铝、氮化硅、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、聚酰亚胺、聚硅氧烷或硅酮橡胶。
本发明实施例中，所述第三开口106底部位于所述第一钝化层102内部；或者，所述第三开口106露出所述第一钝化层102表面。
相应的，本发明还提供一种封装方法。参考图13，为本发明封装方法一实施例的剖面结构示意图。
所述封装方法包括：提供前述的半导体芯片，所述半导体芯片具有导电凸起400和第三开口106的面为连接面；提供布线基板；在所述半导体芯片的连接面与所述布线基板之间形成粘合层401，使所述半导体芯片的连接面与所述布线基板接合固定。
所述半导体芯片的导电凸起400由前述的金属帽111、所述金属柱110及所述导电凸起下金属膜112共同构成。所述布线基板由基板402和位于基板上的导电球403构成。
在所述半导体芯片的连接面与所述布线基板之间形成粘合层401的步骤包括：将所述半导体芯片与所述布线基板进行对位；将对位后的所述半导体芯片与所述布线基板进行焊接；将焊接后的所述半导体芯片与所述布线基板进行底部填充工艺，在所述半导体芯片的连接面与所述布线基板之间形成粘合层401。
在本发明实施例中，所述粘合层401的材料是环氧树脂胶水。
所述半导体芯片中包括前述具有第三开口106的第二钝化层104，提高了所述第二钝化层104的粗糙度，因此在填充所述半导体芯片与布线基板之间的空隙时，增强了填充介质与所述半导体芯片的粘合度，从而使形成的封装结构更加稳定，性能更加优良。另外，本发明方案中第二钝化层中的开口还可以位于所述半导体芯片的拐角处。由于所述半导体芯片形成的封装结构拐角处的应力较大，容易引起分层断裂。因此，所述开口的引入使得填充介质与所述半导体芯片的粘合度更强，避免了分层现象，提高了所形成的封装结构的性能。
相应的，本发明还提供一种封装结构，继续参考图13，为本发明封装结构一实施例的剖面结构示意图。
所述封装结构包括：前述的半导体芯片，所述半导体芯片具有导电凸起400和第三开口106的面为连接面；布线基板；位于所述半导体芯片的连接面与所述布线基本之间的粘合层401。
所述半导体芯片的结构、导电凸起的结构及布线基板的结构请参考前述实施例，此处不再赘述。所述粘合层401的材料是环氧树脂胶水。
所述半导体芯片中包括前述具有第三开口106的第二钝化层104，其有益效果请参考前述实施例，此处不再赘述。
综上，本发明方案中所述第二钝化层中形成有第三开口，提高了所述第二钝化层的粗糙度，因此在填充所述半导体芯片与布线基板之间的空隙时，增强了填充介质与所述半导体芯片的粘合度，从而使形成的封装结构更加稳定，性能更加优良。此外，所述第三开口位于所述半导体芯片的拐角处。由于所述半导体芯片形成的封装结构拐角处的应力较大，容易引起分层断裂。因此，所述第三开口的引入使得填充介质与所述半导体芯片的粘合度更强，避免了分层现象，提高了所形成的封装结构的性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底上形成有连接层；
在所述基底上形成第一钝化层，所述第一钝化层具有露出所述连接层的第一开口；
形成第二钝化层，所述第二钝化层填充所述第一开口且覆盖所述第一钝化层；
在所述第二钝化层中形成第二开口和第三开口；所述第二开口位于第一开口内且露出所述连接层，所述第三开口位于第一开口外；
在所述第二开口中形成导电凸起。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三开口的开口尺寸大于或等于20μm。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三开口沿平行于衬底方向的截面呈六边形。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述基底布有多条切割道，切割道相交位置处构成拐角区域，形成第三开口的步骤包括：在所述拐角区域形成第三开口。
5.如权利要求4所述的半导体结构的形成方法，其特征在于，在所述切割道交叉的拐角区域形成一个或多个第三开口。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三开口底部位于所述第一钝化层内部；或者，所述第三开口露出所述第一钝化层表面。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第二钝化层的材料是氧化硅、氧化铝、氮化硅、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、聚酰亚胺、聚硅氧烷或硅酮橡胶。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，在所述第二钝化层中形成第二开口以及第三开口的步骤包括：
形成填充所述第一开口且覆盖所述第一钝化层的第二钝化层；
在所述第二钝化层上形成第一图形层；
以所述第一图形层为掩膜刻蚀所述第二钝化层，形成第二开口以及第三开口。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，在所述第二开口中形成导电凸起的步骤包括：
在所述第二开口侧壁及底部形成金属膜，所述金属膜还覆盖所述第二钝化层且覆盖所述第三开口的侧壁及底部；
在所述金属膜上形成第二图形层，所述第二图形层在所述第二开口区域形成有第四开口，所述第四开口露出所述金属膜；
在所述第四开口内填充金属介质形成金属柱；
在所述金属柱上形成金属帽；
去除所述第二图形层及所述第二图形层下的所述金属膜，露出所述第二钝化层及所述第三开口；
位于所述第四开口内的所述金属膜为导电凸起下金属膜；
所述金属帽、所述金属柱及所述导电凸起下金属膜共同构成导电凸起。
10.一种半导体芯片，其特征在于，包括：
基底，所述基底上形成有连接层；
位于所述连接层上的导电凸起；
位于所述基底上及所述导电凸起之间的第一钝化层，所述第一钝化层具有露出所述导电凸起的第一开口；
位于所述第一钝化层上的第二钝化层，所述第二钝化层中具有露出所述导电凸起且位于第一开口内的第二开口，所述第二钝化层还具有位于所述第一开口外的第三开口。
11.如权利要求10所述的半导体芯片，其特征在于，所述第三开口的开口尺寸大于或等于20μm。
12.如权利要求10所述的半导体芯片，其特征在于，所述第三开口沿平行于基底方向的截面为正六边形结构。
13.如权利要求10所述的半导体芯片，其特征在于，所述第三开口位于所述半导体芯片的拐角区域。
14.如权利要求10所述的半导体芯片，其特征在于，在所述半导体芯片的拐角区域有一个或多个第三开口。
15.如权利要求10所述的半导体芯片，其特征在于，所述第二钝化层的材料是氧化硅、氧化铝、氮化硅、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、聚酰亚胺、聚硅氧烷或硅酮橡胶。
16.如权利要求10所述的半导体芯片，其特征在于，所述第三开口底部位于所述第一钝化层内部；或者，所述第三开口露出所述第一钝化层表面。
17.一种封装方法，其特征在于，包括：
提供如权利要求10至16任一项权利要求所述的半导体芯片，所述半导体芯片具有导电凸起和第三开口的面为连接面；
提供布线基板；
在所述半导体芯片的连接面与所述布线基板之间形成粘合层，使所述半导体芯片的连接面与所述布线基板接合固定。
18.如权利要求17所述的封装方法，其特征在于，所述粘合层的材料是环氧树脂胶水。
19.如权利要求17所述的封装方法，其特征在于，在所述半导体芯片的连接面与所述布线基板之间形成粘合层的步骤包括：
将所述半导体芯片与所述布线基板进行对位；
将对位后的所述半导体芯片与所述布线基板进行焊接；
将焊接后的所述半导体芯片与所述布线基板进行底部填充工艺，在所述半导体芯片的连接面与所述布线基板之间形成粘合层。
20.一种封装结构，其特征在于，包括：
如权利要求10至16任一项权利要求所述的半导体芯片，所述半导体芯片具有导电凸起和第三开口的面为连接面；
布线基板；
位于所述半导体芯片的连接面与所述布线基本之间的粘合层。
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