JP4409455B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4409455B2 JP4409455B2 JP2005022478A JP2005022478A JP4409455B2 JP 4409455 B2 JP4409455 B2 JP 4409455B2 JP 2005022478 A JP2005022478 A JP 2005022478A JP 2005022478 A JP2005022478 A JP 2005022478A JP 4409455 B2 JP4409455 B2 JP 4409455B2
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Description
(1)孔内部を電解メッキ等で充填するのではなく、薄膜の金属メッキを側壁含めた裏面側電極部に形成するだけなので、長時間を要するメッキ充填工程やその後のCMP(Chemical Mechanical Polishing)工程が不要となり、短TATかつ低コストなプロセスで製造できる、
(2)圧接時の塑性流動により貫通電極孔内への注入された金属製バンプは、そのスプリングバック作用により、貫通電極孔内のメッキ電極部と安定した接合状態で維持されるため、常温での圧接のみで電気的な接続を実現できる。さらに、金属製バンプはSiに比べて線膨張係数が大きいため、リフロー加熱時にも熱膨張差によるかしめ状態が形成され、高温時においても安定した接続状態が維持される、
(3)チップ間の接続プロセスは従来の金(Au)のスタッドバンプを用いた圧接工法と同様な装置で対応できるのに加え、必ずしも加熱プロセスを用いる必要がない、
(4)ワイヤボンディングを用いた方法とは異なり、上下チップ間の接続は搭載基板を介さずに接続されるため、搭載基板は最下段の半導体チップから外部電極に接続される配線層のみを形成すればよく、二層あるいは四層基板で構成することが可能となる。したがって、多層のビルドアップ基板で構成された現行基板に比べて、薄型化かつ低コスト化を図ることができる、
(5)異種の半導体チップを積層した場合、例えば上下チップ間に積層されるインターポーザチップは、貫通電極部を形成するプロセス範囲内で裏面側にも再配線層を同時に形成できる。したがって、実質的には二層の配線引回しが可能となり、インターポーザチップとしては、通常、表層アルミ配線一層のみの低コストなチップ構成での使用が可能となる、等がある。
(1)孔内部を電解メッキ等でメッキ充填するのではなく、薄膜の金属メッキを側壁含めた裏面側電極部に形成するだけなので、長時間を要するメッキ充填工程やその後のCMP(Chemical Mechanical Polishing)工程が不要となり、短TATかつ低コストなプロセスで製造できる。
(2)圧接時の塑性流動により貫通電極孔内への注入された金属製バンプは、そのスプリングバック作用により、貫通電極孔内のメッキ電極部と安定した接合状態で維持されるため、常温での圧接のみで電気的な接続を実現できる。さらに、金属製バンプはSiに比べて線膨張係数が大きいため、リフロー加熱時にも熱膨張差によるかしめ状態が形成され、高温時においても安定した接続状態が維持される。
(3)チップ間の接続プロセスは従来の金のスタッドバンプを用いた圧接工法と同様な装置で対応できるのに加え、必ずしも加熱プロセスを用いる必要がない。
(4)ワイヤボンディングを用いた方法とは異なり、上下チップ間の接続は搭載基板を介さずに接続されるため、搭載基板は最下段の半導体チップから外部電極に接続される配線層のみを形成すればよく、二層あるいは四層基板で構成することが可能となる。したがって、多層のビルドアップ基板で構成された現行基板に比べて、薄型化かつ低コスト化を図ることができる。
(5)異種の半導体チップを積層した場合、例えば上下チップ間に積層されるインターポーザチップは、貫通電極部を形成するプロセス範囲内で裏面側にも再配線層を同時に形成できる。したがって、実質的には二層の配線引回しが可能となり、インターポーザチップとしては、通常、表層アルミ配線一層のみの低コストなチップ構成での使用が可能となる、等がある。すなわち、公知例で開示されている貫通電極を用いた接続方法に対比して、非常に低コスト・短TATな構成及びプロセスで済み、かつ金属バンプの塑性流動変形を利用したかしめ作用により高い信頼性をもった独自の接続構造を実現することが可能であり、実用性の高い三次元のチップ間接続構造を提供できる。
本実施形態1では、インターポーザチップ(仲介用配線基板)を介在して異種の半導体チップを三次元的に積層した積層構造を有する半導体装置について説明する。
図1は、半導体装置の概略構成を示す模式的断面図、
図2は、図1の一部を拡大した模式的断面図、
図3は、図1のチップ積層体において、最下段に位置する半導体チップの概略構成を示す図((a)は全体の模式的断面図,(b)は(a)の一部を拡大した模式的断面図)、
図4は、図1のチップ積層体において、最上段に位置する半導体チップの概略構成を示す図((a)は全体の模式的断面図,(b)は(a)の一部を拡大した模式的断面図)、
図5は、図1のチップ積層体において、最下段の半導体チップと最上段の半導体チップとの間に位置するインターポーザチップの概略構成を示す模式的断面図、
図6は、図5の一部を拡大した模式的断面図((a)は図5に向かって左側の電極部分の構成を示す模式的断面図,(b)は図5に向かって右側の電極部分の構成を示す模式的断面図)、
図7は、図6の電極部分の構成を示す模式的平面図((a)はインターポーザチップの主面側から見た電極部分の平面図,(b)はインターポーザチップの裏面側から見た電極部分の平面図)、
図8は、図3(b)の電極部分を拡大した模式的断面図、
図9は、図8の凹状電極の概略構成を示す図((a)は模式的平面図,(b)は模式的断面図)、
図10は、半導体装置の製造に使用される半導体ウエハの模式的平面図、
図11は、図10の半導体ウエハの模式的断面図、
図12は、半導体装置の製造を説明するための模式的平面図、
図13乃至図17は、半導体装置の製造を説明するための図((a)及び(b)は模式的断面図)である。
(1)孔内部を電解メッキ等でメッキ充填するのではなく、薄膜の金属メッキを側壁含めた裏面側電極部に形成するだけなので、長時間を要するメッキ充填工程やその後のCMP(Chemical Mechanical Polishing)工程が不要となり、短TATかつ低コストなプロセスで製造できる。
(2)圧接時の塑性流動により貫通電極孔内(凹状電極の凹部内)へ注入された金属製バンプは、そのスプリングバック作用により、貫通電極孔内のメッキ電極部と安定した接合状態で維持されるため、常温での圧接のみで電気的な接続を実現できる。さらに、金属製バンプはSiに比べて線膨張係数が大きいため、リフロー加熱時にも熱膨張差によるかしめ状態が形成され、高温時においても安定した接続状態が維持される。
(3)チップ間の接続プロセスは従来の金のスタッドバンプを用いた圧接工法と同様な装置で対応できるのに加え、必ずしも加熱プロセスを用いる必要がない。
(4)ワイヤボンディングを用いた方法とは異なり、上下チップ間の接続は搭載基板(パッケージ基板)を介さずに接続されるため、搭載基板は最下段の半導体チップから外部電極に接続される配線層のみを形成すればよく、二層あるいは四層基板で構成することが可能となる。したがって、多層のビルドアップ基板で構成された現行基板に比べて、薄型化かつ低コスト化を図ることができる。
(5)異種の半導体チップを積層した場合、例えば上下チップ間に積層されるインターポーザチップは、貫通電極部を形成するプロセス範囲内で裏面側にも再配線層を同時に形成できる。したがって、実質的には二層の配線引回しが可能となり、インターポーザチップとしては、通常、表層アルミ配線一層のみの低コストなチップ構成での使用が可能となる、等がある。すなわち、公知例で開示されている貫通電極を用いた接続方法に対比して、非常に低コスト・短TATな構成及びプロセスで済み、かつ金属バンプの塑性流動変形を利用したかしめ作用により高い信頼性をもった独自の接続構造を実現することが可能であり、実用性の高い三次元のチップ間接続構造を提供できる。
(6)複数の半導体チップが立体的に積層されたチップ積層体を有する半導体装置の製造において、ダイシング領域22で区画された複数の製品形成領域21を有する半導体ウエハ20を使用し、ガラス基板25に半導体ウエハ20を貼り付けた状態で、半導体ウエハ20の各々の製品形成領域21に圧着を伴う半導体チップを実装することができるので、半導体装置の生産効率向上を図ることができる。
(7)半導体チップ1a上にインターポーザチップ11を介在して半導体チップ1aよりも外形サイズの小さい半導体チップ1bが積層された積層構造を有する半導体装置の製造において、半導体ウエハ20の製品形成領域21に半導体チップ1aを実装する際、接続箇所(電極パッド14a,14b)の下部には樹脂26aからなる土台が形成されているため、製品形成領域21の電極パッド14(14a,14b)が半導体チップ1bよりも外側に位置している場合(先に実装した半導体チップ1bよりも後から実装する半導体チップ1bの外形サイズが大きい場合)であっても、製品形成領域21に損傷を与えることなく、製品形成領域21のスタッドバンプ9を塑性流動に伴う変形によって半導体チップ1aの凹状電極8(8a,8b)の凹部7内に圧接注入することができ、圧着を伴う半導体チップ1aの実装を確実に行うことができる。この結果、半導体装置の製造歩留まり向上を図ることができる。
図18は、実施形態1の変形例1であるインターポーザチップの模式的断面図である。
図19は、本実施形態1の変形例2である半導体チップの模式的断面図である。
図20は、本実施形態1の変形例3であるチップ積層体の一部を示す模式的断面図である。
図21は、本実施形態1の変形例4である半導体チップの一部を示す模式的断面図である。
図22及び図23は、実施形態1の変形例5である半導体装置の製造を説明するための図((a)〜(d)は模式的断面図)である。
図24は、実施形態1の変形例6である半導体装置の製造を説明するための図((a)〜(d)は模式的断面図)である。
図25及び図26は、本発明の実施形態2である半導体装置に係わる図であり、
図25は、半導体装置の概略構成を示す模式的断面図、
図26は、図25のチップ積層体において、各チップの概略構成を示す図((a)は最上段に位置する半導体チップの模式的断面図,(b)はインターポーザチップの模式的断面図,(c)は最下段に位置する半導体チップの模式的断面図)である。
図27は、本発明の実施形態3である半導体装置の概略構成を示す模式的断面図である。
(1)実施形態1では、最下段のチップと搭載基板間は従来のフリップチップ接続であるため、高温での接続プロセスが必須であるが、本実施形態3では搭載基板との接続も常温で可能となる。したがって、接続プロセスにおける温度階層がなくなり、微細接続に有利である、
(2)ポリイミド系フィルムをベースにすることで、二層基板での厚さは30−50μmとなり、更なる薄型化が可能となる、等がある。
図28は、本発明の実施形態4である半導体装置の概略構成を示す模式的断面図である。
(1)インターポーザチップが不要となり、より低コストかつ短TATな三次元のチップ間接続が可能となる。ただし、本実施形態を適用するための前提条件としては、上段側の半導体チップの接合領域が、下段側の半導体チップサイズ以下であること、また、下段側半導体チップの裏面側での多層引き回しは困難であり、一層の再配線で上下チップ間の接続を可能とする上下チップ相互の適正なピン配置が達成されていることが必要である、
(2)上下半導体チップ相互のチップ間接続の配線長がより最短化され、配線インダクタンスの低減が図れる、等がある。
図30は、本発明の実施形態5である半導体装置の概略構成を示す模式的断面図であり、
図31は、図30の半導体装置の結線状態を示すブロック図である。
2…半導体基板、3…薄膜積層体、4(4a,4b,4c,4d)…電極パッド、5…孔、6…導電膜、6a…シード層、6b…メッキ層、7…凹部、8(8a,8b,8c,8d)…凹状電極、9…スタッドバンプ、
11…インターポーザチップ(仲介用配線基板)、12…半導体基板、13…導電膜、14(14a,14b,14c,14d)…電極パッド、15…孔、16…導電膜、17…凹部、18(18a,18b,18c,18d)…凹状電極、
20…半導体ウエハ、21…製品形成領域、22…ダイシング領域、
25…ガラス基板、25a…接着材、
26,26a,26b、26c…接着材、
27…ダイシングテープ、27a…接着材、
30,30a,30b,30c…チップ積層体、
31…製品形成領域、32…ダイシング領域、33,34…電極パッド、35…多数個取り配線基板、36…配線基板、37…半田バンプ、
40…グランドライン、41…チップセレクト用アドレスライン。
Claims (2)
- (a);主面に配置された第1、及び第2の電極パッドと、
前記主面とは反対側の裏面側から前記第1の電極パッドに向かって窪む凹部を有し、当該凹部における内径は、少なくともその一部が前記第1の電極パッドに向かう奥行き方向に対して広くなるよう形成され、前記第1の電極パッドに接続された第1の凹状電極と、
前記裏面側から前記第2の電極パッドに向かって窪む凹部を有し、当該凹部における内径は、少なくともその一部が前記第2の電極パッドに向かう奥行き方向に対して広くなるよう形成され、前記第2の電極パッドに接続された第2の凹状電極と、
を備えた第1の半導体チップを準備する工程と、
(b);主面に配置された第3及び第4の電極パッドと、
前記第3の電極パッド上に配置され、前記主面から突出する第1の突起状電極と、
前記第4の電極パッド上に配置され、前記主面から突出する第2の突起状電極と、
を備えた第2の半導体チップを準備する工程と、
(c);ダイシング領域で区画された複数の製品形成領域を有する半導体ウエハであって、前記各製品形成領域は、
主面に配置された第5、第6及び第7の電極パッドと、
前記主面とは反対側の裏面側から前記第7の電極パッドに向かって窪む凹部を有し、当該凹部における内径は、少なくともその一部が前記第7の電極パッドに向かう奥行き方向に対して広くなるよう形成され、前記第7の電極パッドに接続された第3の凹状電極と、
前記裏面側から前記第6の電極パッドに向かって窪む凹部を有し、当該凹部における内径は、少なくともその一部が前記第6の電極パッドに向かう奥行き方向に対して広くなるよう形成され、前記第6の電極パッドに接続された第4の凹状電極と、
前記裏面側から前記主面側に向かって窪む凹部を有し、当該凹部における内径は、少なくともその一部が前記主面に向かう奥行き方向に対して広くなるよう形成された第5の凹状電極と、
前記主面に形成され、前記第5の電極パッドと前記第7の電極パッドとを電気的に接続する第1の配線と、
前記裏面に形成され、前記第4の凹状電極と前記第5の凹状電極とを電気的に接続する第2の配線と、
を備えた半導体ウエハを準備する工程と、
(d);ガラス基板に前記各製品形成領域の主面が向かい合う状態で、前記ガラス基板に前記半導体ウエハを貼り付ける工程と、
(e);前記ガラス基板に前記半導体ウエハが貼り付けられた状態で、前記各製品形成領域において、前記製品形成領域の裏面に向かって前記第2の半導体チップを圧着し、前記製品形成領域の前記第3の凹状電極の凹部内に前記第2の半導体チップの前記第1の突起状電極の一部、前記製品形成領域の前記第4の凹状電極の凹部内に前記第2の半導体チップの前記第2の突起状電極の一部を、それぞれ塑性流動に伴う変形によって圧接注入する工程と、
(f);前記ガラス基板から前記半導体ウエハを剥離する工程と、
(g);前記(f)工程の後、前記各製品形成領域において、前記製品形成領域の前記第5の電極パッド上に第3の突起状電極、前記製品形成領域の前記第6の電極パッド上に第4の突起状電極を形成する工程と、
(h);前記(g)工程の後、前記各製品形成領域において、前記製品形成領域の主面に向かって前記第1の半導体チップを圧着し、前記第1の半導体チップの前記第1の凹状電極の凹部内に前記製品形成領域の前記第3の突起状電極の一部、前記第1の半導体チップの前記第2の凹状電極の凹部内に前記製品形成領域の前記第4の突起状電極を、それぞれ塑性流動に伴う変形によって圧接注入する工程と、
(i);前記半導体ウエハの前記各製品形成領域を個片化する工程と、
を有することを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記各製品形成領域の第5及び第6の電極パッドは、前記第2の半導体チップの周囲に配置され、
前記(h)工程では、前記製品形成領域の裏面から前記第2の半導体チップの裏面までの距離とほぼ同じ厚さの土台が前記製品形成領域の前記第5及び第6の電極パッド下に配置されていることを特徴とする半導体装置の製造方法。
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