TW201530723A - 用於處理導線框表面之方法及具有經處理之導線框表面之裝置 - Google Patents

用於處理導線框表面之方法及具有經處理之導線框表面之裝置 Download PDF

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Publication number
TW201530723A
TW201530723A TW103145865A TW103145865A TW201530723A TW 201530723 A TW201530723 A TW 201530723A TW 103145865 A TW103145865 A TW 103145865A TW 103145865 A TW103145865 A TW 103145865A TW 201530723 A TW201530723 A TW 201530723A
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Taiwan
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region
lead frame
pin
leadframe
tip
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TW103145865A
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English (en)
Inventor
Joseph D Fernandez
Ekgachai Kenganantanon
Greg Perzanowski
Tarapong Soontornvipart
Oliver Mabutas
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Microchip Tech Inc
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Publication of TW201530723A publication Critical patent/TW201530723A/zh

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Abstract

本發明揭示一種用於製造一積體電路裝置之方法。提供一導線框，其具有經組態以接納一積體電路晶粒之一晶粒支撐區域及與晶粒支撐區域相鄰之複數個導線框引腳，各導線框引腳包含在該導線框引腳之一個端處之一引腳尖端區域。該導線框經遮蔽使得該導線框之一或多個區域被覆蓋且該導線框之一或多個區域曝露，其中針對各導線框引腳，該各自引腳尖端區域之一第一區由該遮蔽覆蓋且該各自引腳尖端區域之一第二區曝露。該導線框之該一或多個曝露區域鍍銀，使得針對各導線框引腳，該各自引腳尖端區域之該第二區鍍銀且該各自引腳尖端區域之該第一區不鍍銀。

Description

用於處理導線框表面之方法及具有經處理之導線框表面之裝置 [相關申請案之交叉參考]
此申請案主張2013年12月27日申請之美國臨時申請案第61/921,141號之權利，該案之全文併入本文中。
本發明係關於半導體製造，特定言之係關於一種用於處理導線框表面之方法。
許多或大多數積體電路(「IC」)封裝在如由JEDEC MSL(「水分敏感度等級」)測試指定之85℃及85%濕度之水分負載要求達168個小時之一持續時間後遇到分層。在此文中，分層係指歸因於一模製化合物與鍍銀區域之間的較差黏著，在鍍銀導線引腳區域與模製化合物之間的一分離。已知鍍銀具有一光滑表面，且因此模製化合物常無法正確黏著至電鍍區域。分層可影響IC封裝，導致諸如當對封裝施加壓力時之可靠性測試期間例如歸因於水分、溫度或濕度之封裝及線接合缺陷。分層亦可導致產品現場故障，諸如損壞或抬升之線接合。
因此，需要消除IC封裝(諸如8L SOIC & 28SOIC半導體裝置外殼)中之導線引腳分層。JEDEC要求規定在MSL 1下使用塗鈀銅線之線接合區域上的零分層，MSL 1分級指示裝置不對水分敏感。必須在容許時段(袋外車間壽命)內安裝且回焊組件。減少或消除導線引腳分層之 一個方法係將裝置降級至MSL3，該分級定義裝置組裝於一PCB上前最多曝露至環境條件一週。然而，此通常對零件添加大量成本，且當自水分障壁袋取出零件時需要消費者特殊處理零件。
意在解決此問題之另一方法係移除導線框上之鍍銀以容許模製化合物增大與導線框之銅表面之黏著。此有助於減少分層，但並未解決問題，因為線接合需要鍍銀。
根據各種實施例，可消除導線框分層，且使一線接合程序更可靠。根據一些實施例，一機械遮罩用於導線框之鍍銀，該遮罩使在導線尖端處曝露銅區域，該等區域因此並不鍍銀。此減小鍍銀區域，且增大導線尖端處之銅區域以容許模製化合物(其在一IC晶粒安裝且連接至導線框後施加)完全黏著於導線引腳之銅表面，此可產生並不分層之一「鎖定」機構。
揭示提供一種用於製造一積體電路裝置之方法之一項實施例。提供一導線框，其具有經組態以接納一積體電路晶粒之一晶粒支撐區域及與晶粒支撐區域相鄰之複數個導線框引腳，各導線框引腳包含在導線框引腳之一個端處之一引腳尖端區域。導線框經遮蔽使得導線框之一或多個區域被覆蓋且導線框之一或多個區域曝露，其中針對各導線框引腳，各自線接合區域之一第一區由該遮蔽覆蓋且各自線接合區域之一第二區曝露。導線框之一或多個曝露區域鍍銀，使得針對各導線框引腳，各自線接合區域之第二區鍍銀且各自線接合區域之第一區不鍍銀。
在一進一步實施例中，方法進一步包含：將積體電路晶粒附接至導線框之晶粒支撐區域；將積體電路晶粒線接合至複數個導線框引腳，其包含將一線接合至各導線框引腳之線接合區域之鍍銀區，且將一模製材料施加於導線框及積體電路晶粒上方，使得模製材料直接接 觸各導線框引腳之線接合區域之第一、非鍍銀區。
在一進一步實施例中，針對複數個導線框引腳之至少一者，導線框引腳自靠近導線框之晶粒支撐區域之一第一端延伸至較遠離晶粒支撐區域之一第二端或區域，且線接合區域之第一、非鍍銀區定位於靠近晶粒支撐區域之導線框引腳之第一端處。
在一進一步實施例中，針對複數個導線框引腳之至少一者，線接合區域之第一、非鍍銀區按幾何定位於線接合區域之第二、鍍銀區與導線框之晶粒支撐區域之間。
在一進一步實施例中，遮蔽步驟包括遮蔽導線框，使得針對導線框引腳之至少一者，各自線接合區域之一第一區由該遮蔽覆蓋，且各自線接合區域之至少兩個第二區曝露，至少兩個第二區與彼此間隔開。
在一進一步實施例中，遮蔽步驟包括遮蔽導線框，使得針對導線框引腳之至少一者，各自線接合區域之一第一區由該遮蔽覆蓋，且各自線接合區域之一對第二區曝露，其中第一覆蓋區定位於該對第二區之間。
在一進一步實施例中，導線框包含具有一線接合區域之至少一個額外導線框引腳，該線接合區域完全鍍銀或完全不鍍銀。
另一實施例提供一積體電路結構，該結構包含一導線框，該導線框包括經組態以接納一積體電路晶粒之一晶粒支撐區域及與晶粒支撐區域相鄰之複數個導線框引腳，各導線框引腳包含在導線框引腳之一個端處之一引腳尖端區域。各導線框引腳之線接合區域包含一表面，該表面包含鍍銀之一第一區及不鍍銀之一第二區。
在一進一步實施例中，積體電路結構進一步包含：一積體電路晶粒，其安裝至導線框之晶粒支撐區域；線接合連接，其等在積體電路晶粒與各線接合區域之第一、鍍銀區之間；及一模製材料，其經施 加於導線框及積體電路晶粒上方，其中模製材料直接接觸各線接合區域之第二、非鍍銀區。
在一進一步實施例中，針對複數個導線框引腳之至少一者，導線框引腳自靠近導線框之晶粒支撐區域之一第一端延伸至較遠離晶粒支撐區域之一第二端或區域，且線接合區域之第二、非鍍銀區定位於靠近晶粒支撐區域之導線框引腳之第一端處。
在一進一步實施例中，針對複數個導線框引腳之至少一者，線接合區域之第二、非鍍銀區按幾何定位於線接合區域之第一、鍍銀區與導線框之晶粒支撐區域之間。
在一進一步實施例中，針對複數個導線框引腳之至少一者，線接合區域之表面包含與彼此間隔開之至少一個第二、非鍍銀區。
在一進一步實施例中，針對複數個導線框引腳之至少一者，線接合區域之表面包含一對第二、非鍍銀區，其中第一、鍍銀區定位於該對第二、非鍍銀區之間。
在一進一步實施例中，導線框包含具有一線接合區域之至少一個額外導線框引腳，該線接合區域完全鍍銀或完全不鍍銀。
10‧‧‧導線框
12‧‧‧晶粒支撐區或板
14‧‧‧導線引腳
16‧‧‧連接結構/連接區
20‧‧‧導線引腳尖端區域/尖端
30a‧‧‧遮罩邊界
30b‧‧‧遮罩邊界
40‧‧‧鍍銀區
50a‧‧‧邊界線
50b‧‧‧邊界線
50c‧‧‧開口
50d‧‧‧開口
50e‧‧‧開口
50f‧‧‧開口
50g‧‧‧開口
50h‧‧‧開口
52‧‧‧遮蔽區
60‧‧‧鍍銀區域/鍍銀區
62‧‧‧非鍍銀區域/非鍍銀區
100‧‧‧例示性程序
102‧‧‧步驟
104‧‧‧步驟
106‧‧‧步驟
108‧‧‧步驟
110‧‧‧步驟
112‧‧‧步驟
114‧‧‧步驟
116‧‧‧步驟
150‧‧‧晶圓
152‧‧‧IC裝置基板陣列
154‧‧‧晶圓黏片
160‧‧‧切割線
170‧‧‧環氧樹脂
180‧‧‧塗鈀銅或金線接合
190‧‧‧積體電路裝置/晶片
CL‧‧‧切割線
下文參考圖式討論例示性實施例，其中：圖1展示用於安裝一積體電路晶粒以形成一積體電路裝置(例如，一晶片)之一例示性導線框；圖2A繪示用於鍍銀一導線框之導線引腳尖端區域之一現存或習知遮蔽；圖2B展示使用圖2A中展示之現存或習知遮蔽之導線框之產生之鍍銀；圖3A根據一第一例示性實施例繪示用於鍍銀一導線框之導線引腳尖端區域之一例示性遮蔽組態； 圖3B展示使用圖3A中展示之遮蔽之導線框之產生之鍍銀，該遮蔽界定導線引腳尖端上之非鍍銀區域以改良與一模製化合物之黏著；圖4A根據一第二例示性實施例繪示用於鍍銀一導線框之導線引腳尖端區域之另一例示性遮蔽組態；圖4B展示使用圖4A中展示之遮蔽之導線框之產生之鍍銀，該遮蔽界定導線引腳尖端上之非鍍銀區域以改良與一模製化合物之黏著；及圖5根據一例示性實施例繪示用於製造一積體電路裝置之一例示性程序，該積體電路裝置具有：一晶粒，其安裝至一導線框；一模製化合物，其形成於結構上方；及一改良黏著，其在模製化合物與導線引腳尖端之非鍍銀區域之間。
圖1展示在被處理(例如，藉由鍍銀導線框)、將一積體電路(IC)晶粒安裝至導線框、將IC晶粒線接合至導線框、模製導線框且(例如)沿例示性切割線CL自一更大導線框陣列切割導線框之前之一例示性導線框10。圖1中展示例示性導線框10，其用界定經組態以支撐安裝至其之一積體電路晶粒之一晶粒支撐區或板12之一圖案、經配置圍繞晶粒支撐區12(且與之間隔開)之一周邊之複數個導線引腳14及將晶粒支撐區12實體連接至包含導線引腳14之導線框10之剩餘部分之一或多個連接結構16形成。各導線引腳14包含一尖端區20，尖端區20靠近晶粒支撐區12且經組態用於(例如，藉由線接合)電連接至安裝於晶粒支撐區12上之一積體電路晶粒。
導線框10可自任何適當材料形成，例如，銅或一銅合金、含有鎳、鈷或鉻之一鐵合金、鎳或一鎳合金或任何其他適當材料。為討論之目的，本文討論一銅導線框；然而，應理解，本文討論之概念不限於一銅導線框，而適用於任何其他適當材料之導線框。另外，圖1中 展示之導線框10之形狀及圖案僅係一實例；導線框10亦可具有任何其他適當圖案及形狀，其等包含晶粒支撐區或板12、導線引腳14及連接結構16之任何其他適當配置。
導線引腳尖端區域20可經塗佈或電鍍有任何適當材料以提供安裝至導線框10之IC晶粒與導線引腳14之材料(在本文討論之實例中為銅)之間的一所需電及機械接觸(例如，經由線接合)。在(例如)如本文討論之一些實施例中，導線引腳尖端區域20可經塗佈或電鍍有銀。在(例如)如本文討論之其他實施例中，導線引腳尖端區域20可經塗佈或電鍍有另一適當材料。
圖2A及圖2B繪示用於鍍銀導線框10之導線引腳尖端區域20之一現存或習知技術。為施加鍍銀，使用任何適當遮蔽設備及技術來遮蔽導線框10，且接著，將鍍銀施加至導線框10之曝露區域。圖2A展示一例示性遮蔽，其中遮蔽在遮罩邊界30b內側之區域及在遮罩邊界30a外側之區域，因此曝露在遮罩邊界30a與30b之間的導線框10之區域。圖2B展示使用圖2A之遮蔽組態之鍍銀之結果。如展示，在各導線引腳尖端20上界定一鍍銀區40。
圖2A及圖2B繪示用於鍍銀導線框10之導線引腳尖端區域20之一現存或習知技術。為施加鍍銀，使用任何適當遮蔽設備及技術來遮蔽導線框10，且接著，將鍍銀施加至導線框10之曝露區域。圖2A展示一例示性遮蔽，其中遮蔽在遮罩邊界30b內側之區域及在遮罩邊界30a外側之區域，因此曝露在遮罩邊界30a與30b之間的導線框10之區域。圖2B展示使用圖2A之遮蔽組態之鍍銀之結果。如展示，在各導線引腳尖端20上界定一鍍銀區40。
圖3A及圖3B根據本發明之一第一例示性實施例繪示用於鍍銀導線框10之導線引腳尖端區域20之一改良技術之一實例。為施加鍍銀，使用一或多個實體或機械遮罩來遮蔽導線框10，使得針對各導線框引 腳14，引腳尖端區域20之一第一區被遮蔽且引腳尖端區域20之至少一個第二區通過遮罩曝露。圖3A展示一實體遮罩之一實例，該遮罩界定包含由邊界線50a及50b界定之一對開口之一遮罩圖案。根據此遮蔽，針對各導線框引腳14，最接近晶粒支撐區12之引腳尖端區域20之一區(指示為區52)經遮蔽以防止該區鍍銀。如展示，各引腳尖端區域20之遮蔽區52可相對於晶粒支撐區域12定位於各自引腳尖端區域20之曝露區域內。
圖3B展示使用圖3A之例示性遮罩圖案之鍍銀之結果。如展示，一鍍銀區域60界定於各導線引腳尖端20上，且一非鍍銀區域62(對應於圖3A中展示之遮蔽區52)相對於晶粒支撐區12界定於鍍銀區60內之各導線引腳尖端20上。在一些實施例中，遮罩圖案可在各引腳尖端區域20中界定定位於一對遮蔽區之間的一曝露區，使得在鍍銀後，各引腳尖端區域20包含定位於兩個非鍍銀區62之間的鍍銀區60，其中相對於晶粒支撐區12，一個非鍍銀區62定位於鍍銀區60內，且另一個非鍍銀區62定位於鍍銀區62外。
在一些實施例中，遮罩完全覆蓋或完全曝露至少一個導線引腳尖端20，使得至少一個導線引腳尖端20經完全鍍銀或完全不鍍銀。另外，取決於特定實施例，遮罩可或可不曝露任何連接區16之(若干)區域。
導線引腳尖端20之非鍍銀區62減小導線引腳尖端20上之鍍銀區域，且提供用於在導線引腳尖端20之非鍍銅表面與模製化合物之間直接接觸之一區域，該模製化合物後續在一IC晶粒安裝至導線框10且電連接(例如，線接合)至各尖端20上鍍銀區60處之各導線引腳尖端20後施加至結構。模製化合物可靠黏著至導線引腳尖端20(在非鍍銀區62處)之曝露銅，且不同於在模製化合物與鍍銀之間傾向於隨著時間而分層之介面，該模製化合物不分層。特定言之，藉由在朝向尖端20之 最遠端(靠近晶粒支撐區12)之方向上，在各導線引腳尖端20之端部分處(即，超過各自鍍銀區60)提供一非鍍銀區62，非鍍銀區62與模製化合物之間的直接接觸產生導線引腳14之一「鎖定」機構，該機構減少或防止各自鍍銀區60與模製化合物分層。在導線引腳尖端20與模製化合物之間的此牢固連接容許IC晶粒至導線引腳14隨著時間的可靠線接合(例如，使用塗鈀銅或金線接合)。
圖4A及圖4B根據本發明之一第二例示性實施例繪示用於鍍銀導線框10之導線引腳尖端區域20之一改良技術之另一實例。如在圖4A中展示，遮罩界定數個開口50c至50h，該等開口曝露下伏導線框10之特定區域。特定言之，針對各導線框引腳尖端區域20，遮罩圖案係使得一第一區曝露且在第一區之任一側上之一對第二區由遮罩覆蓋。
圖4B展示使用圖4A之例示性遮罩圖案之鍍銀之結果。如展示，各導線引腳尖端區域20包含一鍍銀區60、在鍍銀區60之相對側上之一對非鍍銀區62。非鍍銀區62提供用於導線引腳尖端20之銅表面與後續施加至結構之模製化合物之間直接接觸之區域，此可產生導線引腳14與模製化合物之間的一「鎖定」機構，該機構減少或防止鍍銀區60與模製化合物分層。
應理解，在圖3A及圖4A中展示之遮罩圖案僅係實例，且遮罩可具有導致個別導線引腳尖端區域20之一或多個非鍍銀區域以改良與後續施加之模製化合物之黏著之任何其他適當圖案。
圖5根據一例示性實施例繪示用於製造一積體電路裝置190之一例示性程序100。在步驟102提供界定一IC裝置基板陣列152之一晶圓150。在步驟104，例如使用環氧樹脂及/或黏著帶將晶圓150安裝至一晶圓黏片154。在步驟106，如由切割線160指示，使用一晶圓鋸切割晶圓。在步驟108，在晶圓上執行一遮蔽及鍍銀程序，使得各導線框10之導線框引腳尖端20具有一或多個非鍍銀區域62(例如，如上文討 論)。舉例而言，可在步驟108使用諸如在圖3A或圖4A之例示性實施例中展示之一遮罩。
在步驟110，一IC晶粒經挑選且(例如，使用一環氧樹脂170及固化程序)附接至各導線框10之晶粒支撐區12。在步驟112，各晶粒(例如，使用塗鈀銅或金線接合180)線接合至各自導線框10之各導線框引腳尖端20之鍍銀區60。在步驟114，在一塑膠或其他適當模製化合物中模製結構。如上文討論，導線框引腳尖端20之非鍍銀區域62直接接觸模製化合物，且提供一牢固黏著，從而將模製化合物鎖定至導線框引腳14。在步驟116，晶圓經標記且分割，而導致複數個離散IC裝置/晶片190。
上文之教示可提供各種優點。首先，可消除或實質上減少導線框與模製化合物之間的分層。因此，產生之裝置可更可能滿足JEDEC MSL1可靠性標準。此外，產生之IC裝置之產品可靠性及壽命可延長。可實質上減少或消除現場故障中抬升、損壞線接合之發生及對應之消費者申訴。此外，相較於諸如將裝置降級至MSL3之解決方案，所揭示之解決方案可例如藉由消除乾燥封裝之需要，提供封裝方法中之成本節省。最後，歸因於無烘烤程序，可減少生產週期時間。
儘管在本發明中詳細描述所揭示之實施例，但應理解，在不脫離該等實施例之精神及範疇的情況下可對其等做出各種改變、替換及更改。
10‧‧‧導線框
12‧‧‧晶粒支撐區或板
14‧‧‧導線引腳
20‧‧‧導線引腳尖端區域/尖端
50a‧‧‧邊界線
50b‧‧‧邊界線
52‧‧‧遮蔽區

Claims (14)

  1. 一種用於製造一積體電路裝置之方法，該方法包括：提供一導線框，其包括：一晶粒支撐區域，其經組態以接納一積體電路晶粒；及複數個導線框引腳，其等與該晶粒支撐區域相鄰，各導線框引腳包含在該導線框引腳之一個端處之一引腳尖端區域；遮蔽該導線框，使得該導線框之一或多個區域被覆蓋且該導線框之一或多個區域曝露，其中針對各導線框引腳，該各自引腳尖端區域之一第一區由該遮蔽覆蓋且該各自引腳尖端區域之一第二區曝露；及鍍銀該導線框之該一或多個曝露區域，使得針對各導線框引腳，該各自引腳尖端區域之該第二區鍍銀且該各自引腳尖端區域之該第一區不鍍銀。
  2. 如請求項1之方法，其進一步包括：將該積體電路晶粒附接至該導線框之該晶粒支撐區域；將該積體電路晶粒線接合至該複數個導線框引腳，此包含將一線接合至各導線框引腳之該引腳尖端區域之該鍍銀區；及在該導線框及積體電路晶粒上方施加一模製材料，使得該模製材料直接接觸各導線框引腳之該引腳尖端區域之該第一、非鍍銀區。
  3. 如請求項1之方法，其中，針對該複數個導線框引腳之至少一者：該導線框引腳自靠近該導線框之該晶粒支撐區域之一第一端延伸至較遠離該晶粒支撐區域之一第二端或區域；及該引腳尖端區域之該第一、非鍍銀區定位於靠近該晶粒支撐 區域之該導線框引腳之該第一端處。
  4. 如請求項1之方法，其中，針對該複數個導線框引腳之至少一者，該引腳尖端區域之該第一、非鍍銀區按幾何定位於該引腳尖端區域之該第二、鍍銀區與該導線框之該晶粒支撐區域之間。
  5. 如請求項1之方法，其中該遮蔽步驟包括遮蔽該導線框，使得針對該等導線框引腳之至少一者，該各自引腳尖端區域之一第一區由該遮蔽覆蓋，且該各自引腳尖端區域之至少兩個第二區曝露，該至少兩個第二區與彼此間隔開。
  6. 如請求項1之方法，其中該遮蔽步驟包括遮蔽該導線框，使得針對該等導線框引腳之至少一者，該各自引腳尖端區域之一第一區由該遮蔽覆蓋，且該各自引腳尖端區域之一對第二區曝露，其中該第一覆蓋區定位於該對第二區之間。
  7. 如請求項1之方法，其中該導線框包含具有一引腳尖端區域之至少一個額外導線框引腳，該引腳尖端區域完全鍍銀或完全不鍍銀。
  8. 一種積體電路結構，其包括：一導線框，其包括：一晶粒支撐區域，其經組態以接納一積體電路晶粒；及複數個導線框引腳，其等與該晶粒支撐區域相鄰，各導線框引腳包含在該導線框引腳之一個端處之一引腳尖端區域；其中各導線框引腳之該引腳尖端區域包含一表面，其包含：一第一區，其經鍍銀；及一第二區，其不鍍銀。
  9. 如請求項8之積體電路結構，其進一步包括：一積體電路晶粒，其經安裝至該導線框之該晶粒支撐區域； 線接合連接，其等在該積體電路晶粒與各導線框引腳尖端區域之該第一、鍍銀區之間；及一模製材料，其施加於該導線框及積體電路晶粒上方，其中該模製材料直接接觸各導線框引腳尖端區域之該第二、非鍍銀區。
  10. 如請求項8之積體電路結構，其中，針對該複數個導線框引腳之至少一者：該導線框引腳自靠近該導線框之該晶粒支撐區域之一第一端延伸至較遠離該晶粒支撐區域之一第二端或區域；及該引腳尖端區域之該第二、非鍍銀區定位於靠近該晶粒支撐區域之該導線框引腳之該第一端處。
  11. 如請求項8之積體電路結構，其中，針對該複數個導線框引腳之至少一者，該引腳尖端區域之該第二、非鍍銀區按幾何定位於該引腳尖端區域之該第一、鍍銀區與該導線框之該晶粒支撐區域之間。
  12. 如請求項8之積體電路結構，其中，針對該複數個導線框引腳之至少一者，該引腳尖端區域之該表面包含與彼此間隔開之至少兩個第二、非鍍銀區。
  13. 如請求項8之積體電路結構，其中，針對該複數個導線框引腳之至少一者，該引腳尖端區域之該表面包含一對第二、非鍍銀區，其中該第一、鍍銀區定位於該對第二、非鍍銀區之間。
  14. 如請求項8之積體電路結構，其中該導線框包含具有一引腳尖端區域之至少一個額外導線框引腳，該引腳尖端區域完全鍍銀或完全不鍍銀。
TW103145865A 2013-12-27 2014-12-26 用於處理導線框表面之方法及具有經處理之導線框表面之裝置 TW201530723A (zh)

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