CN104303299A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN104303299A
CN104303299A CN201380025448.2A CN201380025448A CN104303299A CN 104303299 A CN104303299 A CN 104303299A CN 201380025448 A CN201380025448 A CN 201380025448A CN 104303299 A CN104303299 A CN 104303299A
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terminal
shell
packaging part
semiconductor device
power semiconductor
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CN104303299B (zh
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田中淳也
南尾匡纪
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Abstract

本发明提供一种单个外壳(2)内集成了多个封装件(6、6)的半导体装置的制造方法，其将具有第一端子(1)的外壳(2)以其底部的开口部(30)朝下的方式载放到操作台(3)上，将具有第二端子(4)的封装件(6、6)通过外壳(2)的开口部(30)载放到操作台(3)上，第一端子(1)与第二端子(4)之间形成间隙(31)，在间隙(31)中装入接合材料(7)，并将第一端子(1)与第二端子(4)电连接。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明涉及包含有开关元件等功率器件且用于逆变器等功率转换用途的半导体装置。
背景技术
对于太阳能发电系统的功率调节器、用于发动机旋转控制的功率器件，为了能够减小安装面积、缩短半导体元件之间的距离来提高性能、减轻用户方的设计负荷，将多个功率器件集成在一个封装件中的模块化成品逐渐增多。
被集成在一个封装件中的产品称为功率模块。该功率模块中搭载有多个进行开关的IGBT(insulated gate bipolar transistor：绝缘栅双极型晶体管)、MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)之类的功率半导体元件。搭载有用于驱动该功率半导体元件的多个驱动元件且在必要时还同时内置有多个无源元件从而具有驱动和保护功率半导体的功能的模块被特殊地称为IPM(Intelligent PowerModule：智能功率模块)，其市场占有额正在逐步扩大。
该功率模块结构的制造方法通常是在被称为嵌入式外壳的树脂成型的壳体内，配置被接合在陶瓷基板上的功率半导体元件，利用Al等金属导线将外壳的端子与功率半导体元件的表面连接之后，灌注硅胶从而将其一并密封。
但是，由于不同的模块尺寸和结构，安装在在嵌入式外壳背面的散热板有时会发生弯曲，从而难以确保背面的平坦性。这种情况下，如果用散热润滑剂将功率模块安装到散热器上，则不同部位的散热润滑剂厚度会产生偏差，厚度较大部分的散热效率将显著下降，因此有可能导致功率模块发生热损。
专利文献1中公开了针对这一问题的策略。
图10(a)、图10(b)是专利文献1所记载的半导体装置100的俯视图。图10(b)是图10(a)的剖视图。
半导体装置100包括外壳101和至少2个以上的封装件102。外壳101由树脂成型的壳体形成，设有外部端子103和输出端子104。外壳101的4个角上设有用于和散热器(未图示)连接的螺钉孔105。封装件102包括由例如Cu构成的金属块106。金属块106的背面固定有陶瓷等的绝缘基板114。金属块106上隔着金属引线框107固定有功率半导体元件108。功率半导体元件108使用例如MOSFET或IGBT。另外，功率半导体元件108的表面电极通过由Al等形成的直径为300μm左右的接合线109而与内部引线110连接。
金属块106和功率半导体元件108还被环氧树脂等模塑树脂111密封，并使一部分引线框107露出。
从模塑树脂111引出功率端子112和控制端子113并使其露出。功率端子112与外壳101的外部端子103和输出端子104相连接。控制端子113从模塑树脂111上与引出功率端子112的那条边不同的边引出。
对该半导体装置的制造方法作简单说明。
首先，在金属块106上固定引线框107，再在其上配置功率半导体元件108，之后，用压铸模装置进行树脂成型。即，将固定了金属块106等的引线框107配置到模具内之后，使环氧树脂流入模具内，从而形成模塑树脂111。
这种情况下，金属块106的背面从所述模具露出。在形成了模塑树脂111之后，将金属块106从所述模具去除，用焊锡等在金属块106的背面接合绝缘基板114。
最后，去除引线框107中不需要的部分，将引线框107加工成所期望的形状，从而形成功率端子112和控制端子113。至此，封装件102的组装结束。
接着，如图10(a)和图10(b)所示，将封装件102放入外壳101中，并将外部端子103、输出端子104与功率端子112相连接。这一连接可以使用例如焊锡等。通过连接功率端子112与外部端子103、输出端子104，封装件102被固定在外壳101中。
现有技术文献
专利文献
专利文献1：日本专利第4177571号公报
发明内容
发明所要解决的技术问题
基于以下观点，现有的半导体装置存在以下问题。
虽然现有文献中没有记载，但在半导体装置100实际使用时，会向封装件102所具备的控制端子113安装用于控制功率半导体元件108的控制基板。另外，如上所述，由于该控制基板是用来驱动和保护功率半导体元件108，且它们的布线距离越短，就越能降低电感等，这样在电学上较为有利，因此，将控制基板组装到功率模块的内部的方式已成为主流。
在这种情况下，在将封装件102组装到外壳101内后，将控制基板安装到各封装件102的控制端子113上，使螺钉穿过螺钉孔105从而将半导体装置100进行螺钉止动从而将其固定在散热器上。在现有文献中，因为没有考虑各封装件102的高度偏差，因此，若用螺钉将半导体装置100螺钉止动在散热器上时封装件102的底面高度产生偏差，则在与散热器紧贴时对封装件102产生的反作用力会出现偏差。
现有技术中，也是在各封装件102的背面涂布散热润滑剂，但当例如封装件102的背面比外壳101的背面要突出时，安装时产生的上浮力将相对较大，但如果封装件102的背面比外壳101的背面要低，则散热器与封装件102之间会存在间隙，因此即使有散热润滑剂隔着，所受到的反作用力也会变弱。这种情况下，控制基板已经通过焊锡安装，其高度是固定的，因此，从外壳101的背面突出的封装件102的控制端子113的接合部上会产生过大的应力，有可能因焊锡断裂而导致导通不良。
即，如果各封装件102相对于外壳101的高度出现偏差，则相对于外壳101的底面最向散热器的安装面一侧突出的封装件102将受到最大的反作用力，安装半导体装置100时封装件102的位移量也最大，因此，将在控制端子113的接合部产生最大的应力。
此外，还存在以下问题。
如上所述，通常在将半导体装置100固定到散热器上时，会在底面涂布散热润滑剂来提高接触性。预先涂布一定厚度的散热润滑剂，并通过螺钉固定时的按压力和转矩管理来达到所期望的厚度。但是，如果封装件102的高度有偏差，则如上所述封装件102所受到的应力也会发生变化，因此，存在于各封装件102底面的散热润滑剂的厚度也会有偏差，从而会大大地影响到散热性。例如，散热润滑剂的热传导率为1W/m·℃以下，且使用的厚度为100μm以下。但是，当存在高度偏差的封装件102的散热润滑剂的厚度达到200μm时，从功率半导体元件108到散热器为止的热阻有可能达到2倍以上，此时，若达到额定以上的温度时，功率半导体元件108会发生热损，从而有可能导致动作不良。
近年来，作为功率半导体元件的材料，使用SiC(碳化硅)或GaN(氮化镓)这样的新型材料来代替以往的Si(硅)的功率半导体元件逐渐得到实用。这些新型器件能够在高于现有的工作温度150℃～200℃的温度下进行工作，因此利用简化散热机构后的结构能够实现小型化。即，能够使散热器比以往更小，从而实现整组设备的小型化。
然而，散热器变小对于包含半导体装置100在内的整个结构体来说，会使得散热润滑剂在热阻中所占的比例变大，因此会导致高度偏差带来的影响也变大。由此发现今后对于散热润滑剂的厚度管理会变得越来越重要。
本发明是鉴于上述问题而完成的，其目的在于提供一种能够减小搭载在外壳中的各封装件的热阻偏差、并且能够抑制控制基板与控制端子的接合部上的应力过剩的半导体装置的制造方法及半导体装置。
解决技术问题所采用的技术方案
本发明的权利要求1所记载的半导体装置的制造方法的特征在于，在制造将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置时，将具有与所述功率半导体元件相连接且一端沿着内侧底部引出的第一端子的所述壳体，以其底部的开口部朝下的方式载放到操作台上，将具有与所述功率半导体元件相连接的第二端子的所述封装件，通过所述外壳的所述开口部而载放到所述操作台上，在所述外壳的所述第一端子与所述封装件的所述第二端子之间形成间隙，并在所述间隙中装入接合材料来将所述第一端子与所述第二端子电连接。
本发明的权利要求2所记载的半导体装置的制造方法的特征在于，在制造将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置时，将具有与所述功率半导体元件相连接的第二端子的所述封装件载放到操作台上，使所述第二端子沿着所述操作台延伸，将具有与所述功率半导体元件相连接且一端在内侧沿着深度方向的中间位置引出的第一端子的所述壳体，以其底部的开口部朝下地覆盖所述封装件的方式载放到所述操作台上，在所述外壳的所述第一端子与所述封装件的所述第二端子之间装入接合材料来将所述第一端子与所述第二端子电连接。
本发明的权利要求3所记载的半导体装置的制造方法的特征在于，在制造将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置时，将具有与所述功率半导体元件相连接且一端在内侧沿着深度方向引出的第一端子的所述壳体，以其底部的开口部朝下的方式载放到操作台上，将具有与所述功率半导体元件相连接且向所述外壳的深度方向引出的第二端子的所述封装件，通过所述外壳的所述开口部而载放到所述操作台上，使所述外壳的所述第一端子与所述封装件的所述第二端子相接触并电接合。
本发明的权利要求9所记载的半导体装置是将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置，其特征在于，包括：封装件，该封装件具有与内部所搭载的所述功率半导体元件相连接的第二端子；外壳，该外壳的底部形成有使所述封装件的一部分露出的开口部，且所述外壳具有与所述第二端子相连接且一端沿着内侧底部引出的第一端子；以及接合材料，该接合材料装在所述外壳的所述第一端子与所述封装件的所述第二端子之间沿着所述外壳底部的方向上的间隙中，将所述第一端子与所述封装件的所述第二端子电连接。
本发明的权利要求10所记载的半导体装置是将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部的半导体装置，其特征在于，包括：封装件，该封装件具有与内部所搭载的所述功率半导体元件相连接的第二端子；外壳，该外壳的底部形成有使所述封装件的一部分露出的开口部，且所述外壳具有与所述第二端子相连接且一端在内侧沿着深度方向的中间位置引出的第一端子；以及接合材料，该接合材料装在所述外壳的第一端子与所述封装件的所述第二端子之间沿着所述外壳底部的方向上的间隙中，将所述第一端子与所述封装件的所述第二端子电连接。
本发明的权利要求11所记载的半导体装置是将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部的半导体装置，其特征在于，包括：封装件，该封装件具有与内部所搭载的所述功率半导体元件相连接的第二端子；以及外壳，该外壳的底部形成有使所述封装件的一部分露出的开口部，且所述外壳具有与所述功率半导体元件相连接且一端在内侧沿着深度方向引出的第一端子，并且，所述封装件的所述第二端子沿着所述外壳的所述第一端子在所述深度方向上延伸，并与所述第一端子相接触，且所述第一端子与所述第二端子通过铆接或超声波接合而实现电连接。
发明效果
根据本发明，在载放于操作台上的外壳的第一端子与载放于所述操作台上的封装件的第二端子之间形成间隙，并在平行于所述操作台而形成的所述间隙中装入接合材料，来将第一端子与所述第二端子电连接，从而能够使搭载在外壳中的封装件的底面高度相一致，能够减小各封装件的热阻偏差。而且，能够抑制控制基板安装部上产生过大的应力。
根据本发明，以沿深度方向从外壳引出的第一端子与沿所述深度方向从封装件引出的第二端子相接触的方式，将所述外壳和所述封装件载放到操作台上，相接触的第一端子与第二端子彼此通过铆接或超声波接合而实现电连接，从而，能够使搭载在外壳中的封装件的底面高度相一致，能够减小各封装件的热阻偏差。而且，能够抑制控制基板安装部上产生过大的应力。
附图说明
图1(a)是表示本发明的实施方式1中的半导体装置的剖视图，图1(b)是其俯视图。
图2(a)～(d)是实施方式1中的半导体装置的制造工序图。
图3是实施方式1中的封装件的电路图。
图4(a)是表示实施方式1中的封装件的内部结构的概要图，图4(b)是功率半导体元件的俯视图。
图5是实施方式1中的封装件的剖视图。
图6是本发明的实施方式2中的半导体装置的剖视图。
图7(a)～(d)是实施方式2中的半导体装置的制造工序图。
图8是本发明的实施方式3中的半导体装置的剖视图。
图9(a)～(c)是实施方式3中的半导体装置的制造工序图。
图10(a)是表示现有实施方式中的半导体装置的剖视图，图10(b)是其俯视图。
具体实施方式
下面，基于各实施方式，对本发明的半导体装置的制造方法进行说明。
(实施方式1)
图1(a)(b)是实施方式1中的半导体装置100的剖视图和俯视图。
作为壳体而形成的外壳2中配置有多个封装件6。外壳2是树脂成型的壳体，设有正极端子17、负极端子18和输出端子19。
为了将各封装件6的担当正极和负极的第二端子4与外壳2的正极端子17、负极端子18连接，图1(a)(b)中未图示的正极端子17和负极端子18在外壳2的内部形成分岔的形状。
即，通过使预先钣金加工成所期望形状的端子与树脂同时成型，来形成埋嵌有端子的结构。
封装件6除了具有沿外壳2底部延伸的第二端子4以外，还具有从壳体2底部向深度方向上方折弯的第三端子5。
外壳2的4个角上设有用于和散热器连接的螺钉孔20。本实施方式中，外壳2中形成了3个封装件6并排的结构，但也可以将本发明应用于具有2个以上封装件6的半导体装置。另外，正极端子17、负极端子18、输出端子19的位置关系也不限于本实施例的方式。
图2(a)～图2(d)表示本发明的实施方式1中的半导体装置的制造工序。
首先，如图2(a)所示，将外壳2载放到表面平坦的操作台3上。外壳2呈底部形成有开口部30的矩形框状。外壳2中设有第一端子1，该第一端子1的一端在外壳2底部露出，另一端引出到外壳2的外部。第一端子1可以由Cu或以Cu为主材料的合金形成，也可以在其表面镀金属。由于在功率模块领域中会处理大电流，因此优选使用电阻较小且热传导较好的Cu所占比例较高的材料。此外，外壳2可以和第一端子1一起通过树脂的嵌入成型来形成。此时，树脂使用例如PPS(Poly PhenyleneSulfide Resin：聚苯硫醚树脂)，其耐热性和刚性十分优异，因此是优选的。
操作台3可以由例如经过机械加工的金属制工作台来形成。虽然未图示，但从操作性考虑，优选在操作台3上设置用于对外壳2进行定位的定位机构。
此时，外壳2的底面与操作台3处于大致平行的状态，存在于外壳2与操作台3之间的间隙优选为调整到50μm以下。这是为了在用螺钉固定外壳2时，抑制外壳2的材料即树脂开裂。
接下来，如图2(b)所示，将封装件6载放到在外壳2内侧露出的操作台3上。具体而言，与图10(a)的情况相同，外壳2的尺寸为能够并排地配置多个、这里为3个封装件6的尺寸。
此时，设置在外壳2内侧的3个封装件6的底面与操作台3处于大致平行的状态，各封装件6与操作台3之间即使存在50μm以下的间隙也没有问题。这是因为要安装功率模块的散热器的平坦度被控制在50μm左右，通过使操作台3的平坦度与该散热器的平坦度相匹配，就能够在实际使用时重现与封装件6底面之间的间隙。
第二端子4和第三端子5可以由Cu或以Cu为主材料的合金形成，也可以在其表面镀金属。第三端子5将在后续的工序中安装到控制基板上，因此，考虑到焊锡润湿性，封装件6的外装镀敷优选为镀Sn类合金，例如镀Sn-Bi。此外，膜厚可以在5μm以上。
在该图2(b)所示的状态下，外壳2和各封装件6的底面处于分别与操作台3发生接地的状态，在外壳2的第一端子1与各封装件6的第二端子4之间会产生间隙31。这是因为，通过故意在第一端子1的接合面与第二端子4的接合面之间设置距离，从而各封装件6的底面必定会与操作台3相接触。通过这样的结构，能够高精度地使外壳2的底面与各封装件6的底面对齐。
接着，在图2(c)所示的工序中，用接合材料7将第一端子1与第二端子4电接合。接合材料7可以使用例如焊锡或Ag膏。如图2(b)所说明的，第一端子1与第二端子4之间存在间隙31，因此，可以将接合材料7设置在该间隙31中。在接合材料7使用的是焊锡的情况下，具有以下优点：即，接合时因热空气或激光而造成的局部加热会使焊锡熔融，但由于是液体，因此可以利用毛细管现象使接合材料7均匀地扩散到接合部上。
即，通过故意地将第一端子1与第二端子4分离设置，能够提高接合质量，从而改善操作性。该分离的距离只要在10μm以上就能进行接合，考虑接合可靠性的问题，优选具有100μm左右的厚度。
接着，在图2(d)所示的工序中，使第三端子5插入预先设有通孔的控制基板8，并进行电接合。此时，第三端子5与控制基板8可以由焊锡来接合，但通常可以使用较为实用的Sn-Ag-Cu焊锡。在图2(b)所示的工序中，封装件6底面的高度能够基本达到一致，因此，控制基板8的安装面也能够安装在大致同一高度上。
由此，在本发明的实施方式中，使用同一平面来使外壳2和各封装件6的底面高度对齐，因此，能够使安装到散热器上时封装件6的底面所受到的反作用力相同，并能抑制从各封装件6取出的第三端子5与控制基板8的接合部所受到的应力，从而提高其可靠性。
此外，由于能够使封装件6之间的散热润滑剂厚度均匀，因此，热阻也变得均匀，从而也能够抑制因散热润滑剂的偏差而导致的半导体装置热损。
另外，本发明的实施方式的前提是组装在外壳2内的封装件6的个数为上述的2个以上。关于这一点将进行补充说明。
图3是封装件6内的电路图。封装件6的内部结构并不限于这一方式。
图4(a)(b)是表示本发明的实施方式中的封装件6的内部平面结构的概要图。
封装件6如图3所示那样是2个功率半导体元件9串联的结构，形成具有正极端子、负极端子、输出端子的单相逆变器。如图4(a)所示，功率半导体元件9搭载在引线框10上的2个部位，其中一个形成正极侧电路，另一个形成负极侧电路。还分别设有用于在导通和断开之间切换的栅极。例如通过将具有这样电路结构的3个封装件6组合起来，能够形成三相交流用逆变器电路，从而成为对发动机进行旋转控制的电路。上述用于功率转换用途的功率模块中，形成这样的结构作为一个单元，将2个以上的封装件6组合起来以模块的方式发挥功能。
如图4(a)所示，引线框10上搭载有功率半导体元件9。功率半导体元件9例如为IGBT，这种情况下，同时地搭载有二极管9b。功率半导体元件9通过接合材料(未图示)与引线框10接合。考虑到散热性，接合材料优选使用例如Sn-Ag-Cu类焊锡等金属类的热传导性优异的材料。
如图4(b)所示，功率半导体元件9的正面具有源电极11和栅电极12，并通过Al线13与引线框10的端子接合。这种情况下，功率半导体元件9的漏电极位于元件的背面。另外，由于源电极12中会流过数A～数百A的大电流，因此将多根Al线13接合起来以达到不会熔断的程度。Al线13不一定要是导线形状，也可以是箔状的Al结。
另一方面，栅电极12与源电极11相比，仅仅流过控制用的小电流，因此电极面积也较小，Al线13的形状比源电极11所用的Al线细也无妨。例如，可以使用直径为150μm的Al线13。这些构件都被模塑树脂14密封，只留下引出到外部的第二端子4和第三端子5。模塑树脂14可以使用例如压铸模用的热固化性环氧树脂。
图5示出封装件6的剖视图。
引线框10的下表面设有散热板16，且两者之间隔着绝缘层15。功率半导体元件9所产生的热量通过该散热板16而向外部散热。另外，包括功率半导体元件9的电路最大会产生数百V～超过1000V的电压，但为了在安全上保证散热板16与引线框10电绝缘，使用绝缘层15作为中间层。绝缘层15优选使用同时具有散热性和绝缘性的树脂。为了提高散热性，可以使用氧化铝或氮化硼等热传导优异的填料。
这样，就不会对控制基板8和封装件6的连接部施加过大的应力，且能够减小各封装件6的热阻偏差，从而能够有效地提高半导体装置的可靠性。
本实施方式1中，是在图2(d)所示的工序中将控制基板8安装到第三端子5上，但也可以在将封装件6载放到操作台3上的图2(b)所示的工序中，将第三端子5上已经安装了控制基板8的封装件6载放到操作台3上来进行制造。
(实施方式2)
图6、图7(a)～图7(d)表示本发明的实施方式2。
实施方式1中，封装件6的第二端子4通过接合材料7与外壳2一侧的第一端子1的上表面连接，但在本实施方式2的半导体装置中，封装件6的第二端子4通过接合材料7与外壳2一侧的第一端子1的下表面连接，在这一点上不同于实施方式1。其它都与实施方式1相同。
如图6所示，实施方式2中的外壳2在外壳内侧的深度方向中间形成有隔壁32。隔壁32的中央形成有开口部33。第一端子1的一端设置成在外壳2的隔壁32的下表面露出。第二端子4位于比第一端子1更靠近散热器的安装面一侧，即第二端子4位于第一端子1的下方。
图7(a)～图7(d)表示制造工序。
首先，在图7(a)所示，将封装件6放置到操作台3上，并且在第二端子4的上表面涂布作为接合材料7的焊膏等。
接着，如图7(b)所示，将外壳2载放到操作台3上，并将外壳2设置在封装件6上方。从而，在封装件6的第二端子4上，外壳2的第一端子1隔着接合材料7与之接触。
在图7(c)中，使封装件6的第三端子5插入预先设有通孔的控制基板8，并进行电接合。此时，第三端子5与控制基板8可以由焊锡来接合，但通常可以使用较为实用的Sn-Ag-Cu焊锡。
在图7(d)中，进行加热并冷却，用接合材料7将第一端子1与第二端子4焊接接合，从而完成半导体装置100。
这样，在图7(b)所示的工序中，能够使外壳2与封装件6的底面对齐。并且，能够使封装件6底面的高度基本达到一致，因此，控制基板8的安装面也能够安装在大致同一高度上。因而，不会对控制基板8和封装件6的连接部施加过大的应力，且能够减小各封装件6的热阻偏差，从而能够有效地提高半导体装置的可靠性。
本实施方式2中，是在图7(c)所示的工序中将控制基板8安装到第三端子5上，但在控制基板8的宽度W2比外壳2的隔壁32上所形成的开口部33的宽度W1要窄时，也可以在图7(a)所示的工序中，将第三端子5上已经安装了控制基板8的封装件6载放到操作台3上来进行制造。
(实施方式3)
图8、图9(a)～图9(c)表示本发明的实施方式3。
实施方式1、2中，在平行于外壳2底面而延伸的第一端子1与平行于封装件6底面而延伸的第二端子4之间形成间隙31而使两者分开，从而使第一端子1和第二端子4不会在制造过程中发生接触，但在本实施方式3中，通过在垂直于各个底面的方向上变更第一端子1和第二端子4的方向，即使第一端子1与第二端子4直接接触，也能够使外壳2与封装件6的底面对齐。其它都与实施方式1、2相同。
如图8所示，第一端子1的一端在外壳2的内侧露出，并且沿着外壳2的深度方向向上方折弯。第一端子1的另一端穿过外壳2而引出到外部。从封装件6水平引出的第二端子4的前端沿着外壳2的深度方向向上方折弯，并与第一端子1发生面接触。相互面接触的第一端子1和第二端子4例如通过直接铆接或者超声波接合来实现电连接。
从封装件6引出且沿着外壳2的深度方向向上方折弯的第三端子5插入预先设有通孔的控制基板8，并用焊锡接合。
图9(a)～图9(c)表示制造工序。
首先，如图9(a)所示，将外壳2载放到操作台3上。
接下来，如图9(b)所示，将封装体6载放到在外壳2内侧的操作台3上。相互面接触的第一端子1和第二端子4例如通过直接铆接或者超声波接合来实现电连接。
第一端子1与第二端子4、第三端子5都向同一方向取出。即，这些端子设置在垂直于外壳2底面及封装件6的背面的垂直方向上。
在图9(c)中，使第三端子5插入控制基板8，并进行焊接。
在这样的结构下，无需像实施方式1、2那样使第一端子1与第二端子4分离。即，实施方式1、2中，为了使外壳2与封装件6的底面对齐，使平行于各自底面而延伸的第一端子1和第二端子4分离而不接触，但在本实施方式3中，通过在垂直于底面的垂直方向上变更各个端子的方向，即使第一端子1与第二端子4发生接触，也能使外壳2与封装件6的底面对齐。
另外，虽然是在外壳2的内侧插入封装件6，但也可以先在操作台3上载放封装件6，然后使外壳2覆盖封装件6的外侧来制造。
本实施方式3中，向着外壳2的上方引出第一端子1，封装件6的第二端子4也沿着第一端子1向外壳2的上方折弯，但也可以向着外壳2的下方引出第一端子1，封装件6的第二端子4也沿着第一端子1向外壳2的下方折弯，由此来制造半导体装置。将第一端子1和第二端子4彼此铆接或者超声波接合来实现接合的操作如图8所示，第一端子1、第二端子4向外壳2的上方折弯时的操作性更好。
尤其是在不矛盾的点上，在能获得以下效果这一点上是相同的：即，可以同时实施本实施方式1～3。这种情况下，也是使用操作台的同一平面来放置外壳和封装件，因此，通过使搭载在外壳中的封装件的底面高度一致，能够抑制施加在控制基板8上的过大应力，能够使各封装件之间在安装到散热器上时使用的散热润滑剂的厚度一致，从而能够抑制热阻的偏差。
工业上的实用性
本发明有利于实现逆变器等功率转换用途中使用的半导体装置的高性能化。
标号说明
1  第一端子
2  外壳
3  操作台
4  第二端子
5  第三端子
6  封装件
7  接合材料
8  控制基板
9  功率半导体元件
10 引线框
11 源电极
12 栅电极
13 Al线
14 模塑树脂
15 绝缘层
16 散热板
17 正极端子
18 负极端子
19 输出端子
20 螺钉孔
30 外壳底部的开口部
31 外壳的第一端子与封装件的第二端子之间的间隙
32 外壳内侧的深度方向中央形成的隔壁
33 隔壁中央的开口部

Claims (12)

1.一种半导体装置的制造方法，其特征在于，
在制造将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置时，
将具有第一端子的所述外壳以其底部的开口部朝下的方式载放到操作台上，其中，所述第一端子与所述功率半导体元件相连接，所述第一端子的一端沿着内侧底部引出，
将具有第二端子的所述封装件通过所述外壳的所述开口部而载放到所述操作台上，并在所述外壳的所述第一端子与所述封装件的所述第二端子之间形成间隙，其中，所述第二端子与所述功率半导体元件相连接，
在所述间隙中装入接合材料，将所述第一端子与所述第二端子电连接。
2.一种半导体装置的制造方法，其特征在于，
在制造将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置时，
将具有与所述功率半导体元件相连接的第二端子的所述封装件载放到操作台上，使所述第二端子沿着所述操作台延伸，
将具有第一端子的所述外壳以其底部的开口部朝下地覆盖所述封装件的方式载放到所述操作台上，并在所述外壳的所述第一端子与所述封装件的所述第二端子之间装入接合材料来将所述第一端子与所述第二端子电连接，其中，所述第一端子与所述功率半导体元件相连接，所述第一端子的一端在内侧沿着深度方向的中间位置引出。
3.一种半导体装置的制造方法，其特征在于，
在制造将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部而形成的半导体装置时，
将具有第一端子的所述外壳以其底部的开口部朝下的方式载放到操作台上，其中，所述第一端子与所述功率半导体元件相连接，所述第一端子的一端在内侧沿着深度方向引出，
将具有第二端子的所述封装件通过所述外壳的所述开口部而载放到所述操作台上，并使所述外壳的所述第一端子与所述封装件的所述第二端子相接触并电接合，其中，所述第二端子与所述功率半导体元件相连接并沿着所述外壳的深度方向引出。
4.如权利要求1或2所述的半导体装置的制造方法，其特征在于，
通过使作为接合材料的Sn类焊锡加热熔融来将所述第一端子与所述第二端子相接合。
5.如权利要求1或2所述的半导体装置的制造方法，其特征在于，
对所述第二端子实施以Sn为主要成分的镀敷。
6.如权利要求3所述的半导体装置的制造方法，其特征在于，
通过铆接或超声波接合来将所述第一端子与所述第二端子相接合。
7.如权利要求1至3的任一项所述的半导体装置的制造方法，其特征在于，
所述封装件设有沿着所述外壳的深度方向向远离所述操作台的方向引出的第三端子，在将所述封装件载放到所述操作台上之前或之后，将构建有向所述功率半导体元件输出驱动信号的电路的控制基板与第三端子电连接。
8.如权利要求1至3的任一项所述的半导体装置的制造方法，其特征在于，
所述第一端子、所述第二端子都由Cu或Cu合金形成。
9.一种半导体装置，该半导体装置将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部，其特征在于，包括：
封装件，该封装件具有与内部所搭载的所述功率半导体元件相连接的第二端子；
外壳，该外壳的底部形成有使所述封装件的一部分露出的开口部，且该外壳具有第一端子，其中，所述第一端子与所述第二端子相连接，所述第一端子的一端沿着内侧底部引出；以及
接合材料，该接合材料装在所述外壳的所述第一端子与所述封装件的所述第二端子之间的沿所述外壳底部的方向上的间隙中，将所述第一端子与所述封装件的所述第二端子电连接。
10.一种半导体装置，该半导体装置将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部，其特征在于，包括：
封装件，该封装件具有与内部所搭载的所述功率半导体元件相连接的第二端子；
外壳，该外壳的底部形成有使所述封装件的一部分露出的开口部，且该外壳具有第一端子，其中，所述第一端子与所述第二端子相连接，所述第一端子的一端在内侧沿着深度方向的中间位置引出；以及
接合材料，该接合材料装在所述外壳的第一端子与所述封装件的所述第二端子之间的沿所述外壳底部的方向上的间隙中，将所述第一端子与所述封装件的所述第二端子电连接。
11.一种半导体装置，该半导体装置将内部搭载有功率半导体元件的多个封装件配置于树脂成型的外壳内部，其特征在于，包括：
封装件，该封装件具有与内部所搭载的所述功率半导体元件相连接的第二端子；以及
外壳，该外壳的底部形成有使所述封装件的一部分露出的开口部，且该外壳具有第一端子，其中，所述第一端子与所述功率半导体元件相连接，所述第一端子的一端在内侧沿着深度方向引出，
并且，所述封装件的所述第二端子沿着所述外壳的所述第一端子在所述深度方向上延伸而与所述第一端子相接触，并且所述第一端子和所述第二端子通过铆接或超声波接合而实现电连接。
12.如权利要求9至11的任一项所述的半导体装置，其特征在于，
所述封装件设有沿着所述外壳的深度方向向远离所述操作台的方向引出的第三端子，所述第三端子与构建有向所述功率半导体元件输出驱动信号的电路的控制基板电连接。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110168721A (zh) * 2017-01-16 2019-08-23 三菱电机株式会社 半导体装置
CN110998832A (zh) * 2017-07-28 2020-04-10 三菱电机株式会社 半导体装置以及半导体模块
WO2021230294A1 (ja) * 2020-05-14 2021-11-18 ヌヴォトンテクノロジージャパン株式会社 光源モジュール

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102153041B1 (ko) * 2013-12-04 2020-09-07 삼성전자주식회사 반도체소자 패키지 및 그 제조방법
JP6093455B2 (ja) * 2014-01-27 2017-03-08 株式会社日立製作所 半導体モジュール
JP6246051B2 (ja) * 2014-04-17 2017-12-13 三菱電機株式会社 電力半導体装置およびその製造方法
EP3349572A4 (en) * 2015-09-15 2019-08-14 Once Innovations, Inc. ACTIVATION OF BIOLOGICAL RESPONSES IN INCUBATED EGGS
JP6800121B2 (ja) * 2017-09-21 2020-12-16 三菱電機株式会社 半導体装置および電力変換装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204400A (ja) * 1992-12-28 1994-07-22 Mitsubishi Electric Corp 半導体モジュール
CN1219767A (zh) * 1997-12-08 1999-06-16 东芝株式会社 半导体功率器件的封装及其组装方法
JP2002076258A (ja) * 2000-08-25 2002-03-15 Mitsubishi Electric Corp 半導体装置
US6421244B1 (en) * 1999-12-28 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Power module

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54107257A (en) 1978-02-09 1979-08-22 Fujitsu Ltd Semiconductor device mounting method
JPH1084079A (ja) 1996-09-09 1998-03-31 Matsushita Electric Ind Co Ltd 半導体装置
JP3758383B2 (ja) * 1998-10-23 2006-03-22 富士電機デバイステクノロジー株式会社 パワー半導体装置およびその組立方法
JP4177571B2 (ja) 2001-09-20 2008-11-05 三菱電機株式会社 半導体装置
JP2005217072A (ja) 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
JP5064107B2 (ja) 2007-05-09 2012-10-31 昭和シェル石油株式会社 電子部品モジュール又はｃｉｓ系薄膜太陽電池モジュールのリボンワイヤの接続方法
JP2009099339A (ja) 2007-10-16 2009-05-07 Mitsubishi Electric Corp 電子機器の配線接続構造及び方法
JP2011103367A (ja) 2009-11-11 2011-05-26 Mitsubishi Electric Corp 電力用半導体装置
JP5213919B2 (ja) 2010-06-17 2013-06-19 三菱電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204400A (ja) * 1992-12-28 1994-07-22 Mitsubishi Electric Corp 半導体モジュール
CN1219767A (zh) * 1997-12-08 1999-06-16 东芝株式会社 半导体功率器件的封装及其组装方法
US6421244B1 (en) * 1999-12-28 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Power module
JP2002076258A (ja) * 2000-08-25 2002-03-15 Mitsubishi Electric Corp 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110168721A (zh) * 2017-01-16 2019-08-23 三菱电机株式会社 半导体装置
CN110168721B (zh) * 2017-01-16 2022-12-27 三菱电机株式会社 半导体装置以及半导体装置的制造方法
CN110998832A (zh) * 2017-07-28 2020-04-10 三菱电机株式会社 半导体装置以及半导体模块
CN110998832B (zh) * 2017-07-28 2023-10-13 三菱电机株式会社 半导体装置以及半导体模块
WO2021230294A1 (ja) * 2020-05-14 2021-11-18 ヌヴォトンテクノロジージャパン株式会社 光源モジュール

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