TWI697058B - 具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體 - Google Patents

具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體 Download PDF

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TWI697058B
TWI697058B TW105110137A TW105110137A TWI697058B TW I697058 B TWI697058 B TW I697058B TW 105110137 A TW105110137 A TW 105110137A TW 105110137 A TW105110137 A TW 105110137A TW I697058 B TWI697058 B TW I697058B
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copper plate
circuit
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胡志良
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胡志良
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Abstract

製作具良好散熱性及高電功率之電路元件封裝體之封裝方法，其包含以下步驟：於一第一銅板上形成陣列排序的銅質線路，並於選定位置以機械鑽孔方式形成陣列式的導通孔；於一第二銅板上形成複數個排列有序的銅質線路，再於設定位置上印刷導電膠；於其一導電膠上定置該電路元件之電路核心。接著就前述已完成導電膠印刷之銅板結構，進行定位對準程序，完成兩銅板結構與電路核心之定位對準。其後取適確尺寸之銅柱，插置於已開設之導通孔完成兩銅板結構連結，經高溫處理後，即完成電路核心與兩銅板結構的電性導接。於套合後之兩製程銅板結構注入氣密隔絕材料，再以蝕刻銅板製程加工兩製程銅板外端結構，以完成兩銅板之外部銅質線路，以及其後經上、下合模施工步驟，施注氣密隔絕封裝材料，且經烘烤固化後，進行切割以分離個別電路元件而形成該封裝體。

Description

具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體
本發明係有關於半導體電路元件之封裝體及其封裝方法，特別是訴求於有功率要求，講求熱散效應的表面黏著元件封裝方法及封裝體。本發明更係有關於具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體。
目前諸如二極體、發光二極體、電晶體及閘流體等離散式電路元件的表面黏著型(Surface Mount)構裝，大致有1，圓柱型玻璃/塑膠封裝；2，導線架(Lead-frame)有引腳封裝(Leaded package)；3，方形無引腳的平板式封裝(Flat-pack leadless)；以及4，覆晶(Flit-chip)封裝等數種常見型態。
其中覆晶封裝雖有輕、薄、短、小等特點，但因製程昂貴，客戶使用不便及零件老化、壽命測試不佳諸缺點，故其商業性上客戶甚少直接使用在訴求於功率及講求較佳老化壽命應用上。相較之下，前述三者是為目前功率型封裝體之市場主流。但隨著電性要求越高，功率增大，熱傳及高溫所造成元件本質問題，此三種封裝製程技術亦已趨於現有技術之臨界。此外，隨著環保要求，封裝製程、封裝材料的限制亦是有待克服的成本及技術。
因此，即便此等三種有無接腳之離散式元件應用於印刷電路板上之表面黏著(surface mount technology)所必需取置(Pick and place)自動化技術，目前並無技術問題，但此類離散式元件製程之良率，自動化及 成本問題，已成為當下業者主要課題，但相對於元件封裝之功率提升，熱傳改善，更是其瓶頸及欲解決首要課題。
本發明之一目的在於簡化離散式電路元件之製作且同時提升元件電氣(電流、功率及老化等諸特性)及機械性、散熱性。
本發明之另一目的在於簡化離散式電路元件封裝製程，從而減少加工程序且提高自動化程度，製程良率而達成本降低目的。
本發明之另一目的在於簡化離散式電路元件製作所需使用的材料種類，使之符合RoHS(Restriction of Hazardous Substances Directive)Halgon Free、WEEE(Waste Electrical and Electronic Equipment Directive)等環保法規，更著重熱導材料選用及共晶結合的電氣，電熱效應，使元件具有高品質及最佳化之壽命品質。
製作具良好散熱性及高電功率之電路元件封裝體之封裝方法，其包含以下步驟：於一第一銅板上形成陣列排序的銅質線路，並於選定位置以機械鑽孔方式形成陣列式的導通孔；於一第二銅板上形成複數個排列有序的銅質線路，再於設定位置上印刷導電膠；於其一導電膠上定置該電路元件之電路核心。接著就前述已完成導電膠印刷之銅板結構，進行定位對準程序，完成兩銅板結構與電路核心之定位對準。其後取適確尺寸之銅柱，插置於已開設之導通孔完成兩銅板結構連結，經高溫處理後，即完成電路核心與兩銅板結構的電性導接。於套合後之兩製程銅板結構注入氣密隔絕材料，再以蝕刻銅板製程加工兩製程銅板外端結構，以完成兩銅板之外部銅質線路，以及其後經上、下合模施工步驟，施注氣密隔絕封裝材料，且經烘烤固化後，進行切割以分離個別電路元件而形成該封裝體。
˙110‧‧‧製程階段第一銅板結構
˙220‧‧‧製程階段第二銅板結構
˙111‧‧‧第一銅板
˙221‧‧‧第二銅板
˙112,222,701,702‧‧‧銅質線路
˙223‧‧‧消蝕減去之銅塊
˙113‧‧‧導通孔
˙301,703‧‧‧電路元件核心
˙302,704‧‧‧銅柱
˙303,706‧‧‧導電膠
˙304,501,502,705,709,710‧‧‧氣密隔絕封裝材料
˙401,402,403,707,708‧‧‧凸出銅塊
˙601,602,711,712,713,714‧‧‧端電極
˙600,700‧‧‧封裝體成品
˙802‧‧‧銅線路塊
圖1-1顯示本發明實施例之一製程銅板結構之上視圖，圖1-2 顯示此銅板結構沿aa’之截面圖。
圖1-3顯示圖1-1製程銅板結構之透視圖。
圖1-4顯示圖1-2結構之透視圖。
圖2-1及2-2分別顯示本發明實施例之另一製程銅板結構其上視圖及截面圖。
圖3顯示兩製程銅板結構與電路核心定位套合且注入氣密隔絕封裝材料後之截面圖。
圖4顯示於插入銅柱後，並完成兩製程銅板結構之外端銅質線路之截面圖。
圖5顯示完成兩外端銅質線路之氣密隔絕封裝保護之截面圖。
圖6-1、6-2分別顯示單一電路元件封裝體分離後之成品橫向截面圖與其外觀端電極圖。
圖7-1、7-2分別顯示適用於本發明之電路連結二個電路核心元件構裝成品截面圖及外觀端電極圖。
圖8顯示依據本發明具堅實導電及導熱性銅質線路之電路元件封裝方法所製作封裝體之另一較佳實施例。
依據本發明一較佳實施例，如圖1-1所示，可於此製程階段之一第一銅板111上，利用蝕刻、電鍍、或化鍍等方式製成陣列排序的銅質線路112。其後再以蝕刻或機械鑽孔，於銅質線路112上選定位置形成導通孔113。圖1-2所示即為此製程階段第一銅板結構110沿aa’線所截取之橫截面圖。
圖2-1及2-2分別顯示本發明實施例之一第二銅板221，其上視圖及截面圖。圖2-1及2-2之製程階段第二銅板結構220，可以利用減去法(subtractive)之作法，先取一適當厚度第二銅板221，利用表面蝕刻等方式， 消蝕減去圖2-2中參考標號223所標示部份之銅質材料而形成。另種作法則可應用增加法(additive)之作法，利用諸如表面鍍銅增厚等方式，形成銅質線路222。兩者皆可製作成一圖2-1及2-2所示，依陣列排序之銅質線路222。
例如，圖1-3顯示圖1-1製程銅板結構之透視圖，圖1-4則顯示圖1-2結構之透視圖。注意到圖1-2及1-4中清楚顯示，圖中作為製作基礎的第一銅板111，其上左側之銅質線路112係利用諸如電鍍之加法製程所形成，此可由上部銅質線路112與其下之第一銅板111之間的接面得知。另一方面，圖中右側之銅質線路112係利用諸如蝕刻之減法製程所形成(即圖2-2中所消除掉之銅塊223)，此可由上部銅質線路112與其下之第一銅板111之間的整體連結構造而得知。
其後，如圖3顯示，取前述製程銅板結構110、220，先於其銅質線路112、222之預設位置，利用點膠或印刷方式完成適量導電膠303佈施。適用之導電膠可為錫、鉛膠亦可為銀、鋁、銻、金、鎳、銅、鉍或其合金等導電膠。其後可進行固晶步驟，利用自動取置(pick and place)程序，將電路核心301依序排列定置於製程第二銅板結構220之導電膠303上。接著取前已印刷完成導電膠303之第一銅板結構110，進行定位對準程序，置於前述已完成電路核心固晶之製程第二銅板結構220上。其後，取適確尺寸之銅柱302，插置進入製程第一銅板結構110上已開設之導通孔113內，並插入至與製程第二銅板結構220之第二銅板221接觸為止。
注意到圖1-1至1-4中所顯示之導通孔113具有圓形之橫截面，但其他形狀，例如矩形、梯形等之多邊形橫截面亦可適用。
如上所述進行定位套合並插入銅柱後，整個結構可利用焊接爐或高溫烘烤製程，而可以完成電路核心301上下兩端之電性導接。亦可依序先完成電路核心301與製程階段第一銅板結構110之電性導接再與製程階段第二銅板結構220定位套合後插入302銅柱再經高溫處理導接。亦即，兩製程階段銅板結構110、220，銅柱302與電路核心301其間可以完成電性導通。接著在第一銅板結構110與第二銅板結構220間注入流體態之氣密隔絕 封裝材料304(如矽化物、氧化物、玻璃、環氧樹脂、2-聚亞醯胺等絕緣性材料)，並經高溫烘烤製程使氣密隔絕材料304固化(curing)，即形成電路核心301四周的氣密絕緣保護。
接著，如圖4所示，可於圖3之銅板結構110、220外露之上下銅面上施以感光乳膠被覆，再經曝光、顯影、蝕刻、清洗等步驟，而後得到獨立之凸出銅塊401、402與403。圖4即顯示本發明此時已完成套合，注入氣密隔絕封裝材料並固化，再經蝕刻處理，形成有分別獨立之凸出銅塊401、402與403之橫截剖面圖。
圖4之中已完成電路核心301電性導接及四周氣密絕緣保護之平板結構，如圖5所示，接著再以上、下合模的施工步驟，施注氣密隔絕封裝材料(如矽化物、氧化物、玻璃、環氧樹脂、2-聚亞醯胺等絕緣性材料)，經高溫烘烤製程即形成氣密隔絕
Figure 105110137-A0305-02-0007-1
封裝材料501、502絕緣保護。其後可沿bb’線，以鑽石刀或鐳射刀、線切割等方式進行切割，以使每一電路元件分離開來。此時即可獲得分離的元件，其橫向截面構造如圖5所示。
分散開來的電路元件再經過滾鍍處理，完成外端電極的包覆，其包覆成分可包含鎳、錫、鉛、銀、金、銅、鋁、鉑等金屬或其合金，圖6-1即顯示此等元件封裝體600的橫向截面圖，圖6-2則為由底端所見之端電極圖。
因此，圖6-1、6-2即顯示適用於本發明封裝電路元件製作方法所製作電路元件之一較佳實施例。本發明此種高散熱效率，高電功率之電路元件可以具有上、下電極之二極體晶粒作為電路核心。如同習於本技藝者所可以理解，以上說明文字所列舉描述之本發明個別離散式電路元件封裝體，其電路元件核心當然不限於二極體。其他諸如發光二極體、電晶體或閘流體等，本發明同樣亦可適用。此外，本說明所附圖式中各式視圖亦未以精確相對尺寸比例繪示。為了說明，其中某些尺度可能有所放大。
圖7-1及7-2分別顯示適用於本發明之電路連結二個電路核心元件構裝製作方法及成品構造之截面圖及其外觀端電極圖。此封裝體700 與前述封裝體600不同之處，僅是其所封裝之電路核心301由單個具上下正負極(圖6，封裝體600)被置換為具有數個相連電路核心703。封裝體700外觀端電極711、712、713、714係如圖7-2所示。
圖8顯示依據本發明具堅實導電及導熱性銅質線路之電路元件封裝方法所製作封裝體之另一較佳實施例。注意到相較於本說明書中前述使用銅柱而將電路元件核心之上電極電性導接之元件底部(右側)獨立銅塊而構成元件電極之各實施例，圖8之橫截面圖顯示，其銅柱已被銅線路塊802所取代。本發明圖8封裝體之製作係將此銅線路塊802當作與電路元件301一樣而進行製程處理。此不但可以免除導通孔(圖1-1至1-4中導通孔113)之製作，亦可增加整體製程效率，降低成本，並增進元件內部電路核心301之導電及導熱性能。
此外，圖8中之銅線路塊802可以具有各種適合之橫截面形狀。例如，圓柱形或矩形之銅線路塊802皆可適用。
雖然本發明已經由較佳實例揭示說明如上，然以上說明並非用以限定本發明。在不脫離於本發明精神之情況下，任何熟悉此項技藝者當可作些許更動與變化。例如，本說明所描述之實施例中，第一或第二銅板結構110、220，或兩者，可直接以一般之導線架基底來取代。因此本發明之保護範圍當視後附之申請範圍所界定者為準。
112,222‧‧‧銅質線路
301‧‧‧電路元件核心
302‧‧‧銅柱
303‧‧‧導電膠
304,501,502‧‧‧氣密隔絕封裝材料
401,402,403‧‧‧凸出銅塊
600‧‧‧封裝體成品
601,602‧‧‧端電極

Claims (1)

  1. 製作具良好散熱性及高電功率之電路元件封裝體之封裝方法，其包含以下步驟：於一第一銅板上形成陣列排序的銅質線路，並於選定位置以機械鑽孔方式形成陣列式的導通孔；於一第二銅板上形成複數個排列有序的銅質線路，再於設定位置上印刷導電膠；於其一導電膠上定置該電路元件之電路核心；接著就前述已完成導電膠印刷之銅板結構，進行定位對準程序，完成兩銅板結構與電路核心之定位對準；其後取適確尺寸之銅柱，插置於已開設之導通孔完成兩銅板結構連結，經高溫處理後，即完成電路核心與兩銅板結構的電性導接；於套合後之兩製程銅板結構注入氣密隔絕材料，再以蝕刻銅板製程加工兩製程銅板外端結構，以完成兩銅板之外部銅質線路；以及其後經上、下合模施工步驟，施注氣密隔絕封裝材料，且經烘烤固化後，進行切割以分離個別電路元件而形成該封裝體。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI697058B (zh) * 2016-03-30 2020-06-21 胡志良 具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體
US11521862B2 (en) * 2017-12-15 2022-12-06 Chih-Liang Hu Process for fabricating circuit components in matrix batches
WO2023137714A1 (zh) * 2022-01-21 2023-07-27 佛山市柔浩电子有限公司 一种微型led芯片及其制备方法和包含其的共晶结构
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201225122A (en) * 2010-12-01 2012-06-16 Holy Stone Entpr Co Ltd Ceramic capacitor structure
CN103515364A (zh) * 2012-06-29 2014-01-15 三星电机株式会社 电源模块封装和用于制造电源模块封装的方法
TW201442159A (zh) * 2013-04-16 2014-11-01 Chih-Liang Hu 離散式電路元件之微型封裝
TW201532487A (zh) * 2014-02-05 2015-08-16 Chih-Liang Hu 高效能封裝體及其封裝方法
US20160027711A1 (en) * 2013-10-03 2016-01-28 Fuji Electric Co., Ltd. Semiconductor module

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7632747B2 (en) * 2004-08-19 2009-12-15 Micron Technology, Inc. Conductive structures for microfeature devices and methods for fabricating microfeature devices
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US8314483B2 (en) * 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
JP5778557B2 (ja) * 2011-11-28 2015-09-16 新光電気工業株式会社 半導体装置の製造方法、半導体装置、及び半導体素子
US8642384B2 (en) * 2012-03-09 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
US20140167237A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power module package
US9130016B2 (en) * 2013-04-15 2015-09-08 Schott Corporation Method of manufacturing through-glass vias
US9515047B2 (en) * 2015-03-10 2016-12-06 Chih-Liang Hu High performance package and process for making
KR102543528B1 (ko) * 2015-12-07 2023-06-15 현대모비스 주식회사 전력 모듈 패키지 및 그 제조방법
US10049896B2 (en) * 2015-12-09 2018-08-14 International Business Machines Corporation Lid attach optimization to limit electronic package warpage
US10014280B2 (en) * 2016-03-29 2018-07-03 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Three dimensional fully molded power electronics module having a plurality of spacers for high power applications
TWI697058B (zh) * 2016-03-30 2020-06-21 胡志良 具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體
KR102508945B1 (ko) * 2016-04-19 2023-03-09 현대모비스 주식회사 양방향 반도체 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201225122A (en) * 2010-12-01 2012-06-16 Holy Stone Entpr Co Ltd Ceramic capacitor structure
CN103515364A (zh) * 2012-06-29 2014-01-15 三星电机株式会社 电源模块封装和用于制造电源模块封装的方法
TW201442159A (zh) * 2013-04-16 2014-11-01 Chih-Liang Hu 離散式電路元件之微型封裝
US20160027711A1 (en) * 2013-10-03 2016-01-28 Fuji Electric Co., Ltd. Semiconductor module
TW201532487A (zh) * 2014-02-05 2015-08-16 Chih-Liang Hu 高效能封裝體及其封裝方法

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