JP2007019215A - 半導体装置及びその製法 - Google Patents

半導体装置及びその製法 Download PDF

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Publication number
JP2007019215A
JP2007019215A JP2005198447A JP2005198447A JP2007019215A JP 2007019215 A JP2007019215 A JP 2007019215A JP 2005198447 A JP2005198447 A JP 2005198447A JP 2005198447 A JP2005198447 A JP 2005198447A JP 2007019215 A JP2007019215 A JP 2007019215A
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Prior art keywords
electrode layer
igbt
region
semiconductor element
lower electrode
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JP2005198447A
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English (en)
Inventor
Katsuyuki Torii
克行 鳥居
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2005198447A priority Critical patent/JP2007019215A/ja
Priority to US11/994,514 priority patent/US7847316B2/en
Priority to EP06729669A priority patent/EP1906452B1/en
Priority to CN2006800010134A priority patent/CN101040386B/zh
Priority to PCT/JP2006/305702 priority patent/WO2007007445A1/ja
Publication of JP2007019215A publication Critical patent/JP2007019215A/ja
Pending legal-status Critical Current

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Abstract

【課題】下部ＩＧＢＴと上部ＩＧＢＴとを半田により良好に固着すると共に、下部ＩＧＢＴとワイヤとを強固に接続して、信頼性の高い半導体装置を形成する。
【解決手段】下部ＩＧＢＴ(1)に固着された下部電極層(5)と、下部電極層(5)に固着された上部電極層(6)と、上部電極層(6)に固着された上部ＩＧＢＴ(2)と、上部電極層(6)と上部ＩＧＢＴ(2)とを接続する半田(7)とを備える。下部電極層(5)と上部電極層(6)とを異なる材質により形成し、上部電極層(6)に設けた切欠部(36)から外部に部分的に露出する結線領域(15)を下部電極層(5)の上面(5a)に設け、結線領域(15)にワイヤ(8)を接続する。上部電極層(6)を半田付け性に優れた材質により形成し、下部電極層(5)をワイヤ(8)との接続強度の高い材質により形成することができる。
【選択図】図１

Description

本発明は、半導体装置、特に複数の半導体素子を積重して小型化できる半導体装置に関する。
金属製の支持板と、支持板上に順次積層された第１のトランジスタ及び第２のトランジスタと、支持板上に順次積層された第３のトランジスタ及び第４のトランジスタと、第１のトランジスタ及び第２のトランジスタと第３のトランジスタ及び第４のトランジスタとの間で支持板上に固着された制御回路（制御ＩＣ）とを備え、第１のトランジスタ及び第２のトランジスタと、第３のトランジスタ及び第４のトランジスタとにより、Ｈ型ブリッジ回路を構成する半導体装置は、下記特許文献１により公知である。特許文献１によれば、第１のトランジスタと第２のトランジスタとを積重すると共に、第３のトランジスタと第４のトランジスタとを積重することにより、支持板の占有面積を減少しつつ集積度を向上することができる。
また、特許文献１の半導体装置では、第１のトランジスタ及び第３のトランジスタの上面に形成された上面電極と第２のトランジスタ及び第４のトランジスタの下面に形成された下面電極とを半田により固着すると共に、第１のトランジスタ及び第３のトランジスタの上面に形成された上面電極と制御回路の上面電極及び支持板の周囲に配置された複数の外部リードとをワイヤにより接続している。第１のトランジスタと第２のトランジスタ及び第３のトランジスタと第４のトランジスタとを半田により電気的に互いに接続するので、電流の結線経路を短縮して、電流の結線経路の延長によるノイズ発生及び電力損失を抑制することができる。また、ワイヤ結線を簡素化できる。
国際公開第２００５／０１８００１号公報
しかしながら、下方に配置される第１のトランジスタ及び第３のトランジスタの上面電極は、第２のトランジスタ及び第４のトランジスタの下面電極との半田による接続に適した金属又はワイヤとの接続に適した金属の何れかにより形成されていた。半田付け性に優れたニッケル又は銅等の金属から成る電極は、アルミニウム又は金等の金属から成るワイヤとの接続性が劣っている。また、ワイヤとの接続強度が高いアルミニウム等の金属から成る電極は、鉛又は錫等の金属から成る半田との接続性（半田濡れ性）が劣っている。このため、上記特許文献１の半導体装置では、半田付け強度とワイヤ接続強度の両方が高く得られる半導体装置を実現することが困難であった。
よって、本発明は、ワイヤ及び半田との接続性の高い電極を有する半導体装置を提供することを目的とする。
本発明の半導体装置は、下部半導体素子(1)と、下部半導体素子(1)の上面(1a)に形成された下部電極層(5)と、下部電極層(5)の上面(5a)に形成された上部電極層(6)と、上部電極層(6)の上面(6a)に固着された上部半導体素子(2)と、上部電極層(6)と上部半導体素子(2)とを固着する接着剤層(7)とを備えている。下部電極層(5)の上面(5a)と上部電極層(6)の上面(6a)とを異なる材質により形成し、上部電極層(6)から外部に部分的に露出する結線領域(15)を下部電極層(5)の上面(5a)に設け、結線領域(15)にリード細線(8)の端部を接続する。
本発明の半導体装置の製法は、下部半導体素子(1)の上面(1a)に下部電極層(5)を形成する工程と、下部電極層(5)の上面(5a)とは異なる材質により成る上面(6a)を有する上部電極層(6)を下部電極層(5)の上面(5a)に形成する工程と、上部電極層(6)に切欠部(36)を設けて切欠部(36)を通じて外部に部分的に露出する結線領域(15)を下部電極層(5)の上面(5a)に形成する工程と、接着剤(7)により上部電極層(6)の上面(6a)に上部半導体素子(2)を固着する工程と、結線領域(15)にリード細線(8)の端部を接続する工程とを含む。
下部半導体素子(1)と上部半導体素子(2)との間に設けられる下部電極層(5)の上面(5a)と上部電極層(6)の上面(6a)を異なる材質により形成するので、上部電極層(6)の上面(6a)を半田付け性に優れた材質により形成し、下部電極層(5)の上面(5a)をリード細線(8)との接続強度の高い材質により形成できる。このため、下部半導体素子(1)と上部半導体素子(2)とを半田等から成る接着剤層(7)により良好に固着すると共に、下部半導体素子(1)とリード細線(8)とを強固に接続して、信頼性の高い半導体装置を形成することができる。
本発明によれば、上部半導体素子と下部半導体素子との半田付け強度と、ワイヤ接続強度との両方が高く得られる半導体装置を実現することができる。
以下、本発明による半導体装置の実施の形態を図１〜図１２について説明する。
図１に示すように、本実施の形態の半導体装置は、下部半導体素子としての下部ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）(1)と、下部ＩＧＢＴ(1)の上面(1a)に形成された下部電極層(5)と、下部電極層(5)と離間して下部ＩＧＢＴ(1)の上面(1a)に形成された離間電極層(ゲートパッド)(18)と、下部電極層(5)の上面(5a)に形成された上部電極層(6)と、上部電極層(6)の上面(6a)に接着剤層としての半田(7)により固着された上部半導体素子としての上部ＩＧＢＴ(2)と、上部ＩＧＢＴ(2)の上面(2a)に形成された最上部電極層(27)と、上部電極層(6)、離間電極層(18)及び下部電極層(5)等の一部を被覆する非導電性の保護膜(9)と、最上部電極層(27)等の一部を被覆する非導電性の保護膜(29)とを備える。下部電極層(5)は、上部電極層(6)に設けた切欠部(36)と保護膜(9)に設けた開口部(19)とにより、外部に露出する結線領域(15)を有する。結線領域(15)は、平坦に形成され、リード細線としてのワイヤ(8)の一方の端部が接続（ワイヤボンディング）される。
図２に示すように、下部ＩＧＢＴ(1)は、シリコン単結晶基板等から成る下部半導体基板(51)と、下部半導体基板(51)の上面(51a)に形成された例えば二酸化シリコンから成るゲート絶縁膜(24)と、下部半導体基板(51)の上面(51a)にゲート絶縁膜(24)を介して形成された例えばポリシリコンから成るゲート電極（制御電極）(25)と、ゲート電極(25)と下部電極層(5)とを電気的に絶縁する層間絶縁膜(26)と、下部半導体基板(51)の下面(51b)に形成された例えばアルミニウムとニッケルとを積層して成るコレクタ電極（底面電極）(13)とを備える。
下部半導体基板(51)は、下部半導体基板(51)の下面(51b)に隣接して形成されたＰ＋型半導体領域から成るコレクタ領域(31)と、コレクタ領域(31)に隣接して上方に形成されたＮ−型バッファ領域(32)と、Ｎ−型バッファ領域(32)に隣接して上方に形成されたＮ型ベース領域(30)と、下部半導体基板(51)の上面(51a)に隣接してＮ型ベース領域(30)内に形成されたＰ型ベース領域(33)と、下部半導体基板(51)の上面(51a)に隣接してＰ型ベース領域(33)内に形成されたＮ型エミッタ領域(34)とを備えている。Ｎ型エミッタ領域(34)とＮ型ベース領域(30)との間に挟まれたＰ型ベース領域(33)の上には、ゲート絶縁膜(24)を介してゲート電極(25)が形成されており、周知のチャネル領域を形成する。図２に示すように、ゲート電極(25)と下部電極層(5)とを電気的に絶縁する層間絶縁膜(26)には、開口部(26a)が形成され、下部電極層(5)は、開口部(26a)を通じてＮ型エミッタ領域(34)とＰ型ベース領域(33)に電気的に接続され、エミッタ電極を構成する。
図３及び図４は、下部半導体基板(51)の上面(51a)を示す。図３に示すように、Ｐ型ベース領域(33)は、下部半導体基板(51)の平面方向に対して（平面的に見て）、Ｎ型ベース領域(30)内に格子状又はストライプ状に並列して配置されている。また、Ｎ型エミッタ領域(34)はＰ型ベース領域(33)の縁部に沿って互いに対抗するように配置されている。また、ゲート電極(25)は、隣り合うＰ型ベース領域(33)に跨るようにＰ型ベース領域(33)の間にストライプ状に形成されている。これにより、半導体素子の活性領域の最小単位であるセル(20a)が形成されている。本実施の形態の半導体装置では、Ｎ型エミッタ領域(34)が下部半導体基板(51)の中央側にのみ形成されており、下部半導体基板(51)の外周側にはＮ型エミッタ領域(34)が形成されていない。このため、図４に示すように、下部ＩＧＢＴ(1)の上面(1a)には、複数のセル(20a)が形成されたセル形成領域(20)と、セル(20a)が形成されていない非形成領域(44)とが形成される。セル形成領域(20)は、下部ＩＧＢＴ(1)の中央側に形成され、非形成領域(44)はセル形成領域(20)を包囲するように下部ＩＧＢＴ(1)の外周側に環状に形成されている。なお、Ｐ型ベース領域(33)は、Ｎ型ベース領域(30)内に島状に形成してもよい。
また、下部半導体基板(51)の上面(51a)には、ゲート電極(25)と離間電極層(18)とを電気的に接続するゲートバスライン(43)が下部半導体基板(51)の周面に沿って形成される。離間電極層(18)及びゲートバスライン(43)は、アルミニウム等の導電性金属により形成され、ストライプ状に形成されたゲート電極(25)の延長部分を被覆して、ゲート電極(25)と電気的に接続される。即ち、離間電極層(18)及びゲートバスライン(43)は、下部半導体基板(51)の上面(51a)でポリシリコンとアルミニウムとの積層構造を有する。
上部ＩＧＢＴ(2)は、平面的に見て、下部ＩＧＢＴ(1)の上面(1a)及び下面(1b)と比較して小さい面積の上面(2a)及び下面(2b)を有する。図示しないが、上部ＩＧＢＴ(2)は、複数のセルが形成されたセル形成領域(20)を上面(52a)に有する上部半導体基板(52)と、上部半導体基板(52)の上面(52a)に形成されたゲート絶縁膜と、上部半導体基板(52)の上面(52a)にゲート絶縁膜を介して形成されたゲート電極と、セルに電気的に接続された最上部電極層（エミッタ電極）(27)と、ゲート電極と最上部電極層(27)とを電気的に絶縁する層間絶縁膜と、上部半導体基板(52)の下面(52b)に形成されたコレクタ電極(14)とを有する。上部ＩＧＢＴ(2)は、下部ＩＧＢＴ(1)と同様にセル形成領域(20)を半導体基板(52)の中央側にのみ形成してもよいし、セル形成領域(20)を半導体基板(52)の全体に形成してもよい。
下部ＩＧＢＴ(1)の下部電極層(5)は、Ｎ型エミッタ領域(34)とＰ型ベース領域(33)とに電気的に接続される。また、下部電極層(5)は、平面的に見て、セル形成領域(20)の外周側にまで延伸し、非形成領域(44)の上面の一部も被覆している。上部電極層(6)は、下部電極層(5)の上面(5a)に形成されており、セル形成領域(20)の外周側にまで延伸し、平面的に見て、非形成領域(44)の上面の一部も被覆している。即ち、セル形成領域(20)は、平面的に見て、セル形成領域(20)及び非形成領域(44)の外周縁よりも下部半導体基板(51)の中心側に配置されている。
また、少なくとも下部電極層(5)の上面(5a)と上部電極層(6)の上面(6a)とを異なる材質により形成し、下部電極層(5)は、ワイヤ(8)を形成する金属との接着性の高い金属により上部電極層(6)に隣接して形成された結線層(23)を有し、上部電極層(6)は、半田(7)を形成する金属との接着性の高い金属により半田(7)に隣接して形成された固着層(21)を有する。本実施の形態では、図２に示すように、下部電極層(5)は、結線層(23)のみにより構成され、結線層(23)は、ワイヤ(8)を形成するアルミニウムとの接着性の高い同じアルミニウム(Al)又はシリコン含有アルミニウムにより形成される。これに対し、上部電極層(6)は、半田(7)との密着性に優れた例えばニッケル(Ni)から成る固着層(21)と、固着層(21)と下部電極層(5)との間に形成される例えばチタン(Ti)から成る介在層(22)とを備え、固着層(21)が上部電極層(6)の上面(6a)を形成する。下部電極層(5)を上部電極層(6)と同様に複数の異なる材質からなる積層構造としてもよい。
本実施の形態では、上部電極層(6)の固着層(21)を半田(7)との濡れ性（相性）に優れたニッケルにより形成したが、半田(7)との濡れ性に優れた他の金属材（例えば金）によって形成してもよい。また、下部電極層(5)についても、同様にアルミニウム以外の他の金属を使用してもよい。上部電極層(6)の介在層(22)は、固着層(21)及び下部電極層(5)の結線層(23)の双方の材質との相性により適宜に材質が決定される。
保護膜(9,29)は、ＰＩＦ（ポリイミドフィルム）又はＰＢＯ（ポリベンズオキサゾール）等の耐熱性材料により形成され、下部ＩＧＢＴ(1)に設けられる保護膜(9)は、下部電極層(5)の結線領域(15)を外部に露出する開口部(19)を有し、上部ＩＧＢＴ(2)に設けられる保護膜(29)は、最上部電極層(27)の結線領域(35)を外部に露出する開口部(39)を有する。保護膜(9,29)は、イオン等の不純物から下部ＩＧＢＴ(1)及び上部ＩＧＢＴ(2)の半導体表面を保護する。上部ＩＧＢＴ(2)の上面(2a)に形成された最上部電極層(27)は、下部電極層(5)と同様に、ワイヤ(8)を形成する金属との接着性の高い金属により形成される。
図１に示すように、下部電極層(5)の結線領域(15)は、下部ＩＧＢＴ(1)のエミッタ電極のワイヤ接続領域（ワイヤボンディングパッド）を構成し、ワイヤ(8)により外部素子等と接続される。また、保護膜(9)の開口部(19)に露出した上部電極層(6)の上面(6a)は、上部ＩＧＢＴ(2)の半田付け領域（ダイボンディングパッド）を構成し、上部ＩＧＢＴ(2)のコレクタ電極(14)と電気的に接続される。即ち、上部ＩＧＢＴ(2)が固着する上部電極層(6)の固着領域(16)は、半田付け性に優れたニッケル電極面となり、ワイヤ(8)が接続される結線領域(15)は、ワイヤ(8)の接続性に優れたアルミニウム電極面となる。本発明では、下部ＩＧＢＴ(1)と上部ＩＧＢＴ(2)との間に設けられる下部電極層(5)の上面(5a)と上部電極層(6)の上面(6a)とを異なる材質により形成するので、上部電極層(6)の上面(6a)を半田付け性に優れた材質により形成し、下部電極層(5)の上面(5a)をワイヤ(8)との接続強度の高い材質により形成できる。このため、下部ＩＧＢＴ(1)と上部ＩＧＢＴ(2)とを半田(7)により良好に固着すると共に、下部ＩＧＢＴ(1)とワイヤ(8)とを強固に接続して、信頼性の高い半導体装置(10)を形成することができる。本発明でいう接着剤は、半田材、ろう材及び銀ペースト等の接着剤を含み、特に導電性を有することが望ましい。なお、半田材として、鉛を含まない錫、銀、銅若しくはアルミニウム等の材料からなる鉛フリー半田が使用されるが、錫及び鉛からなる一般半田又は他の周知の半田を使用してもよい。ワイヤ(8)は、例えば金、アルミニウム又はシリコン含有アルミニウムから成る周知のワイヤが使用できる。
図１の半導体装置(10)を製造する際に、複数のセル(20a)を形成したセル形成領域(20)を上面(1a)の中央側に設けた下部ＩＧＢＴ(1)と、下部ＩＧＢＴ(1)と同様にセル形成領域を上面(2a)に設けた上部ＩＧＢＴ(2)とを形成する。図３に示すように、下部ＩＧＢＴ(1)のセル形成領域(20)は、下部半導体基板(51)の上面(51a)の中央側に形成され、セル形成領域(20)を包囲して非形成領域(44)が環状に形成される。下部ＩＧＢＴ(1)及び上部ＩＧＢＴ(2)のような半導体素子の製法は公知であり、説明を省略する。
図５に示すように、アルミニウムから成る下部電極層(5)がＣＶＤ又はＰＶＤ等の蒸着法、スパッタ法又はメッキ法等の周知の方法により、下部半導体基板(51)の上面(51a)に形成される。次に、下部電極層(5)の上面(5a)に図示しないエッチングマスクを形成し、エッチングマスクに形成された開口を通じて、アルミニウムを溶解するリン酸系エッチング液等のアルミエッチング液により、離間電極層(18)と下部電極層(5)との間の離間部(37)を含む下部電極層(5)の不要な部分を除去する。下部電極層(5)は、平面的に見て、セル形成領域(20)の外周側にまで延伸し、非形成領域(44)の上面の一部も被覆している。また、離間電極層(18)は、非形成領域(44)の上面に形成される。
続いて、図６に示すように、上部電極層(6)のチタンから成る介在層(22)とニッケルから成る固着層(21)とが下部電極層(5)と同様の方法により、順次に下部電極層(5)の上面(5a)に形成される。この後、図７に示すように、上部電極層(6)の上面(6a)に図示しないエッチングマスクを形成し、エッチングマスクに形成された開口を通じて、チタンとニッケルとを同時に溶解する塩酸系エッチング液等の金属エッチング液により上部電極層(6)の不要な部分を除去する。異なるエッチング液により、チタンとニッケルとを順次にエッチングしてもよい。これにより、下部ＩＧＢＴ(1)の上面(1a)に下部電極層(5)と上部電極層(6)とを積重する。また、エッチングにより上部電極層(6)に設けた切欠部(36)により、上部電極層(6)に被覆されない結線領域(15)が下部電極層(5)に形成される。このとき、上部電極層(6)は、セル形成領域(20)の外周縁よりも下部半導体基板(51)の外周側、即ち非形成領域(44)の上側をエッチング除去する。このため、上部電極層(6)は、セル形成領域(20)の外周側にまで延伸し、平面的に見て非形成領域(44)の上面の一部も被覆している。また、図７に示すように、下部電極層(5)の結線領域(15)は、下部半導体基板(51)のセル形成領域(20)よりも外側に形成される。
エッチング液により上部電極層(6)をエッチングした際に、上部電極層(6)と共に下部電極層(5)が侵蝕されることがあるが、上部電極層(6)をセル形成領域(20)の外周縁よりも下部半導体基板(51)の外周側でエッチング除去するため、上部電極層(6)のエッチングによって電気的特性が損なわれることを防止することができる。また、セル形成領域(20)でのセル(20a)のエッチング損傷を防止することができる。即ち、下部電極層(5)は、多数のセル(20a)のＰ型ベース領域(33)及びＮ型エミッタ領域(34)を相互に電気的に接続しているため、セル形成領域(20)の上に形成された下部電極層(5)がエッチングされると、下部ＩＧＢＴ(1)の電気的特性を損なうおそれがある。これに対し、下部ＩＧＢＴ(1)のセル形成領域(20)の外側に延伸する非形成領域(44)は、ボンディングパッドと成る結線領域(15)等を構成する部分であり、万一上部電極層(6)のエッチングによって侵蝕されることがあっても、電気的特性に影響を受けることが極めて少ない。よって、電気的特性が安定して得られる信頼性の高い半導体装置を形成することができる。
次に、保護膜(9)により、上部電極層(6)、離間電極層(18)及び下部電極層(5)の一部を被覆する。保護膜(9)は、結線領域(15)と離間電極層(18)との２つのボンディングパッドと、固着領域(16)のパッドとに開口部(19)を有する。図８に示すように、固着領域(16)の開口部(19)を通じて、下部ＩＧＢＴ(1)に上部ＩＧＢＴ(2)が半田(7)により固着される。上部ＩＧＢＴ(2)には、最上部電極層(27)、保護膜(29)及びコレクタ電極(14)が予め形成される。図９に示すように、保護膜(9)は、下部ＩＧＢＴ(1)の固着領域(16)の外周に環状に形成され、上部ＩＧＢＴ(2)を固着する際の位置決め効果を有する。この結果、図１に示すように、上部ＩＧＢＴ(2)が下部ＩＧＢＴ(1)の所定位置に精度よく半田付けされる。また、固着領域(16)を包囲する保護膜(9)は、半田(7)の流れ出しを防止できる。この結果、半田(7)は、上部電極層(6)の上面に比較的厚く形成され、半導体装置(10)を動作させたときに発生する熱を良好に放熱することができる。
また、下部半導体基板(51)の下面(51b)に形成されたコレクタ電極(13)は、支持板(45)の上面に半田を介して固着される。更に、図１に示すように、下部ＩＧＢＴ(1)及び上部ＩＧＢＴ(2)の結線領域(15,35)と離間電極層(18)は、図示しない外部素子又は外部リードに接続されたワイヤ(8)の端部が接続される。これにより、半導体装置(10)が完成する。
図１０は、図１に示す半導体装置(10)により図１１に示すＨ型ブリッジ回路を単一の半導体装置で構成した本発明の実施例を示す。Ｈ型ブリッジ回路は、ハイサイド側の下部ＩＧＢＴ(1)及び他の下部ＩＧＢＴ(3)と、ローサイド側の上部ＩＧＢＴ(2)及び他の上部ＩＧＢＴ(4)とを備える。下部ＩＧＢＴ(1)と上部ＩＧＢＴ(2)との第１積層体と、他の下部ＩＧＢＴ(3)と他の上部ＩＧＢＴ(4)との第２積層体とは、放熱性を有する銅又はアルミニウム等の金属製の支持板(45)の上に固着される。下部ＩＧＢＴ(1)から他の上部ＩＧＢＴ(4)までのスイッチング動作を制御する制御装置(40)を備え、制御装置(40)の表面電極又は支持板(45)の周囲に配置された複数の外部リード(42)と、下部ＩＧＢＴ(1)及び上部ＩＧＢＴ(2)の結線領域（エミッタ電極）(15,35)と離間電極層（ゲート電極）(18)とをワイヤ(8)により接続する。図１０に示すように、制御装置(40)は、第１積層体と第２積層体との間で支持板(45)上に固着されている。下部ＩＧＢＴ(1)の下部電極層（エミッタ電極）(5)と上部ＩＧＢＴ(2)のコレクタ電極(14)との接続点(A1)と、他の下部ＩＧＢＴ(3)の下部電極層（エミッタ電極）と他の上部ＩＧＢＴ(4)のコレクタ電極との接続点(A2)との間には、交流電流により駆動される例えば冷陰極蛍光放電管である負荷(41)が接続される。樹脂封止体(43)により半導体装置全体が被覆されるが、外部リード(42)は樹脂封止体(43)から外部に導出される。
Ｈ型ブリッジ回路を作動する際に、下部ＩＧＢＴ(1)及び他の上部ＩＧＢＴ(4)と、上部ＩＧＢＴ(2)及び他の下部ＩＧＢＴ(3)とを交互にオン・オフ動作させて、スイッチング作動させることにより、接続点(A1)と(A2)との間に交互に逆方向の電流を流して、負荷(41)を作動させることができる。このように、下部ＩＧＢＴ(1)から他の上部ＩＧＢＴ(4)までのスイッチング動作を行ない、直流電圧源を使用し、接続点(A1)と(A2)との間に接続された冷陰極蛍光放電管を点灯させることができる。図１０に示す半導体装置(50)によれば、支持板(45)の占有面積を減少しつつ集積度を向上できると共に、下部ＩＧＢＴ(1)と上部ＩＧＢＴ(2)と、他の下部ＩＧＢＴ(3)と他の上部ＩＧＢＴ(4)とを半田(7)により良好に固着し、各ＩＧＢＴ(1,2,3,4)とワイヤ(8)とを強固に接続して、信頼性の高い半導体装置を形成することができる。
本発明の実施の形態は、前記実施の形態に限定されず、種々の変更が可能である。例えば、各ＩＧＢＴ(1,2,3,4)に代えて、他のバイポーラトランジスタ、電界効果トランジスタ、サイリスタ又はトライアック等の半導体素子を構成してもよい。また、図１２に示すように、保護膜(9)により下部電極層(5)の一部を被覆した後に、上部電極層(6)を下部電極層(5)の上面(5a)に形成してもよい。このようにすると、保護膜(9)によって下部電極層(5)が保護されるため、保護膜(9)の上方で上部電極層(6)の不要な部分をエッチング除去したときに、下部電極層(5)が侵蝕されるのを良好に防止できる。
本発明は、複数の半導体素子を積重して形成された半導体装置、冷陰極蛍光放電管の駆動装置に使用されるＨブリッジ回路（フルブリッジ回路）等を構成する半導体装置に良好に適用できる。
本発明による半導体装置の一実施の形態を示す断面図 図１の部分拡大図 図１の下部半導体基板の部分拡大図 図１の下部半導体基板の平面図 下部半導体基板の上面に下部電極層を形成した状態を示す断面図 図５の下部電極層の上面に上部電極層を形成した状態を示す断面図 図６の上部電極層をエッチングした状態を示す断面図 図９に上部ＩＧＢＴを積重した状態を示す断面図 図７の下部半導体基板の上面に保護膜を被覆した状態を示す平面図 図１の半導体装置の実施例を示す平面図 図１０の回路図 図１の変形例を示す断面図
符号の説明
(1)・・下部半導体素子（下部ＩＧＢＴ）、 (1a,2a,5a,6a)・・上面、 (2)・・上部半導体素子（上部ＩＧＢＴ）、 (5)・・下部電極層、 (6)・・上部電極層、 (7)・・半田、 (8)・・リード細線（ワイヤ）、 (9)・・保護膜、 (15)・・結線領域、 (19)・・開口部、 (20)・・セル形成領域、 (20a)・・セル、 (21)・・固着層、 (23)・・結線層、 (36)・・切欠部、 (40)・・制御装置、

Claims (5)

  1. 下部半導体素子と、該下部半導体素子の上面に形成された下部電極層と、該下部電極層の上面に形成された上部電極層と、該上部電極層の上面に固着された上部半導体素子と、前記上部電極層と前記上部半導体素子とを固着する接着剤層とを備え、
    前記下部電極層の上面と前記上部電極層の上面とを異なる材質により形成し、
    前記上部電極層から外部に部分的に露出する結線領域を前記下部電極層の上面に設け、
    前記結線領域にリード細線の端部を接続したことを特徴とする半導体装置。
  2. 前記下部電極層の上面は、前記上部電極層の上面よりも前記リード細線を形成する金属との接着性の高い金属により形成され、
    前記上部電極層の上面は、前記下部電極層の上面よりも前記接着剤層を形成する材料との接着性の高い金属により形成された請求項１に記載の半導体装置。
  3. 前記下部半導体素子は、複数のセルが形成されたセル形成領域と、セルが形成されていない非形成領域とを前記上面に有し、
    前記セル形成領域は、前記下部半導体素子の中央側に配置され、
    前記非形成領域は、前記セル形成領域を包囲して前記下部半導体素子の外周側に環状に配置され、
    前記上部電極層は、前記セル形成領域よりも前記下部半導体素子の外周側に延伸する請求項１又は２に記載の半導体装置。
  4. 下部半導体素子の上面に下部電極層を形成する工程と、
    前記下部電極層の上面とは異なる材質により成る上面を有する上部電極層を前記下部電極層の上面に形成する工程と、
    前記上部電極層に切欠部を設けて該切欠部を通じて外部に部分的に露出する結線領域を前記下部電極層の上面に形成する工程と、
    接着剤により前記上部電極層の上面に上部半導体素子を固着する工程と、
    前記結線領域にリード細線の端部を接続する工程とを含むことを特徴とする半導体装置の製法。
  5. 前記下部半導体素子の上面に複数のセルが形成されたセル形成領域と、セルが形成されていない非形成領域とを設ける工程を含み、
    前記下部電極層の上面に結線領域を形成する工程は、前記上部電極層を前記セル形成領域よりも前記下部半導体素子の内側でエッチング除去する工程を含む請求項４に記載の半導体装置の製法。
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