WO2007007445A1 - 半導体装置及びその製法 - Google Patents

半導体装置及びその製法 Download PDF

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Publication number
WO2007007445A1
WO2007007445A1 PCT/JP2006/305702 JP2006305702W WO2007007445A1 WO 2007007445 A1 WO2007007445 A1 WO 2007007445A1 JP 2006305702 W JP2006305702 W JP 2006305702W WO 2007007445 A1 WO2007007445 A1 WO 2007007445A1
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WIPO (PCT)
Prior art keywords
electrode layer
igbt
region
lower electrode
semiconductor element
Prior art date
Application number
PCT/JP2006/305702
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English (en)
French (fr)
Inventor
Katsuyuki Torii
Original Assignee
Sanken Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co., Ltd. filed Critical Sanken Electric Co., Ltd.
Priority to CN2006800010134A priority Critical patent/CN101040386B/zh
Priority to EP06729669A priority patent/EP1906452B1/en
Priority to US11/994,514 priority patent/US7847316B2/en
Publication of WO2007007445A1 publication Critical patent/WO2007007445A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device that can be downsized by stacking a plurality of semiconductor elements.
  • a semiconductor device that forms an H-type bridge circuit by the third transistor and the fourth transistor is known from Patent Document 1 below. According to Patent Document 1, the first transistor and the second transistor are stacked, and the third transistor and the fourth transistor are stacked, thereby reducing the area occupied by the support plate. The degree can be improved.
  • the upper electrode formed on the upper surfaces of the first transistor and the third transistor and the lower electrode formed on the lower surfaces of the second transistor and the fourth transistor are fixed by soldering, and the upper electrode formed on the upper surface of the first transistor and the third transistor and the upper electrode of the control circuit and a plurality of external leads arranged around the support plate are connected by wires. Connected. The first transistor, the second transistor, and the third transistor and the fourth transistor are electrically connected to each other by soldering, so that the current connection path is shortened and noise is generated by extending the current connection path. And power loss can be suppressed. Moreover, wire connection can be simplified.
  • Patent Document 1 International Publication No. 2005Z018001
  • an object of the present invention is to provide a semiconductor device having an electrode having high connectivity with a wire and solder, and a manufacturing method thereof.
  • the semiconductor device of the present invention includes a lower semiconductor element (1), a lower electrode layer (5) formed on the upper surface (la) of the lower semiconductor element (1), and an upper surface of the lower electrode layer (5) ( The upper electrode layer (6) formed in 5a), the upper semiconductor element (2) fixed to the upper surface (6a) of the upper electrode layer (6), the upper electrode layer (6) and the upper semiconductor element (2 ) And an adhesive layer (7).
  • the manufacturing method of the semiconductor device of the present invention is different from the step of forming the lower electrode layer (5) on the upper surface (la) of the lower semiconductor element (1) and the upper surface (5a) of the lower electrode layer (5).
  • the upper surface (5a) of the lower electrode layer (5) and the upper surface (6a) of the upper electrode layer (6) formed between the lower semiconductor element (1) and the upper semiconductor element (2) are formed of different materials. Therefore, the upper surface (6a) of the upper electrode layer (6) is made of a material with excellent solderability, and the upper surface (5a) of the lower electrode layer (5) is a material with high connection strength to the lead wire (8). Can be formed. For this reason, the lower semiconductor element (1) and Highly reliable by firmly bonding the upper semiconductor element (2) to the upper semiconductor element (2) with an adhesive layer (7) made of solder, and firmly connecting the lower semiconductor element (1) and the fine lead wire (8). A semiconductor device can be formed.
  • FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention.
  • FIG. 5 is a sectional view showing a state in which a lower electrode layer is formed on the upper surface of the lower semiconductor substrate.
  • FIG. 6 is a sectional view showing a state in which an upper electrode layer is formed on the upper surface of the lower electrode layer in FIG.
  • FIG. 7 is a sectional view showing a state where the upper electrode layer in FIG. 6 is etched.
  • Fig. 9 is a cross-sectional view showing the state where the upper IGBT is stacked
  • FIG. 9 is a plan view showing a state where a protective film is coated on the upper surface of the lower semiconductor substrate of FIG.
  • FIG. 10 is a plan view showing an embodiment of the semiconductor device of FIG.
  • FIG. 12 is a sectional view showing a modification of FIG.
  • the semiconductor device of the present embodiment is formed on a lower I GBT (insulated gate bipolar transistor) (1) as a lower semiconductor element and an upper surface (la) of a lower IGBT (l).
  • a non-conductive protective film (9) covering a part and a non-conductive protective film (29) covering a part of the uppermost electrode layer (27) and the like are provided.
  • the lower electrode layer (5) has a connection region (15) exposed to the outside by a notch (36) provided in the upper electrode layer (6) and an opening (19) provided in the protective film (9). .
  • the connection region (15) is formed flat, and one end of the wire (8) as a lead fine wire is connected (wire bonding).
  • the lower IGBT (l) is formed, for example, on a lower semiconductor substrate (51) made of silicon single crystal substrate and is formed on the upper surface (51a) of the lower semiconductor substrate (51).
  • a collector electrode (bottom electrode) (13) formed by laminating aluminum and nickel is provided.
  • the lower semiconductor substrate (51) is formed adjacent to the lower surface (51b) of the lower semiconductor substrate (51).
  • a gate electrode (25) is formed on the P-type base region (33) sandwiched between the N-type emitter region (34) and the N-type base region (30) via a gate insulating film (24).
  • Well-known channel area Form a zone.
  • an opening (26a) is formed in the interlayer insulating film (26) that electrically insulates the gate electrode (25) from the lower electrode layer (5), and the lower electrode layer (5) Is electrically connected to the N-type emitter region (34) and the P-type base region (33) through the opening (26a) to form an emitter electrode.
  • FIG. 3 and 4 show the upper surface (51a) of the lower semiconductor substrate (51).
  • the P-type base region (33) is latticed in the N-type base region (30) with respect to the plane direction of the lower semiconductor substrate (51) (as viewed in plan). In parallel or in stripes.
  • the N-type emitter region (34) is arranged so as to oppose each other along the edge of the P-type base region (33).
  • the gate electrode (25) is formed in a stripe shape between the P-type base regions (33) so as to straddle the adjacent P-type base regions (33). As a result, a cell (20a) which is the minimum unit of the active region of the semiconductor element is formed.
  • the N-type emitter region (34) is formed only on the center side of the lower semiconductor substrate (51), and the N-type emitter region is formed on the outer peripheral side of the lower semiconductor substrate (51). (34) is not formed. Therefore, as shown in FIG. 4, the upper surface (la) of the lower IGBT (l) has no cell formation region (20) in which a plurality of cells (20a) are formed, and no cell (20a) is formed. A non-forming region (44) is formed.
  • the cell formation region (20) is formed on the center side of the lower IGBT (l), and the non-formation region (44) is annularly formed on the outer peripheral side of the lower IGBT (l) so as to surround the cell formation region (20). Is formed.
  • the P-type base region (33) may be formed in an island shape in the N-type base region (30).
  • a gate bus line (43) for electrically connecting the gate electrode (25) and the separated electrode layer (18) is provided on the lower semiconductor substrate (51).
  • the spaced electrode layer (18) and the gate bus line (43) are formed of a conductive metal such as aluminum, and cover the extended portion of the gate electrode (25) formed in a stripe shape to form a gate electrode (25 ) And electrically connected. That is, the separated electrode layer (18) and the gate bus line (43) have a laminated structure of polysilicon and aluminum on the upper surface (51a) of the lower semiconductor substrate (51).
  • the upper IGBT (2) has an upper surface (2a) and a lower surface (2b) that are smaller in area than the upper surface (la) and the lower surface (lb) of the lower IGBT (l) in plan view.
  • the upper IGBT (2) includes an upper semiconductor substrate (52) having a cell formation region (20) in which a plurality of cells are formed on the upper surface (52a), A gate insulating film formed on the upper surface (52a) of the upper semiconductor substrate (52), a gate electrode formed on the upper surface (52a) of the upper semiconductor substrate (52) via the gate insulating film, and the cell electrically Connected to the uppermost electrode layer (emitter electrode) (27), the interlayer insulating film that electrically insulates the gate electrode from the uppermost electrode layer (27), and the lower surface (52b) of the upper semiconductor substrate (52). And a collector electrode (14) formed.
  • the cell formation region (20) may be formed only on the center side of the semiconductor substrate (52) as in the case of the
  • the lower electrode layer (5) of the lower IGBT (l) is electrically connected to the N-type emitter region (34) and the P-type base region (33). Further, the lower electrode layer (5) extends to the outer peripheral side of the cell formation region (20) in plan view, and also covers a part of the upper surface of the non-formation region (44).
  • the upper electrode layer (6) is formed on the upper surface (5a) of the lower electrode layer (5), and extends to the outer peripheral side of the cell formation region (20). A part of the upper surface of) is also covered. That is, the cell formation region (20) is arranged on the center side of the lower semiconductor substrate (51) from the outer peripheral edge of the cell formation region (20) and the non-formation region (44) in plan view. .
  • the lower electrode layer (5) and the upper surface (6a) of the upper electrode layer (6) are formed of different materials, and the lower electrode layer (5) It has a wiring layer (23) formed adjacent to the upper electrode layer (6) by a metal having high adhesiveness to the metal forming the upper electrode layer (6), and the upper electrode layer (6) forms a solder (7). It has an adhesion layer (21) formed adjacent to the solder (7) with a metal having high adhesion to the metal.
  • the lower electrode layer (5) is composed only of the connection layer (23), and the connection layer (23) is adhesive to the aluminum forming the wire (8).
  • the upper electrode layer (6) has excellent adhesion to the solder (7), for example, an adhesion layer (21) having nickel (Ni) force, an adhesion layer (21), and a lower electrode layer (5). And an intervening layer (22) that also has, for example, titanium (z) force formed between them, and the fixing layer (21) forms the upper surface (6a) of the upper electrode layer (6).
  • the lower electrode layer (5) may have a laminated structure having a plurality of different material forces.
  • the adhesive layer (21) of the upper electrode layer (6) is formed of nickel having excellent wettability (compatibility) with the solder (7). It may be formed of another metal material excellent in (for example, gold).
  • the lower electrode layer (5) is other than aluminum. Other metals may be used.
  • the material of the intervening layer (22) of the upper electrode layer (6) is appropriately determined depending on the compatibility with the materials of both the fixing layer (21) and the wiring layer (23) of the lower electrode layer (5).
  • the protective film (9, 29) is formed of a heat-resistant material such as PIF (polyimide film) or PBO (polybenzoxazole), and the protective film (9) provided on the lower IGBT (l) is formed of the lower electrode.
  • the protective layer (29) provided on the upper IGBT (2) has an opening (19) that exposes the connection region (15) of the layer (5) to the outside, and the connection region of the uppermost electrode layer (27). It has an opening (39) that exposes (35) to the outside.
  • the protective film (9, 29) protects the semiconductor surface of the lower IGBT (l) and the upper IGBT (2) from impurities such as ions.
  • the uppermost electrode layer (27) formed on the upper surface (2a) of the upper IGBT (2) is made of a metal having high adhesiveness with the metal forming the wire (8), like the lower electrode layer (5). It is formed.
  • connection region (15) of the lower electrode layer (5) constitutes the wire connection region (wire bonding pad) of the emitter electrode of the lower IGBT (l), and the wire (8) Connected with external elements.
  • the upper surface (6a) of the upper electrode layer (6) exposed in the opening (19) of the protective film (9) constitutes the soldering area (die bonding pad) of the upper IGBT (2), and the upper IGBT ( It is electrically connected to the collector electrode (14) in 2). That is, the fixed region (16) of the upper electrode layer (6) to which the upper IGBT (2) is fixed becomes a nickel electrode surface excellent in solderability, and the connection region (15) to which the wire (8) is connected is The aluminum electrode surface is excellent in wire (8) connectivity.
  • the upper surface (5a) of the lower electrode layer (5) provided between the lower IGBT (l) and the upper IGBT (2) and the upper surface (6a) of the upper electrode layer (6) are made of different materials. Therefore, the upper surface (6a) of the upper electrode layer (6) is made of a material with excellent solderability, and the upper surface (5a) of the lower electrode layer (5) has high connection strength with the wire (8). It can be formed by the material. For this reason, the lower IGBT (l) and the upper IGBT (2) are firmly fixed with solder (7), and the lower IGBT (l) and the wire (8) are firmly connected to provide a highly reliable semiconductor. A device (10) can be formed.
  • the adhesive referred to in the present invention includes an adhesive such as a solder material, a brazing material, and a silver paste, and it is particularly desirable to have conductivity.
  • a solder material it is possible to use lead-free solder that also has material strength such as tin, silver, copper, or aluminum that does not contain lead.
  • General solder that is tin and lead or other well-known solder may be used.
  • the wire (8) for example, a well-known wire made of gold, aluminum, or silicon-containing aluminum can be used.
  • a lower IGBT (l) in which a cell formation region (20) in which a plurality of cells (20a) are formed is provided on the center side of the upper surface (la);
  • the upper IGBT (2) with the cell formation area on the upper surface (2a) is formed.
  • the cell formation region (20) of the lower IGBT (l) is formed on the center side of the upper surface (51a) of the lower semiconductor substrate (51) and surrounds the cell formation region (20).
  • the formation region (44) is formed in an annular shape. Manufacturing methods of semiconductor elements such as the lower IGBT (l) and the upper IGBT (2) are well known and will not be described.
  • the lower electrode layer (5) made of aluminum is applied to the upper surface (51a) of the lower semiconductor substrate (51) by a known method such as a deposition method such as CVD or PVD, a sputtering method, or a plating method. ) Formed.
  • a deposition method such as CVD or PVD
  • a sputtering method or a plating method.
  • an etching mask (not shown) is formed on the upper surface (5a) of the lower electrode layer (5), and is separated by an aluminum etching solution such as a phosphate-based etching solution that dissolves aluminum through an opening formed in the etching mask. Unnecessary portions of the lower electrode layer (5) including the gap (37) between the electrode layer (18) and the lower electrode layer (5) are removed.
  • the lower electrode layer (5) extends to the outer peripheral side of the cell formation region (20) in a plan view and covers a part of the upper surface of the non-formation region (44). Further, the separation electrode layer (18) is formed on the upper surface of the non-formation region (44).
  • the intervening layer (22) also having the titanium force of the upper electrode layer (6) and the fixing layer (21) made of nickel are the same method as the lower electrode layer (5).
  • the lower electrode layer (5) is sequentially formed on the upper surface (5a).
  • an etching mask (not shown) is formed on the upper surface (6a) of the upper electrode layer (6), and hydrochloric acid that simultaneously dissolves titanium and nickel through the opening formed in the etching mask.
  • Unnecessary portions of the upper electrode layer (6) are removed with a metal etchant such as a base etchant. Titanium and nickel may be sequentially etched with different etching solutions.
  • the lower electrode layer (5) and the upper electrode layer (6) are stacked on the upper surface (la) of the lower IGBT (l). Further, a connection region (15) that is not covered by the upper electrode layer (6) is formed in the lower electrode layer (5) by the notch (36) provided in the upper electrode layer (6) by etching.
  • the upper electrode layer (6) etches away the outer peripheral side of the lower semiconductor substrate (51) from the outer peripheral edge of the cell forming region (20), that is, the upper side of the non-formed region (44). For this reason, the upper electrode layer (6) extends to the outer peripheral side of the cell formation region (20), and also covers a part of the upper surface of the non-formation region (44) when seen in a plan view.
  • connection region (15) of the lower electrode layer (5) is formed outside the cell formation region (20) of the lower semiconductor substrate (51).
  • the lower electrode layer (5) may be eroded together with the upper electrode layer (6). Since etching is removed on the outer peripheral side of the lower semiconductor substrate (51) rather than the outer peripheral edge of (20), it is possible to prevent the electrical characteristics from being damaged by etching of the upper electrode layer (6). Further, etching damage of the cell (20a) in the cell formation region (20) can be prevented. That is, the lower electrode layer (
  • the cell formation region (20) because the P-type base region (33) and the N-type emitter region (34) of many cells (20a) are electrically connected to each other. If the lower electrode layer (5) is etched, the electrical characteristics of the lower IGBT (l) may be impaired. On the other hand, the non-formation region (44) extending outside the cell formation region (20) of the lower IGBT (l) is a part constituting the connection region (15) etc. serving as a bonding pad. Even if it is eroded by the etching of the upper electrode layer (6), it is very unlikely to be affected by the electrical characteristics. Therefore, a highly reliable semiconductor device with stable electrical characteristics can be formed.
  • the protective film (9) has an opening (19) in the two bonding pads of the connection region (15) and the separated electrode layer (18) and the pad of the fixing region (16). As shown in Figure 8, the anchoring area (1
  • the upper IGBT (2) is fixed to the lower IGBT (l) by solder (7).
  • the uppermost electrode layer (27), the protective film (29), and the collector electrode (14) are formed in advance.
  • the protective film (9) is formed in an annular shape on the outer periphery of the fixing region (16) of the lower IGBT (l), and has a positioning effect when fixing the upper IGBT (2).
  • the upper IGBT (2) is accurately soldered to a predetermined position of the lower IGBT (l).
  • the protective film (9) surrounding the fixing region (16) can prevent the solder (7) from flowing out.
  • the solder (7) is formed relatively thick on the upper surface of the upper electrode layer (6), and the heat generated when the semiconductor device (10) is operated can be radiated well.
  • the collector electrode (13) formed on the lower surface (51b) of the lower semiconductor substrate (51) is fixed to the upper surface of the support plate (45) via solder. Further, as shown in FIG. 1, the connection regions (15, 35) and the separated electrode layer (18) of the lower IGBT (l) and the upper IGBT (2) are not shown, but are connected to external elements or external leads. The end of the connected wire (8) is connected. This completed the semiconductor device (10). To do.
  • FIG. 10 shows an embodiment of the present invention in which the H-type bridge circuit shown in FIG. 11 is configured by a single semiconductor device by the semiconductor device (10) shown in FIG.
  • the H-type bridge circuit includes a lower IGBT (l) on the high side and another lower IGBT (3), an upper IGBT (2) on the low side, and another upper IGBT (4).
  • the first stack of lower IGBT (l) and upper IGBT (2) and the second stack of other lower IGBT (3) and other upper IGBT (4) are copper or aluminum with heat dissipation It is fixed on the metal support plate (45).
  • the lower IGBT (l) force is also equipped with a control device (40) that controls the switching operation to the other upper IGBT (4), and a plurality of devices arranged around the surface electrode or support plate (45) of the control device (40).
  • the external lead (42), the connection region (emitter electrode) (15, 35) of the lower IGBT (l) and the upper IGBT (2) (15) and the separated electrode layer (gate electrode) (18) are connected by the wire (8). Connect.
  • the control device (40) is fixed on the support plate (45) between the first laminate and the second laminate.
  • junction electrode (A) and the collector electrode of the other upper IGBT (4) are located between the junction electrode (A) and the collector electrode of the other upper IGBT (4).
  • a load (41), for example a cold cathode fluorescent discharge tube, driven by the flow is connected.
  • the entire semiconductor device is covered with the resin sealant (43), but the external lead (42) is led out from the resin sealant (43).
  • the lower IGBT (1) and other upper IGBT (4), and the upper BT (2) and other lower IGBT (3) are alternately turned on and off. By switching, the reverse current flows alternately between the connection points (A) and (A) to create the load (41).
  • the polar fluorescent discharge tube can be turned on.
  • the integration area can be improved while reducing the area occupied by the support plate (45), and the lower IGBT (l), upper I GBT (2), and other lower IGBT (3) and other upper IGBT (4) are firmly fixed with solder (7), and each IGBT (1,2,3,4) and wire (8) are firmly connected for reliability
  • a semiconductor device with high resistance can be formed.
  • Embodiments of the present invention are not limited to the above-described embodiments, and various modifications are possible.
  • a semiconductor element such as another bipolar transistor, a field effect transistor, a thyristor, or a triac may be configured.
  • the upper electrode layer (6) is applied to the upper surface (5a) of the lower electrode layer (5). It may be formed. By rubbing in this way, the lower electrode layer (5) is protected by the protective film (9), so when unnecessary portions of the upper electrode layer (6) are etched away above the protective film (9), It is possible to satisfactorily prevent the lower electrode layer (5) from being eroded.
  • the present invention is suitable for a semiconductor device formed by stacking a plurality of semiconductor elements, a semiconductor device constituting an H bridge circuit (full bridge circuit) used for a cold cathode fluorescent tube driving device, etc. Applicable to.

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Abstract

　下部ＩＧＢＴと上部ＩＧＢＴとを半田により良好に固着すると共に、下部ＩＧＢＴとワイヤとを強固に接続して、信頼性の高い半導体装置を形成する。下部ＩＧＢＴ(1)に固着された下部電極層(5)と、下部電極層(5)に固着された上部電極層(6)と、上部電極層(6)に固着された上部ＩＧＢＴ(2)と、上部電極層(6)と上部ＩＧＢＴ(2)とを接続する半田(7)とを備える。下部電極層(5)と上部電極層(6)とを異なる材質により形成し、上部電極層(6)に設けた切欠部(36)から外部に部分的に露出する結線領域(15)を下部電極層(5)の上面(5a)に設け、結線領域(15)にワイヤ(8)を接続する。上部電極層(6)を半田付け性に優れた材質により形成し、下部電極層(5)をワイヤ(8)との接続強度の高い材質により形成することができる。

Description

明 細 書
半導体装置及びその製法
技術分野
[0001] 本発明は、半導体装置、特に複数の半導体素子を積重して小型化できる半導体装 置に関する。
背景技術
[0002] 金属製の支持板と、支持板上に順次積層された第 1のトランジスタ及び第 2のトラン ジスタと、支持板上に順次積層された第 3のトランジスタ及び第 4のトランジスタと、第 1のトランジスタ及び第 2のトランジスタと第 3のトランジスタ及び第 4のトランジスタとの 間で支持板上に固着された制御回路 (制御 IC)とを備え、第 1のトランジスタ及び第 2 のトランジスタと、第 3のトランジスタ及び第 4のトランジスタとにより、 H型ブリッジ回路 を構成する半導体装置は、下記特許文献 1により公知である。特許文献 1によれば、 第 1のトランジスタと第 2のトランジスタとを積重すると共に、第 3のトランジスタと第 4の トランジスタとを積重することにより、支持板の占有面積を減少しつつ集積度を向上 することができる。
[0003] また、特許文献 1の半導体装置では、第 1のトランジスタ及び第 3のトランジスタの上 面に形成された上面電極と第 2のトランジスタ及び第 4のトランジスタの下面に形成さ れた下面電極とを半田により固着すると共に、第 1のトランジスタ及び第 3のトランジス タの上面に形成された上面電極と制御回路の上面電極及び支持板の周囲に配置さ れた複数の外部リードとをワイヤにより接続している。第 1のトランジスタと第 2のトラン ジスタ及び第 3のトランジスタと第 4のトランジスタとを半田により電気的に互いに接続 するので、電流の結線経路を短縮して、電流の結線経路の延長によるノイズ発生及 び電力損失を抑制することができる。また、ワイヤ結線を簡素化できる。
[0004] 特許文献 1：国際公開第 2005Z018001号公報
発明の開示
発明が解決しょうとする課題
[0005] し力しながら、下方に配置される第 1のトランジスタ及び第 3のトランジスタの上面電 極は、第 2のトランジスタ及び第 4のトランジスタの下面電極との半田による接続に適 した金属又はワイヤとの接続に適した金属の何れかにより形成されていた。半田付け 性に優れたニッケル又は銅等の金属力 成る電極は、アルミニウム又は金等の金属 力も成るワイヤとの接続性が劣っている。また、ワイヤとの接続強度が高いアルミ-ゥ ム等の金属力 成る電極は、鉛又は錫等の金属力 成る半田との接続性（半田濡れ 性)が劣っている。このため、上記特許文献 1の半導体装置では、半田付け強度とヮ ィャ接続強度の両方が高く得られる半導体装置を実現することが困難であった。 よって、本発明は、ワイヤ及び半田との接続性の高い電極を有する半導体装置及 びその製法を提供することを目的とする。
課題を解決するための手段
[0006] 本発明の半導体装置は、下部半導体素子 (1)と、下部半導体素子 (1)の上面 (la)に 形成された下部電極層 (5)と、下部電極層 (5)の上面 (5a)に形成された上部電極層 (6) と、上部電極層 (6)の上面 (6a)に固着された上部半導体素子 (2)と、上部電極層 (6)と上 部半導体素子 (2)とを固着する接着剤層 (7)とを備えて 、る。下部電極層 (5)の上面 (5a) と上部電極層 (6)の上面 (6a)とを異なる材質により形成し、上部電極層 (6)から外部に 部分的に露出する結線領域 (15)を下部電極層 (5)の上面 (5a)に設け、結線領域 (15)に リード細線 (8)の端部を接続する。
[0007] 本発明の半導体装置の製法は、下部半導体素子 (1)の上面 (la)に下部電極層 (5)を 形成する工程と、下部電極層 (5)の上面 (5a)とは異なる材質により成る上面 (6a)を有す る上部電極層 (6)を下部電極層 (5)の上面 (5a)に形成する工程と、上部電極層 (6)に切 欠部 (36)を設けて切欠部 (36)を通じて外部に部分的に露出する結線領域 (15)を下部 電極層 (5)の上面 (5a)に形成する工程と、接着剤 (7)により上部電極層 (6)の上面 (6a)に 上部半導体素子 (2)を固着する工程と、結線領域 (15)にリード細線 (8)の端部を接続す る工程とを含む。
[0008] 下部半導体素子 (1)と上部半導体素子 (2)との間に設けられる下部電極層 (5)の上面 (5a)と上部電極層 (6)の上面 (6a)を異なる材質により形成するので、上部電極層 (6)の 上面 (6a)を半田付け性に優れた材質により形成し、下部電極層 (5)の上面 (5a)をリード 細線 (8)との接続強度の高い材質により形成できる。このため、下部半導体素子 (1)と 上部半導体素子 (2)とを半田等力 成る接着剤層 (7)により良好に固着すると共に、下 部半導体素子 (1)とリード細線 (8)とを強固に接続して、信頼性の高い半導体装置を形 成することができる。
発明の効果
[0009] 本発明によれば、上部半導体素子と下部半導体素子との半田付け強度と、ワイヤ 接続強度との両方が高く得られる半導体装置を実現することができる。
図面の簡単な説明
[0010] [図 1]本発明による半導体装置の一実施の形態を示す断面図
[図 2]図 1の部分拡大図
[図 3]図 1の下部半導体基板の部分拡大図
[図 4]図 1の下部半導体基板の平面図
[図 5]下部半導体基板の上面に下部電極層を形成した状態を示す断面図
[図 6]図 5の下部電極層の上面に上部電極層を形成した状態を示す断面図
[図 7]図 6の上部電極層をエッチングした状態を示す断面図
[図 8]図 9に上部 IGBTを積重した状態を示す断面図
[図 9]図 7の下部半導体基板の上面に保護膜を被覆した状態を示す平面図
[図 10]図 1の半導体装置の実施例を示す平面図
[図 11]図 10の回路図
[図 12]図 1の変形例を示す断面図
符号の説明
[0011] (1)· ·下部半導体素子（下部 IGBT)、 (la,2a,5a,6a)- -_hB, (2)· ·上部半導体素 子 (上部 IGBT)、 （5)· ·下部電極層、 （6)· ·上部電極層、 （7)· ·半田、 （8) · ·リード 細線 (ワイヤ)、 （9) · ·保護膜、 （15) · ·結線領域、 （19)· ·開口部、 （20)· ·セル形成 領域、 （20&)· ·セル、 （21)· ·固着層、 （23)· ·結線層、 （36)· ·切欠部、 （40)· '制 御装置、
発明を実施するための最良の形態
[0012] 以下、本発明による半導体装置及びその製法の実施の形態を図 1〜図 12につい て説明する。
図 1に示すように、本実施の形態の半導体装置は、下部半導体素子としての下部 I GBT (絶縁ゲート型バイポーラトランジスタ）（1)と、下部 IGBT(l)の上面 (la)に形成さ れた下部電極層 (5)と、下部電極層 (5)と離間して下部 IGBT(l)の上面 (la)に形成され た離間電極層 (ゲートパッド) (18)と、下部電極層 (5)の上面 (5a)に形成された上部電極 層 (6)と、上部電極層 (6)の上面 (6a)に接着剤層としての半田 (7)により固着された上部 半導体素子としての上部 IGBT(2)と、上部 IGBT(2)の上面 (2a)に形成された最上部 電極層 (27)と、上部電極層 (6)、離間電極層 (18)及び下部電極層 (5)等の一部を被覆 する非導電性の保護膜 (9)と、最上部電極層 (27)等の一部を被覆する非導電性の保 護膜 (29)とを備える。下部電極層 (5)は、上部電極層 (6)に設けた切欠部 (36)と保護膜 ( 9)に設けた開口部 (19)とにより、外部に露出する結線領域 (15)を有する。結線領域 (15 )は、平坦に形成され、リード細線としてのワイヤ (8)の一方の端部が接続 (ワイヤボン デイング)される。
[0013] 図 2に示すように、下部 IGBT(l)は、シリコン単結晶基板等力 成る下部半導体基 板 (51)と、下部半導体基板 (51)の上面 (51a)に形成された例えば二酸ィ匕シリコン力 成 るゲート絶縁膜 (24)と、下部半導体基板 (51)の上面 (51a)にゲート絶縁膜 (24)を介して 形成された例えばポリシリコンカゝら成るゲート電極 (制御電極) (25)と、ゲート電極 (25) と下部電極層 (5)とを電気的に絶縁する層間絶縁膜 (26)と、下部半導体基板 (51)の下 面 (5 lb)に形成された例えばアルミニウムとニッケルとを積層して成るコレクタ電極 (底 面電極)（13)とを備える。
[0014] 下部半導体基板 (51)は、下部半導体基板 (51)の下面 (51b)に隣接して形成された P
+型半導体領域力も成るコレクタ領域 (31)と、コレクタ領域 (31)に隣接して上方に形 成された N—型バッファ領域 (32)と、 N—型バッファ領域 (32)に隣接して上方に形成さ れた N型ベース領域 (30)と、下部半導体基板 (51)の上面 (51a)に隣接して N型ベース 領域 (30)内に形成された P型ベース領域 (33)と、下部半導体基板 (51)の上面 (51a)に 隣接して P型ベース領域 (33)内に形成された N型ェミッタ領域 (34)とを備えている。 N 型ェミッタ領域 (34)と N型ベース領域 (30)との間に挟まれた P型ベース領域 (33)の上 には、ゲート絶縁膜 (24)を介してゲート電極 (25)が形成されており、周知のチャネル領 域を形成する。図 2に示すように、ゲート電極 (25)と下部電極層 (5)とを電気的に絶縁 する層間絶縁膜 (26)には、開口部 (26a)が形成され、下部電極層 (5)は、開口部 (26a) を通じて N型ェミッタ領域 (34)と P型ベース領域 (33)に電気的に接続され、ェミッタ電 極を構成する。
[0015] 図 3及び図 4は、下部半導体基板 (51)の上面 (51a)を示す。図 3に示すように、 P型べ ース領域 (33)は、下部半導体基板 (51)の平面方向に対して (平面的に見て）、 N型べ ース領域 (30)内に格子状又はストライプ状に並列して配置されている。また、 N型エミ ッタ領域 (34)は P型ベース領域 (33)の縁部に沿って互いに対抗するように配置されて いる。また、ゲート電極 (25)は、隣り合う P型ベース領域 (33)に跨るように P型ベース領 域 (33)の間にストライプ状に形成されている。これにより、半導体素子の活性領域の 最小単位であるセル (20a)が形成されている。本実施の形態の半導体装置では、 N型 ェミッタ領域 (34)が下部半導体基板 (51)の中央側にのみ形成されており、下部半導 体基板 (51)の外周側には N型ェミッタ領域 (34)が形成されていない。このため、図 4に 示すように、下部 IGBT(l)の上面 (la)には、複数のセル (20a)が形成されたセル形成 領域 (20)と、セル (20a)が形成されていない非形成領域 (44)とが形成される。セル形成 領域 (20)は、下部 IGBT(l)の中央側に形成され、非形成領域 (44)はセル形成領域 (2 0)を包囲するように下部 IGBT(l)の外周側に環状に形成されている。なお、 P型べ一 ス領域 (33)は、 N型ベース領域 (30)内に島状に形成してもよい。
[0016] また、下部半導体基板 (51)の上面 (51a)には、ゲート電極 (25)と離間電極層 (18)とを 電気的に接続するゲートバスライン (43)が下部半導体基板 (51)の周面に沿って形成 される。離間電極層 (18)及びゲートバスライン (43)は、アルミニウム等の導電性金属に より形成され、ストライプ状に形成されたゲート電極 (25)の延長部分を被覆して、ゲー ト電極 (25)と電気的に接続される。即ち、離間電極層 (18)及びゲートバスライン (43)は 、下部半導体基板 (51)の上面 (51a)でポリシリコンとアルミニウムとの積層構造を有す る。
[0017] 上部 IGBT(2)は、平面的に見て、下部 IGBT(l)の上面 (la)及び下面 (lb)と比較して 小さい面積の上面 (2a)及び下面 (2b)を有する。図示しないが、上部 IGBT(2)は、複数 のセルが形成されたセル形成領域 (20)を上面 (52a)に有する上部半導体基板 (52)と、 上部半導体基板 (52)の上面 (52a)に形成されたゲート絶縁膜と、上部半導体基板 (52) の上面 (52a)にゲート絶縁膜を介して形成されたゲート電極と、セルに電気的に接続 された最上部電極層（ェミッタ電極) (27)と、ゲート電極と最上部電極層 (27)とを電気 的に絶縁する層間絶縁膜と、上部半導体基板 (52)の下面 (52b)に形成されたコレクタ 電極 (14)とを有する。上部 IGBT(2)は、下部 IGBT(l)と同様にセル形成領域 (20)を半 導体基板 (52)の中央側にのみ形成してもよ!/、し、セル形成領域 (20)を半導体基板 (52 )の全体に形成してもよい。
[0018] 下部 IGBT(l)の下部電極層 (5)は、 N型ェミッタ領域 (34)と P型ベース領域 (33)とに 電気的に接続される。また、下部電極層 (5)は、平面的に見て、セル形成領域 (20)の 外周側にまで延伸し、非形成領域 (44)の上面の一部も被覆している。上部電極層 (6) は、下部電極層 (5)の上面 (5a)に形成されており、セル形成領域 (20)の外周側にまで 延伸し、平面的に見て、非形成領域 (44)の上面の一部も被覆している。即ち、セル形 成領域 (20)は、平面的に見て、セル形成領域 (20)及び非形成領域 (44)の外周縁より も下部半導体基板 (51)の中心側に配置されて 、る。
[0019] また、少なくとも下部電極層 (5)の上面 (5a)と上部電極層 (6)の上面 (6a)とを異なる材 質により形成し、下部電極層 (5)は、ワイヤ (8)を形成する金属との接着性の高い金属 により上部電極層 (6)に隣接して形成された結線層 (23)を有し、上部電極層 (6)は、半 田 (7)を形成する金属との接着性の高い金属により半田 (7)に隣接して形成された固 着層 (21)を有する。本実施の形態では、図 2に示すように、下部電極層 (5)は、結線層 (23)のみにより構成され、結線層 (23)は、ワイヤ (8)を形成するアルミニウムとの接着性 の高い同じアルミニウム (A1)又はシリコン含有アルミニウムにより形成される。これに対 し、上部電極層 (6)は、半田 (7)との密着性に優れた例えばニッケル (Ni)力も成る固着 層 (21)と、固着層 (21)と下部電極層 (5)との間に形成される例えばチタン (Ή)力も成る 介在層 (22)とを備え、固着層 (21)が上部電極層 (6)の上面 (6a)を形成する。下部電極 層 (5)を上部電極層 (6)と同様に複数の異なる材質力もなる積層構造としてもよい。
[0020] 本実施の形態では、上部電極層 (6)の固着層 (21)を半田 (7)との濡れ性 (相性）に優 れたニッケルにより形成した力 半田 (7)との濡れ性に優れた他の金属材 (例えば金） によって形成してもよい。また、下部電極層 (5)についても、同様にアルミニウム以外 の他の金属を使用してもよい。上部電極層 (6)の介在層 (22)は、固着層 (21)及び下部 電極層 (5)の結線層 (23)の双方の材質との相性により適宜に材質が決定される。
[0021] 保護膜 (9,29)は、 PIF (ポリイミドフィルム）又は PBO (ポリべンズォキサゾール)等の 耐熱性材料により形成され、下部 IGBT(l)に設けられる保護膜 (9)は、下部電極層 (5) の結線領域 (15)を外部に露出する開口部 (19)を有し、上部 IGBT(2)に設けられる保 護膜 (29)は、最上部電極層 (27)の結線領域 (35)を外部に露出する開口部 (39)を有す る。保護膜 (9,29)は、イオン等の不純物から下部 IGBT(l)及び上部 IGBT(2)の半導 体表面を保護する。上部 IGBT(2)の上面 (2a)に形成された最上部電極層 (27)は、下 部電極層 (5)と同様に、ワイヤ (8)を形成する金属との接着性の高い金属により形成さ れる。
[0022] 図 1に示すように、下部電極層 (5)の結線領域 (15)は、下部 IGBT(l)のェミッタ電極 のワイヤ接続領域 (ワイヤボンディングパッド）を構成し、ワイヤ (8)により外部素子等と 接続される。また、保護膜 (9)の開口部 (19)に露出した上部電極層 (6)の上面 (6a)は、 上部 IGBT(2)の半田付け領域 (ダイボンディングパッド)を構成し、上部 IGBT(2)のコ レクタ電極 (14)と電気的に接続される。即ち、上部 IGBT(2)が固着する上部電極層 (6) の固着領域 (16)は、半田付け性に優れたニッケル電極面となり、ワイヤ (8)が接続され る結線領域 (15)は、ワイヤ (8)の接続性に優れたアルミニウム電極面となる。本発明で は、下部 IGBT(l)と上部 IGBT(2)との間に設けられる下部電極層 (5)の上面 (5a)と上 部電極層 (6)の上面 (6a)とを異なる材質により形成するので、上部電極層 (6)の上面 (6a )を半田付け性に優れた材質により形成し、下部電極層 (5)の上面 (5a)をワイヤ (8)との 接続強度の高い材質により形成できる。このため、下部 IGBT(l)と上部 IGBT(2)とを 半田 (7)により良好に固着すると共に、下部 IGBT(l)とワイヤ (8)とを強固に接続して、 信頼性の高い半導体装置 (10)を形成することができる。本発明でいう接着剤は、半田 材、ろう材及び銀ペースト等の接着剤を含み、特に導電性を有することが望ましい。 なお、半田材として、鉛を含まない錫、銀、銅若しくはアルミニウム等の材料力もなる 鉛フリー半田が使用される力 錫及び鉛力 なる一般半田又は他の周知の半田を使 用してもよい。ワイヤ (8)は、例えば金、アルミニウム又はシリコン含有アルミニウムから 成る周知のワイヤが使用できる。 [0023] 図 1の半導体装置 (10)を製造する際に、複数のセル (20a)を形成したセル形成領域 ( 20)を上面 (la)の中央側に設けた下部 IGBT(l)と、下部 IGBT(l)と同様にセル形成領 域を上面 (2a)に設けた上部 IGBT(2)とを形成する。図 3に示すように、下部 IGBT(l) のセル形成領域 (20)は、下部半導体基板 (51)の上面 (51a)の中央側に形成され、セル 形成領域 (20)を包囲して非形成領域 (44)が環状に形成される。下部 IGBT(l)及び上 部 IGBT(2)のような半導体素子の製法は公知であり、説明を省略する。
[0024] 図 5に示すように、アルミニウム力 成る下部電極層 (5)が CVD又は PVD等の蒸着 法、スパッタ法又はメツキ法等の周知の方法により、下部半導体基板 (51)の上面 (51a) に形成される。次に、下部電極層 (5)の上面 (5a)に図示しないエッチングマスクを形成 し、エッチングマスクに形成された開口を通じて、アルミニウムを溶解するリン酸系エツ チング液等のアルミエッチング液により、離間電極層 (18)と下部電極層 (5)との間の離 間部 (37)を含む下部電極層 (5)の不要な部分を除去する。下部電極層 (5)は、平面的 に見て、セル形成領域 (20)の外周側にまで延伸し、非形成領域 (44)の上面の一部も 被覆している。また、離間電極層 (18)は、非形成領域 (44)の上面に形成される。
[0025] 続いて、図 6に示すように、上部電極層 (6)のチタン力も成る介在層 (22)とニッケルか ら成る固着層 (21)とが下部電極層 (5)と同様の方法により、順次に下部電極層 (5)の上 面 (5a)に形成される。この後、図 7に示すように、上部電極層 (6)の上面 (6a)に図示しな いエッチングマスクを形成し、エッチングマスクに形成された開口を通じて、チタンと ニッケルとを同時に溶解する塩酸系エッチング液等の金属エッチング液により上部電 極層 (6)の不要な部分を除去する。異なるエッチング液により、チタンとニッケルとを順 次にエッチングしてもよい。これにより、下部 IGBT(l)の上面 (la)に下部電極層 (5)と上 部電極層 (6)とを積重する。また、エッチングにより上部電極層 (6)に設けた切欠部 (36) により、上部電極層 (6)に被覆されない結線領域 (15)が下部電極層 (5)に形成される。 このとき、上部電極層 (6)は、セル形成領域 (20)の外周縁よりも下部半導体基板 (51)の 外周側、即ち非形成領域 (44)の上側をエッチング除去する。このため、上部電極層 (6 )は、セル形成領域 (20)の外周側にまで延伸し、平面的に見て非形成領域 (44)の上 面の一部も被覆している。また、図 7に示すように、下部電極層 (5)の結線領域 (15)は 、下部半導体基板 (51)のセル形成領域 (20)よりも外側に形成される。 [0026] エッチング液により上部電極層 (6)をエッチングした際に、上部電極層 (6)と共に下部 電極層 (5)が侵蝕されることがあるが、上部電極層 (6)をセル形成領域 (20)の外周縁よ りも下部半導体基板 (51)の外周側でエッチング除去するため、上部電極層 (6)のエツ チングによって電気的特性が損なわれることを防止することができる。また、セル形成 領域 (20)でのセル (20a)のエッチング損傷を防止することができる。即ち、下部電極層 (
5)は、多数のセル (20a)の P型ベース領域 (33)及び N型ェミッタ領域 (34)を相互に電気 的に接続して ヽるため、セル形成領域 (20)の上に形成された下部電極層 (5)がエッチ ングされると、下部 IGBT(l)の電気的特性を損なうおそれがある。これに対し、下部 I GBT(l)のセル形成領域 (20)の外側に延伸する非形成領域 (44)は、ボンディングパッ ドと成る結線領域 (15)等を構成する部分であり、万一上部電極層 (6)のエッチングによ つて侵蝕されることがあっても、電気的特性に影響を受けることが極めて少ない。よつ て、電気的特性が安定して得られる信頼性の高 ヽ半導体装置を形成することができ る。
[0027] 次に、保護膜 (9)により、上部電極層 (6)、離間電極層 (18)及び下部電極層 (5)の一部 を被覆する。保護膜 (9)は、結線領域 (15)と離間電極層 (18)との 2つのボンディングパ ッドと、固着領域 (16)のパッドとに開口部 (19)を有する。図 8に示すように、固着領域 (1
6)の開口部 (19)を通じて、下部 IGBT(l)に上部 IGBT(2)が半田 (7)により固着される。 上部 IGBT(2)〖こは、最上部電極層 (27)、保護膜 (29)及びコレクタ電極 (14)が予め形成 される。図 9に示すように、保護膜 (9)は、下部 IGBT(l)の固着領域 (16)の外周に環状 に形成され、上部 IGBT(2)を固着する際の位置決め効果を有する。この結果、図 1に 示すように、上部 IGBT(2)が下部 IGBT(l)の所定位置に精度よく半田付けされる。ま た、固着領域 (16)を包囲する保護膜 (9)は、半田 (7)の流れ出しを防止できる。この結 果、半田 (7)は、上部電極層 (6)の上面に比較的厚く形成され、半導体装置 (10)を動作 させたときに発生する熱を良好に放熱することができる。
[0028] また、下部半導体基板 (51)の下面 (51b)に形成されたコレクタ電極 (13)は、支持板 (4 5)の上面に半田を介して固着される。更に、図 1に示すように、下部 IGBT(l)及び上 部 IGBT(2)の結線領域 (15,35)と離間電極層 (18)は、図示しな 、外部素子又は外部リ ードに接続されたワイヤ (8)の端部が接続される。これにより、半導体装置 (10)が完成 する。
[0029] 図 10は、図 1に示す半導体装置 (10)により図 11に示す H型ブリッジ回路を単一の 半導体装置で構成した本発明の実施例を示す。 H型ブリッジ回路は、ハイサイド側の 下部 IGBT(l)及び他の下部 IGBT(3)と、ローサイド側の上部 IGBT(2)及び他の上部 I GBT(4)とを備える。下部 IGBT(l)と上部 IGBT(2)との第 1積層体と、他の下部 IGBT( 3)と他の上部 IGBT(4)との第 2積層体とは、放熱性を有する銅又はアルミニウム等の 金属製の支持板 (45)の上に固着される。下部 IGBT(l)力も他の上部 IGBT(4)までの スイッチング動作を制御する制御装置 (40)を備え、制御装置 (40)の表面電極又は支 持板 (45)の周囲に配置された複数の外部リード (42)と、下部 IGBT(l)及び上部 IGBT (2)の結線領域 (ェミッタ電極)（15,35)と離間電極層（ゲート電極)（18)とをワイヤ (8)によ り接続する。図 10に示すように、制御装置 (40)は、第 1積層体と第 2積層体との間で 支持板 (45)上に固着されている。下部 IGBT(l)の下部電極層（ェミッタ電極) (5)と上 部 IGBT(2)のコレクタ電極 (14)との接続点 (A )と、他の下部 IGBT(3)の下部電極層 (
1
ェミッタ電極）と他の上部 IGBT(4)のコレクタ電極との接続点 (A )との間には、交流電
2
流により駆動される例えば冷陰極蛍光放電管である負荷 (41)が接続される。榭脂封 止体 (43)により半導体装置全体が被覆されるが、外部リード (42)は榭脂封止体 (43)か ら外部に導出される。
[0030] H型ブリッジ回路を作動する際に、下部 IGBT(l)及び他の上部 IGBT(4)と、上部 BT(2)及び他の下部 IGBT(3)とを交互にオン ·オフ動作させて、スイッチング作動させ ることにより、接続点 (A )と (A )との間に交互に逆方向の電流を流して、負荷 (41)を作
1 2
動させることができる。このように、下部 IGBT(l)から他の上部 IGBT(4)までのスィッチ ング動作を行ない、直流電圧源を使用し、接続点 (A )と (A )との間に接続された冷陰
1 2
極蛍光放電管を点灯させることができる。図 10に示す半導体装置 (50)によれば、支 持板 (45)の占有面積を減少しつつ集積度を向上できると共に、下部 IGBT(l)と上部 I GBT(2)と、他の下部 IGBT(3)と他の上部 IGBT(4)とを半田 (7)により良好に固着し、 各 IGBT(1,2,3,4)とワイヤ (8)とを強固に接続して、信頼性の高い半導体装置を形成 することができる。
[0031] 本発明の実施の形態は、前記実施の形態に限定されず、種々の変更が可能であ る。例えば、各 IGBT(1,2,3,4)に代えて、他のバイポーラトランジスタ、電界効果トラン ジスタ、サイリスタ又はトライアツク等の半導体素子を構成してもよい。また、図 12に示 すように、保護膜 (9)により下部電極層 (5)の一部を被覆した後に、上部電極層 (6)を下 部電極層 (5)の上面 (5a)に形成してもよい。このよう〖こすると、保護膜 (9)によって下部 電極層 (5)が保護されるため、保護膜 (9)の上方で上部電極層 (6)の不要な部分をエツ チング除去したときに、下部電極層 (5)が侵蝕されるのを良好に防止できる。
産業上の利用可能性
本発明は、複数の半導体素子を積重して形成された半導体装置、冷陰極蛍光放 電管の駆動装置に使用される Hブリッジ回路 (フルブリッジ回路)等を構成する半導 体装置に良好に適用できる。

Claims

請求の範囲
[1] 下部半導体素子と、該下部半導体素子の上面に形成された下部電極層と、該下部 電極層の上面に形成された上部電極層と、該上部電極層の上面に固着された上部 半導体素子と、前記上部電極層と前記上部半導体素子とを固着する接着剤層とを 備え、
前記下部電極層の上面と前記上部電極層の上面とを異なる材質により形成し、 前記上部電極層から外部に部分的に露出する結線領域を前記下部電極層の上面 に設け、
前記結線領域にリード細線の端部を接続したことを特徴とする半導体装置。
[2] 前記上部電極層の上面よりも前記リード細線を形成する金属との接着性の高い金 属により前記下部電極層の上面を形成し、
前記下部電極層の上面よりも前記接着剤層を形成する材料との接着性の高い金 属により前記上部電極層の上面を形成した請求項 1に記載の半導体装置。
[3] 前記下部半導体素子は、複数のセルが形成されたセル形成領域と、セルが形成さ れて 、な 、非形成領域とを前記上面に有し、
前記下部半導体素子の中央側に前記セル形成領域を配置し、
前記セル形成領域を包囲して前記下部半導体素子の外周側に環状に前記非形成 領域を配置し、
前記セル形成領域よりも前記下部半導体素子の外周側に前記上部電極層を延伸 させた請求項 1に記載の半導体装置。
[4] 下部半導体素子の上面に下部電極層を形成する工程と、
前記下部電極層の上面とは異なる材質により成る上面を有する上部電極層を前記 下部電極層の上面に形成する工程と、
前記上部電極層に切欠部を設けて該切欠部を通じて外部に部分的に露出する結 線領域を前記下部電極層の上面に形成する工程と、
接着剤により前記上部電極層の上面に上部半導体素子を固着する工程と、 前記結線領域にリード細線の端部を接続する工程とを含むことを特徴とする半導体 装置の製法。 前記下部半導体素子の上面に複数のセルが形成されたセル形成領域と、セルが 形成されて ヽな ヽ非形成領域とを設ける工程を含み、
前記下部電極層の上面に結線領域を形成する工程は、前記上部電極層を前記セ ル形成領域よりも前記下部半導体素子の内側でエッチング除去する工程を含む請 求項 4に記載の半導体装置の製法。
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CN101040386B (zh) 2010-07-21
US20090166809A1 (en) 2009-07-02
EP1906452A1 (en) 2008-04-02
EP1906452A4 (en) 2008-07-09
CN101040386A (zh) 2007-09-19
US7847316B2 (en) 2010-12-07
EP1906452B1 (en) 2012-08-29

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