CN104064544A - 多芯片半导体功率器件 - Google Patents

多芯片半导体功率器件 Download PDF

Info

Publication number
CN104064544A
CN104064544A CN201410104223.2A CN201410104223A CN104064544A CN 104064544 A CN104064544 A CN 104064544A CN 201410104223 A CN201410104223 A CN 201410104223A CN 104064544 A CN104064544 A CN 104064544A
Authority
CN
China
Prior art keywords
chip
semiconductor
carrier
semiconductor power
power chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410104223.2A
Other languages
English (en)
Inventor
张翠薇
J.赫格劳尔
R.奥特伦巴
X.施勒格尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Publication of CN104064544A publication Critical patent/CN104064544A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/29078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92246—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

一种多芯片半导体功率器件，该半导体器件包括：第一半导体功率芯片，其被安装在第一载体上方；以及第二半导体功率芯片，其被安装在第二载体上方。该半导体器件进一步包括：接触片，其被安装在第一半导体功率芯片的上方以及第二半导体功率芯片上。半导体逻辑芯片被安装在接触片的上方。

Description

多芯片半导体功率器件
技术领域
本发明涉及一种封装技术，并且特别是，本发明涉及针对功率应用以层叠配置封装多个半导体芯片的技术。
背景技术
半导体器件制造商一直在努力提高其产品的性能，同时降低其制造成本。在半导体器件的制造中成本集中区域就是封装半导体芯片。如所属领域的技术人员知道的那样，在晶片上制备集成电路，然后将晶片单体化以产生半导体芯片。随后，可以将半导体芯片安装在诸如例如引线框架的导电载体上。想要以低费用提供小的部件大小的封装方法。
因为这些以及其它原因而存在对于本发明的需要。
发明内容
根据半导体器件的实施例，该半导体器件包括：第一载体，其具有安装表面；第一半导体功率芯片，其被安装在第一载体的安装表面的上方并且具有背对第一载体的第一表面；第二载体，其具有安装表面；以及第二半导体功率芯片，其被安装在第二载体的安装表面的上方并且具有背对第二载体的第一表面。连接元件具有连接到第一半导体功率芯片的第一表面的第一表面和背对该第一表面的安装表面。第三半导体芯片被安装在连接元件的安装表面的上方。
根据半导体器件的另一实施例，该半导体器件包括：第一半导体功率芯片，其被安装在第一载体上方；第二半导体功率芯片，其被安装在第二载体上方；接触片，其被安装在第一半导体功率芯片的上方和第二半导体功率芯片的上方；以及半导体逻辑芯片，其被安装在接触片的上方。
根据制造半导体器件的方法的实施例，该方法包括：将第一半导体功率芯片安装在第一载体上；将第二半导体功率芯片安装在第二载体上；将接触片接合到第一半导体功率芯片并接合到第二半导体功率芯片；以及将第三半导体芯片安装在接触片的上方。
本领域的技术人员在阅读下面的详细描述并且查看随附的附图后将认识到附加的特征和优点。
附图说明
随附的附图被包括以提供实施例的进一步的理解并且被合并在本说明书中并构成本说明书的一部分。附图图解实施例并且与描述一起用来解释实施例的原理。随着参照下面的详细描述而变得更好地理解实施例，将容易领会实施例的许多意图有的优点以及其它的实施例。附图的元件不必是相对于彼此成比例的。同样的参考编号指代相对应的类似部分。
图1示意性地图解示例的功率半导体器件的横截面视图。
图2示意性地图解示例的功率半导体器件的横截面视图。
图3示意性地图解示例的功率半导体器件的横截面视图。
图4示意性地图解示例的功率半导体器件的横截面视图。
图5图解半桥功率半导体器件的基本电路图。
图6示意性地图解示例的半导体功率器件的透视视图。
图7示意性地图解在图6中示出的功率半导体器件沿着线A-A的横截面视图。
图8示意性地图解在图6中示出的功率半导体器件沿着线B-B的横截面视图。
图9图解包括逻辑线路和驱动器线路的半桥功率半导体器件的基本电路图。
图10A－10I示意性地图解封装半导体芯片的方法的示例处理的横截面视图。
图11A－11B示意性地图解封装半导体芯片的方法的示例处理的横截面视图。
具体实施方式
在下面的详细描述中，参考随附的附图，附图构成本说明书的一部分，在附图中以图解的方式示出其中可以实施本发明的具体实施例。在这一点上，参照被描述的（多个）附图的定向，使用诸如“顶”、“底”、“前”、“后”、“上”、“下”等的方向性术语。因为能够以许多不同的定向定位实施例的部件，所以为了图解的目的而使用方向性术语，并且方向性术语绝不是进行限制。应理解可以利用其它实施例，并且可以在不脱离本发明的范围的情况下作出结构或者逻辑的改变。因此，不应以进行限制的意义看待下面的详细描述，并且本发明的范围由所附权利要求限定。
应理解，除非另外地具体表明，否则可以将在此描述的各种示例实施例的特征彼此组合。
如在本说明书中运用的那样，术语“耦接”和/或“连接”并不意指着通常所意指的元件必须直接耦接或者连接在一起。可以在“耦接”或“连接”的元件之间提供居中的元件。然而，尽管不局限于这样的意义，但是还可以将术语“耦接”和/或“连接”理解为可选地公开了如下的方面：元件被直接耦接或者连接在一起而没有被提供在“耦接”或者“连接”的元件之间的居中元件。
在此描述了包含两个或者更多个功率半导体芯片的器件。特别是，可以牵涉具有竖向结构的一个或更多个功率半导体芯片，也就是说，可以以电流能够在垂直于半导体芯片的主表面的方向上流动这样的方式制备出半导体芯片。具有竖向结构的半导体芯片在其两个主表面上，也就是说在其顶侧和底侧上具有电极。
功率半导体芯片可以由诸如例如Si、SiC、SiGe、GaAs、GaN等的特定半导体材料制造，并且更进一步地，可以包含不是半导体的无机和/或有机材料。功率半导体芯片可以是不同类型的，并且可以由不同的技术制造。
更进一步地，在此描述的电子器件可以包括一个或者更多个逻辑集成电路，以控制功率半导体芯片。逻辑集成电路可以包括一个或者更多个驱动器电路，以驱动功率半导体芯片中的一个或者更多个。逻辑集成电路例如可以是包括例如存储器电路、电平转换器等的微控制器。
功率半导体芯片可以具有电极（芯片焊盘），电极允许作出与包括在半导体芯片中的集成电路的电接触。电极可以包括施加到半导体芯片的半导体材料的一个或者更多个金属层。可以制造具有任意想要的几何形状和任意想要的材料成分的金属层。例如，金属层可以是覆盖区域的层或者岛的形状。以举例子的方式，可以将能够形成焊料接合或者扩散焊料接合的任意想要的金属，例如，Cu、Ni、NiSn、Au、Ag、Pt、Pd、In、Sn和这些金属中的一个或者更多个的合金用作为材料。金属层不必是同质的或者不必仅由一种材料制造，也就是说，在金属层中可以包含各种成分和浓度的材料。
竖向的功率半导体芯片例如可以被配置为功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结栅极场效应晶体管）、功率双极晶体管或者功率二极管。以举例子的方式，功率MOSFET的源极接触电极和栅极接触电极可以被置于一个主表面上，而功率MOSFET的漏极接触电极可以被布置在另一个主表面上。
两个或者更多个半导体功率芯片被安装在载体上方。在一个实施例中，载体的每一个可以是诸如例如引线框架的管芯焊盘的金属板或者金属片。金属板或者金属片可以由任意的金属或者金属合金（例如，铜或者铜合金）制成。在其它实施例中，芯片载体可以由塑料或者陶瓷制成。例如，芯片载体可以包括涂覆有金属层的塑料层。以举例子的方式，这样的芯片载体可以是单层PCB或者是多层PCB。PCB可以具有至少一个绝缘层和附接至该绝缘层的被结构化的金属箔层。绝缘层可以包括环氧树脂、聚四氟乙烯、芳族聚酸胺纤维或碳纤维或者基于这些制成，并且可以包括诸如例如玻璃纤维或者碳纤维的纤维毡的增强单元。在其它实施例中，器件载体可以包括涂覆有金属层的陶瓷板，例如，金属接合的陶瓷衬底。以举例子的方式，器件载体可以是DCB（直接铜接合）陶瓷衬底。
两个或者更多个半导体功率芯片可以至少部分地被包围在或者嵌入在至少一个电绝缘材料中。电绝缘材料形成密封体。密封体可以包括模制材料或者由模制材料制成。可以运用各种技术以形成模制材料的密封体，例如，压缩模制、注入模制、粉末模制或者液体模制。进一步地，密封体可以具有一块层，例如，层叠在（多个）功率半导体芯片和（多个）载体的顶部上的一块片或者一块箔的形状。密封体可以形成封装的外周的一部分，即，可以至少部分地限定半导体器件的形状。
电绝缘材料可以包括热固性材料或者热塑性材料或者由热固性材料或者热塑性材料制成。可以例如基于环氧树脂制来造热固性材料。热塑性材料可以例如包括聚醚酰亚胺（PEI）、聚醚砜（PES）、聚苯硫醚（PPS）或者聚酰胺－酰亚胺（PAI）的组中的一个或者更多个材料。热塑性材料在模制或者层叠期间由于压力和热的施加而熔化，并且（可逆地）在冷却和释放压力时硬化。
形成密封体的电绝缘材料可以包括聚合物材料或者由聚合物材料制成。电绝缘材料可以包括如下中的至少一个：填充或者非填充的模制材料、填充或者非填充的热塑性材料、填充或者非填充的热固性材料、填充或者非填充的层叠、纤维增强的层叠、纤维增强的聚合物层叠、以及具有填料颗粒的纤维增强的聚合物层叠。
在一些实施例中，电绝缘材料可以是层叠，例如，聚合物箔或者聚合物片。可以施加适合于将聚合物箔或者聚合物片附接至下方结构的时间的热和压力。在层叠期间，电绝缘箔或者电绝缘片能够流动（即，处于塑性状态），导致芯片载体上的功率半导体芯片与/或其它拓扑结构之间的间隙被填充有电绝缘箔或者电绝缘片的聚合物材料。电绝缘箔或者电绝缘片可以包括任意适当的热塑性材料或者热固性材料或者由任意适当的热塑性材料或者热固性材料制成。在一个实施例中，绝缘箔或者绝缘片可以包括预浸料（预浸纤维的简称）或者由预浸料制成，即，例如，由例如玻璃纤维或者碳纤维的纤维毡以及例如热固性材料或者热塑性材料的树脂的组合而制成。预浸料材料在本领域中是周知的，并且典型地用于制造PCB（印刷电路板）。
提供诸如例如接触片的连接元件，以将第一半导体功率芯片的负载电极电连接到第二半导体功率芯片的负载电极。连接元件可以具有背对第一和第二半导体功率芯片的、并且被配置成用作为用于至少一个逻辑半导体芯片的安装表面的上安装表面。
可以设计多种不同类型的电子器件以使用在此描述的接触片，也可以通过在此描述的技术制造多种不同类型的电子器件。以举例子的方式，依照本公开的电子器件可以构成包含两个或者更多个功率半导体芯片（例如，MOSFET）以及一个或者更多个逻辑集成电路的电源。例如，在此公开的电子器件可以包括半桥电路，该半桥电路包括高侧晶体管、低侧晶体管以及逻辑集成电路芯片。逻辑集成电路芯片可以可选地包括一个或者多个晶体管驱动器线路。
例如可以在用于将DC或AC电压变换成DC电压的电子电路（分别为所谓的DC-DC变换器和AC-DC变换器）中实现在此公开的半桥电路。DC-DC变换器可以用于将电池或者可再充电的电池提供的DC输入电压变换成与在下游连接的电子电路的要求匹配的DC输出电压。以举例子的方式，在此描述的DC-DC变换器可以是降压变换器或者下变换器。AC－DC变换器可以用于将例如由高压AC电网提供的AC输入电压变换成与在下游连接的电子电路的要求匹配的DC输出电压。
图1图解示例的半导体器件100的横截面视图。半导体器件100可以包括：第一载体110、第二载体120、第一半导体功率芯片130、第二半导体功率芯片140、在下面被称为接触片150的导电连接元件150、以及第三半导体芯片160。第三半导体芯片160不是功率芯片。其可以是例如逻辑集成电路，该逻辑集成电路被配置成控制第一半导体功率芯片130和第二半导体功率芯片140中的一个或这两者。
第一载体110和第二载体120的每一个可以由平坦金属板，例如，引线框架的管芯焊盘制成。第一载体110和第二载体120可以被彼此并排布置。第一载体110和第二载体120可以被断开或者是分隔开的。因此，例如在第一载体110与第二载体120之间不存在直接电连接。
第一载体110的底表面112和第二载体120的底表面122可以形成半导体器件100的被配置成连接至诸如例如应用板（未示出）的外部应用的外部接触焊盘。以举例子的方式，底表面112和底表面122可以是共面的，并且例如可以限定半导体器件100的安装表面。
第一载体110具有安装表面111，并且第二载体120具有安装表面121。第一半导体功率芯片130可以在其底表面背对第一载体110的情况下安装在第一载体110的安装表面111上。第二半导体功率芯片140可以在其底表面背对第二载体120的情况下安装在第二载体120的安装表面121上。
第一载体110的安装表面111和第二载体120的安装表面121可以是共面的。即，第一半导体功率芯片130和第二半导体功率芯片140可以例如基本上被布置在半导体器件100中的同一个器件平面上（在下面称为“功率平面”）。
接触片150具有面对第一半导体功率芯片130和第二半导体功率芯片140的底表面151。更具体地，第一半导体功率芯片130可以具有背对第一载体110且被接合至接触片150的底表面151的第一表面131，并且第二半导体功率芯片140可以具有背对第二载体120且被接合至接触片150的底表面151的第一表面141。
接触片150可以具有与底表面151相对的安装表面152。第三半导体芯片160被安装在接触片150的安装表面152上方。因此，第三半导体芯片160被布置在器件平面中（在下面称为“逻辑平面”），该器件平面被布置在由半导体功率芯片130、140限定的“功率平面”上方。这两个平面可以至少由在“功率平面”与“逻辑平面”之间延伸的接触片150间隔开。
应注意，例如逻辑芯片160的一个或者多个第三半导体芯片可以在“逻辑平面”中被布置在接触片150上。在一些实施例中，没有半导体功率芯片被布置在接触片150上或者“逻辑平面”中。另一表面，在一些实施例中，没有半导体逻辑芯片被布置在“功率平面”中。
一般说来，在一些实施例中，半导体器件100的“功率平面”可以排它地包含半导体功率芯片。进一步地，在一些实施例中，半导体器件100的“逻辑平面”可以排它地包含半导体逻辑芯片。这样，可以保证通过接触片150将逻辑半导体芯片160与半导体功率芯片130、140在几何形状上分离并且热分离。由于热主要在半导体功率芯片130、140中生成，并且经由第一载体110和第二载体120到例如应用板（未示出）来最有效地执行热传递，因此获得第一和第二半导体功率芯片130、140到环境的非常有效的热耦接。另一方面，通过接触片150将可以是逻辑半导体芯片的第三半导体芯片160与“功率平面”热分离或者隔离。由于与功率半导体芯片相比，逻辑半导体芯片典型地对于高温暴露更灵敏，因此，着眼于高的热鲁棒性和小的封装大小，将功率芯片和逻辑芯片分离成两个不同平面以及例如通过接触片150来对这些平面热去耦对于功率应用而言提供了有效的封装设想。
进一步地，如在本领域中周知的那样，半导体功率器件100的最大负载、性能以及寿命关键地取决于被包含在半导体器件100中的半导体功率芯片130、140的工作温度。由于这一原因，上面所解释并且例如以图1示范的构筑设想可以改善半导体器件100的最大负载、性能和寿命。
图2图解具有例如与半导体器件100相同的配置的半导体器件200。然而，半导体器件200可以附加地包括形成密封体210的电绝缘材料，例如，模制材料。密封体210可以嵌入有第一和第二载体110、120；第一和第二半导体功率芯片130、140；接触片150以及第三半导体芯片160。
以举例子的方式，如图2中图解那样，半导体器件200可以具有无引线封装。半导体器件200可以具有在例如5 mm到15 mm之间的范围内、更具体地在例如7 mm到13 mm之间的范围内的横向尺寸或者宽度W。半导体器件200可以具有在例如0.5 mm到5 mm之间的范围内、更特别地在1 mm到2 mm之间的范围内的竖向尺寸或者高度H。在第一半导体芯片130的横向外部轮廓132上方或者在第二半导体芯片140的横向外部轮廓142上方、或是如图1和2中图解那样在第一和第二半导体芯片130、140这两者的横向外部轮廓132、142上方，接触片150可以例如在至少一个横向尺寸上突出。接触片150可以具有大于W的例如60％、70％、80％、90％的横向延伸Wc。接触片150可以具有在例如0.1 mm到1.0 mm之间的范围内、特别是在例如0.15 mm到3 mm之间的范围内的竖向尺寸Hc。第一载体110的竖向尺寸和第二载体120的竖向尺寸可以例如相等。第一载体110的竖向尺寸和/或第二载体120的竖向尺寸可以在等于或者小于例如±0.2 mm或者±0.1 mm的容差内等于Hc。
结合图1和图2的描述可以应用于在此描述的所有实施例。特别是，上面列出的尺寸量可应用于其它实施例。
在图1和图2中，可以在半导体功率器件100、200中实现所谓的半桥电路。第一半导体芯片130可以形成低侧功率开关，并且第二半导体芯片140可以形成半桥的高侧功率开关。第三半导体芯片160（例如逻辑集成电路）可以分别控制低侧功率半导体芯片130和高侧功率半导体芯片140的栅极电极（未图解）。
第一半导体功率芯片130和/或第二半导体功率芯片140可以例如是MOSFET。高侧第二功率半导体芯片140的源极电极可以连接到接触片150。接触片150可以连接到低侧第一半导体功率芯片130的漏极电极。低侧第一半导体功率芯片130的源极电极可以连接到第一载体110。因此，低侧第一半导体功率芯片130可以以源极向下的定向被布置在半导体器件100、200中。相反，高侧第二半导体功率芯片140可以以源极向上的定向的被定向，即，其漏极电极可以被连接到第二载体120。
图3图解功率半导体器件300。除了接触片250被接合到第二载体120而不是接合到第二半导体芯片140以外，功率半导体器件300可以类似于功率半导体器件100。为此目的，接触片210可以被提供有例如弯曲部250a或者突起，如图3中图解的那样。
在功率半导体器件300中，低侧第一半导体功率芯片130可以以源极向上的定向被布置在第一载体110上，并且高侧第二半导体功率芯片140也可以以源极向上的定向被布置在第二载体120上。
类似于结合图1和图2描述的那样，第三半导体芯片160被布置在接触片250之上，并且第一半导体芯片130和第二半导体芯片140被布置在接触片250的主延伸下面的平面中。为了避免重复，请参照上面的相对应的描述。
图4图解示例的功率半导体器件400。除了如结合图2描述的那样施加了电绝缘材料210，例如模制材料以外，功率半导体器件400类似于功率半导体器件300。为了避免重复，请参照图2的相对应的描述。
如已经提及的那样，在此描述的半导体器件可以例如用作半桥。图5示出被布置在两个节点N1和N2之间的半桥500的基本电路。半桥500包括串联连接的两个开关S1和S2。可以将该第一半导体功率芯片130实现为低侧开关S1，并且将第二半导体功率芯片140实现为高侧开关S2。然后，与图1到图4示出的半导体器件100到400相比，节点N1可以是第一半导体功率芯片130的源极电极，节点N2可以是第二半导体功率芯片140的漏极电极，布置在两个开关S1和S2之间的节点N3可以是接触片150。
施加在节点N1与N2之间的电压可以等于或者大于30 V、50 V、100 V、300 V、500 V、1000 V。特别是，如果功率半导体器件500是例如DC-DC变换器，则施加在节点N1与N2之间的电压可以在例如30V到150 V之间的范围内。进一步地，如果功率半导体器件500是AC－DC变换器，则施加在节点N1与N2之间的电压可以在例如300V到1000 V之间的范围内。
以举例子的方式，图6到图8图解功率半导体器件600。功率半导体器件600还可以例如被实现为DC－DC变换器、AC－DC变换器或者另外的电源。进一步地，如上面结合图1和图2解释的那样，功率半导体器件100和200的全部设想和细节均可以被应用于功率半导体器件600，并且为了避免重复，请参照在此的公开。
更具体地，采用如上面示范那样的布置的功率半导体器件600包括：第一载体110、第二载体120、第一半导体芯片130、第二半导体芯片140、接触片150以及第三半导体芯片160。进一步地，功率半导体器件600可以包括被挨着第一载体110布置的第三载体170。诸如例如第一半导体芯片130的栅极电极的芯片电极可以被连接到第三载体170。
进一步地，功率半导体器件600可以包括第四半导体芯片660。第四半导体芯片660可以被安装在接触片150的安装表面152上方或者安装在接触片150的安装表面152上。第四半导体芯片660可以例如包括一个或者两个栅极驱动器，如将结合图9更详细地解释的那样。还可以是用以驱动第一半导体功率芯片130和第二半导体功率芯片140的栅极的栅极驱动器被集成到第三半导体芯片160中，该第三半导体芯片160包括逻辑以控制栅极驱动器。
如在图7中显见的那样，接触片150可以在横向方向上延伸超出第一半导体功率芯片130的外部轮廓132，并且可以被接合到第四载体180。第四载体180可以用作为仅用于接触片150而例如不用于半导体功率芯片130、140的载体。第一、第二、第三和第四载体110、120、170、180可以基本上是共面的。它们可以例如形成功率半导体器件600的外部端子。更具体地，载体110、120、170、180可以例如被暴露在功率半导体器件600的底部。
进一步地，如在图6到图8中显见的那样，可以在功率半导体器件600的外周布置包括端子焊盘190a、190b的许多端子焊盘。端子焊盘190a、190b可以经由例如接合线连接到第三半导体芯片160的电极和/或连接到第四半导体芯片660的电极。进一步地，它们可以经由例如接合线连接到例如第一半导体功率芯片130的栅极电极和/或连接到第二半导体功率芯片140的栅极电极。接合线还可以用于将第四半导体芯片660（或者第三半导体芯片160）电连接到第一半导体功率芯片110或者电连接到第二半导体功率芯片120，例如连接到其栅极电极。
可以通过被布置在接触片150的安装表面152与第三半导体芯片160和/或第四半导体芯片660的底表面之间的绝缘层（未示出），来将“逻辑平面”的第三半导体芯片160和第四半导体芯片660与接触片150电绝缘。该绝缘层可以包括例如聚合物材料或者由例如聚合物材料制成。绝缘层可以具有大于例如100 V、500 V、1000 V或甚至10 kV的介电强度。这样，绝缘层可以用来使“逻辑平面”对“功率平面”电隔离。
图9是图5中示出的线路的示例的、更详细的图解，并且可应用于在此描述的功率半导体器件100－600。如上面解释的那样，开关S1可以由低侧（LS）MOSFET实现，并且开关S2可以由高侧（HS）MOSFET实现。LS MOSFET S1的栅极由栅极驱动器D1驱动，并且HS MOSFET S2的栅极由栅极驱动器D2驱动。栅极驱动器D1和D2由逻辑控制，该逻辑可以在第三半导体芯片160中实现。第三半导体芯片160可以具有接收例如PWM（脉冲宽度调制）信号的输入160a。
以举例子的方式，栅极驱动器D1和D2可以在一个半导体芯片中实现，例如，在第四半导体芯片660中实现。在其它实施例中，栅极驱动器D1在单个半导体芯片中实现，并且栅极驱动器D2在单个半导体芯片中实现，导致“逻辑平面”可能包括至少三个半导体芯片（一个逻辑芯片、两个栅极驱动器芯片）。进一步地，还可能是栅极驱动器D1和D2被集成在第三半导体芯片160中，该第三半导体芯片160实现逻辑。在这种情况下，仅一个半导体芯片，即，第三半导体芯片160可以被布置在上方，并且可以例如被接合到接触片150的安装表面152，即，可以被包含在“逻辑平面”中。
以举例子的方式，图10A－10I图解制造半导体功率器件1000的示例方法的各阶段。如图10I所示，半导体功率器件100类似于半导体功率器件100－600，并且为了避免重复，请参照在此的相对应的描述。
图10A图解提供第一载体110、第二载体120以及例如第四载体180。如上面提及的那样，所有载体110、120、180均可以分别具有彼此共面的上表面和/或下表面。
根据图10B，可以将接合材料1010沉积在第一载体110的安装表面111上以及沉积在第二载体120的安装表面121上。接合材料1010可以例如包括如下或者由如下构成：焊料、软焊料、扩散焊料、膏、纳米胶或者导电接合剂。在第一载体110上和在第二载体120上沉积接合材料1010可以被并行地执行，即，在一个沉积步骤内执行。还可以以批量处理的方式，即，针对被并行地制造的多个半导体功率器件1000来执行沉积。
更具体地，接合材料1010可以例如由诸如例如Au、Sn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi、Sn或者Au的焊料材料制成，或者由包含分布在聚合物材料或诸如例如α松油醇的树脂中的金属颗粒的膏制成。被包含在膏中的金属颗粒可以例如由银、金、铜、锡或者镍制成。金属颗粒的延伸（平均直径）可以例如小于100 nm，并且特别是小于50 nm。在本领域中，还可以将这些膏称为纳米胶。
如图10C中所示，在第一载体110上方，第一半导体功率芯片130被放置在接合材料1010上，并且在第二载体120上方，第二半导体功率芯片140被放置在接合材料1010上方。
参照图10D，接合材料1010被沉积在第一半导体功率芯片130的第一表面131上以及在第二半导体功率芯片140的第一表面141上。进一步地，接合材料1010可以被沉积在第四载体180上。在第四载体180上和在第一及第二半导体功率芯片130、140上沉积接合材料1010可以被并行地执行，即在一个沉积步骤内执行。还可以以批量处理的方式，即，针对被并行地制造的多个半导体功率器件1000来执行沉积。
参照图10E，接触片150被放置在在图10D中沉积的接合材料1010的上方。将接触片150放置在第一半导体功率芯片130上方以及第二半导体功率芯片140上方可以以批量处理的方式执行。
参照图10F，施加能量以使接合材料1010回流、烧结或者固化。可以通过加热、辐照等来施加能量。以举例子的方式，可以在烘炉中施加热。通过施加能量，例如焊料、金属膏、导电接合剂的接合材料1010可以电地并且机械地将第一和第二载体110、120分别连接到第一和第二半导体功率芯片130、140，并且将第一和第二半导体功率芯片130、140连接到接触片150，并且例如将第四载体180连接到接触片150。
参考图10G，接合剂材料1020被沉积在接触片150的安装表面152上。接合剂材料1020可以例如与接合材料1010相同。接合剂材料1020可以是导电的，或者可以是电绝缘的。进一步地，应注意，可以由绝缘层（未示出）来涂覆接触片150的安装表面152，如上描述的那样。
参照图10H，第三半导体芯片160被放置在接合剂材料1020上。进一步地，在该处理阶段，可以将诸如例如第四半导体芯片660（未示出）的附加半导体芯片放置在接合剂材料1020上。可以并行地，并且可选地以批量处理的方式执行芯片放置。
然后，如图10I中图解的那样，对接合剂材料1020进行性质转变，以将第三半导体芯片160（以及例如附加的半导体芯片，诸如例如半导体芯片660）接合到接触片150的安装表面152。该性质转变可以由施加能量，例如热或者辐照引起。如果接合剂材料1020是与接合材料1010相似的焊料材料，则可以在回流处理中使用例如烘炉来施加能量。否则，如果接合剂材料1020是绝缘接合剂材料，诸如例如树脂，则可以通过施加能量来固化接合剂材料1020。
图11A和图11B图解制造如在图10I中图解的那样的半导体器件1000的方法的各阶段。替代如在图10F－10H中示出的处理，以举例子的方式，可以执行在图11A和11B中图解的处理。
更具体地，省略结合图10F解释的第一回流处理。替代地，将接合剂材料1020放置在接触片150的安装表面152上，如上面结合图10H解释的那样。
参照图11B，将第三半导体芯片160（以及例如，附加的半导体芯片，诸如例如半导体芯片660）放置在接合剂材料1020上。
然后，对图11B所示的布置施加能量，以回流或者固化接合材料1010，并且回流或者固化接合剂材料1020。因此，依照图11A和11B中图解的处理阶段，为了得到如图10I中图解的半导体器件1000，只需要单次能量施加处理（例如，加热和/或辐照）。
应注意，在此公开的实施例均实现（至少）两平面的构筑设想，即，设置下“功率平面”和上“逻辑平面”，其中各平面被接触片150分离开。在为了有效率地进行热耗散而可以把下“功率平面”放在载体的附近的同时，可以将“逻辑平面”的半导体芯片160、660放在例如功率半导体芯片的横向外部轮廓132、142之内、或者例如接触片150的轮廓之内的区域中，从而允许提供具有小的占位面积和高的热效率或鲁棒性的紧凑的功率半导体器件封装。
尽管已经在此图解并且描述了具体实施例，但是本领域的普通技术人员将领会，可以在不脱离本发明的范围的情况下，可由多种替换和/或等同的实现代替所示出并描述的具体实施例。本申请意图覆盖在此讨论的具体实施例的任意的适配或改变。因此，意图只由权利要求及其等同物来限制本发明。

Claims (22)

1.一种半导体器件，包括：
第一载体，其具有安装表面；
第一半导体功率芯片，其被安装在所述第一载体的安装表面的上方并且具有背对所述第一载体的第一表面；
第二载体，其具有安装表面；
第二半导体功率芯片，其被安装在所述第二载体的安装表面的上方并且具有背对所述第二载体的第一表面；
连接元件，其具有第一表面，以及背对该第一表面的安装表面，所述连接元件的第一表面连接到所述第一半导体功率芯片的第一表面；以及
第三半导体芯片，其被安装在所述连接元件的安装表面的上方。
2.根据权利要求1所述的半导体器件，其中所述连接元件是接触片。
3.根据权利要求1所述的半导体器件，其中所述连接元件的第一表面连接到所述第二半导体功率芯片的第一表面。
4.根据权利要求1所述的半导体器件，其中所述第一载体和所述第二载体被彼此并排布置。
5.根据权利要求1所述的半导体器件，其中所述第一载体的安装表面和所述第二载体的安装表面是共面的。
6.根据权利要求1所述的半导体器件，其中所述第三半导体芯片是逻辑芯片。
7.根据权利要求1所述的半导体器件，进一步包括：
绝缘层，其被布置在所述连接元件的安装表面与所述第三半导体芯片之间。
8.根据权利要求4所述的半导体器件，其中所述第一半导体功率芯片具有被连接到所述第一载体的安装表面的源极电极。
9.根据权利要求1所述的半导体器件，其中所述第一载体和所述第二载体被彼此电断开。
10.根据权利要求1所述的半导体器件，进一步包括：
外部端子焊盘，其与所述第一载体或者与所述第二载体并排地布置，其中所述连接元件连接到所述外部端子焊盘。
11.根据权利要求10所述的半导体器件，其中所述外部端子焊盘形成无引线封装外部接触区域。
12.根据权利要求1所述的半导体器件，其中所述第一载体的与所述第一载体的安装表面相对的表面、或者所述第二载体的与所述第二载体的安装表面相对的表面形成无引线封装外部接触区域。
13.根据权利要求1所述的半导体器件，其中所述半导体器件是DC-DC变换器或者AC-DC变换器。
14.一种半导体器件，包括：
第一半导体功率芯片，其被安装在第一载体上方；
第二半导体功率芯片，其被安装在第二载体上方；
接触片，其被安装在所述第一半导体功率芯片的上方以及所述第二半导体功率芯片的上方；以及
半导体逻辑芯片，其被安装在所述接触片的上方。
15.根据权利要求14所述的半导体器件，其中所述接触片在至少一个横向方向上具有超出所述第一半导体功率芯片的横向外部轮廓和所述第二半导体功率芯片的横向外部轮廓中的至少一个而突出的延伸。
16.根据权利要求14所述的半导体器件，其中所述第一载体和所述第二载体是共面的。
17.根据权利要求14所述的半导体器件，其中所述第一载体和所述第二载体是引线框架的芯片焊盘。
18.一种制造半导体器件的方法，所述方法包括：
将第一半导体功率芯片安装在第一载体上；
将第二半导体功率芯片安装在第二载体上；
将接触片接合到所述第一半导体功率芯片并接合到所述第二半导体功率芯片；以及
将第三半导体芯片安装在所述接触片的上方。
19.根据权利要求18所述的方法，进一步包括：
将第一接合物沉积在所述第一载体上；
将所述第一半导体功率芯片放置在所述第一接合物上；
将第二接合物沉积在所述第二载体上；
将所述第二半导体功率芯片放置在所述第二接合物上；
将第三接合物沉积在所述接触片上；
将所述第三半导体芯片放置在所述第三接合物上；以及
施加能量以安装所述第一半导体功率芯片、所述第二半导体功率芯片和所述第三半导体芯片。
20.根据权利要求18所述的方法，进一步包括：
将第一接合物沉积在所述第一载体上；
将所述第一半导体功率芯片放置在所述第一接合物上；
将第二接合物沉积在所述第二载体上；
将所述第二半导体功率芯片放置在所述第二接合物上；
施加能量以安装所述第一半导体功率芯片和所述第二半导体功率芯片；
在安装了所述第一和第二半导体功率芯片后，将第三接合物沉积在所述接触片上；
将所述第三半导体芯片放置在所述第三接合物上；以及
施加能量以将所述第三半导体芯片安装到所述接触片。
21.根据权利要求18所述的方法，进一步包括：
施加被配置成将所述第三半导体芯片电连接到所述第一半导体功率芯片或者连接到所述第二半导体功率芯片的接合线。
22.根据权利要求18所述的方法，进一步包括：
利用密封材料至少部分地覆盖所述第一半导体功率芯片、所述第二半导体功率芯片、所述接触片和所述第三半导体芯片。
CN201410104223.2A 2013-03-20 2014-03-20 多芯片半导体功率器件 Pending CN104064544A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/847,681 US9515060B2 (en) 2013-03-20 2013-03-20 Multi-chip semiconductor power device
US13/847681 2013-03-20

Publications (1)

Publication Number Publication Date
CN104064544A true CN104064544A (zh) 2014-09-24

Family

ID=51484846

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410104223.2A Pending CN104064544A (zh) 2013-03-20 2014-03-20 多芯片半导体功率器件

Country Status (3)

Country Link
US (3) US9515060B2 (zh)
CN (1) CN104064544A (zh)
DE (1) DE102014103773B4 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108323211A (zh) * 2018-01-26 2018-07-24 香港应用科技研究院有限公司 功率器件封装

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
US9147631B2 (en) * 2013-04-17 2015-09-29 Infineon Technologies Austria Ag Semiconductor power device having a heat sink
JP5799974B2 (ja) * 2013-05-23 2015-10-28 株式会社デンソー 電子装置
US9006870B2 (en) * 2013-07-31 2015-04-14 Alpha & Omega Semiconductor Inc. Stacked multi-chip packaging structure and manufacturing method thereof
US9653386B2 (en) * 2014-10-16 2017-05-16 Infineon Technologies Americas Corp. Compact multi-die power semiconductor package
US9171788B1 (en) * 2014-09-30 2015-10-27 Alpha And Omega Semiconductor Incorporated Semiconductor package with small gate clip and assembly method
CN104600061A (zh) * 2014-12-30 2015-05-06 杰群电子科技（东莞）有限公司 一种半导体芯片的堆叠式3d封装结构
DE102015106148A1 (de) * 2015-04-22 2016-10-27 Infineon Technologies Austria Ag Vorrichtung mit einem logischen Halbleiterchip mit einer Kontaktelektrode für Clip-Bonding
DE102016101433A1 (de) * 2016-01-27 2017-07-27 Infineon Technologies Ag Multi-Chip-Halbleiterleistungsgehäuse
US10269702B2 (en) 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US9941193B1 (en) * 2016-09-30 2018-04-10 Infineon Technologies Americas Corp. Semiconductor device package having solder-mounted conductive clip on leadframe
EP3385981A1 (en) * 2017-04-04 2018-10-10 Nexperia B.V. Power apparatus
US10784213B2 (en) * 2018-01-26 2020-09-22 Hong Kong Applied Science and Technology Research Institute Company Limited Power device package
US10777489B2 (en) * 2018-05-29 2020-09-15 Katoh Electric Co., Ltd. Semiconductor module
US11145575B2 (en) * 2018-11-07 2021-10-12 UTAC Headquarters Pte. Ltd. Conductive bonding layer with spacers between a package substrate and chip
EP4044225A1 (en) * 2021-02-16 2022-08-17 Nexperia B.V. A semiconductor device and a method of manufacturing a semiconductor device
US11211373B1 (en) * 2021-02-22 2021-12-28 United Silicon Carbide, Inc. Double-sided chip stack assembly

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060208348A1 (en) * 2005-03-18 2006-09-21 Tohru Ohsaka Stacked semiconductor package
US7612459B2 (en) * 2004-07-26 2009-11-03 Sun Microsystems, Inc. Multi-chip module and single-chip module for chips and proximity connectors
US7804131B2 (en) * 2006-04-28 2010-09-28 International Rectifier Corporation Multi-chip module
CN102760724A (zh) * 2011-04-29 2012-10-31 万国半导体股份有限公司 一种联合封装的功率半导体器件
US20120326287A1 (en) * 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US20130043582A1 (en) * 2011-08-15 2013-02-21 Tessera, Inc. Multiple die in a face down package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10301091B4 (de) 2003-01-14 2015-01-22 Infineon Technologies Ag Leistungs-Halbleiterbauelement und Verfahren zur Verbindung von einem gemeinsamen Substratträger zugeordneten Halbleitereinrichtungen
US7750451B2 (en) * 2007-02-07 2010-07-06 Stats Chippac Ltd. Multi-chip package system with multiple substrates
US7851908B2 (en) 2007-06-27 2010-12-14 Infineon Technologies Ag Semiconductor device
US7800208B2 (en) 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
KR20090062612A (ko) * 2007-12-13 2009-06-17 페어차일드코리아반도체 주식회사 멀티 칩 패키지
US20120228696A1 (en) * 2011-03-07 2012-09-13 Texas Instruments Incorporated Stacked die power converter
US9048338B2 (en) * 2011-11-04 2015-06-02 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
US8704384B2 (en) * 2012-02-17 2014-04-22 Xilinx, Inc. Stacked die assembly

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612459B2 (en) * 2004-07-26 2009-11-03 Sun Microsystems, Inc. Multi-chip module and single-chip module for chips and proximity connectors
US20060208348A1 (en) * 2005-03-18 2006-09-21 Tohru Ohsaka Stacked semiconductor package
US7804131B2 (en) * 2006-04-28 2010-09-28 International Rectifier Corporation Multi-chip module
CN102760724A (zh) * 2011-04-29 2012-10-31 万国半导体股份有限公司 一种联合封装的功率半导体器件
US20120326287A1 (en) * 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US20130043582A1 (en) * 2011-08-15 2013-02-21 Tessera, Inc. Multiple die in a face down package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108323211A (zh) * 2018-01-26 2018-07-24 香港应用科技研究院有限公司 功率器件封装
CN108323211B (zh) * 2018-01-26 2021-06-15 香港应用科技研究院有限公司 功率器件封装

Also Published As

Publication number Publication date
US20140284777A1 (en) 2014-09-25
US9515060B2 (en) 2016-12-06
DE102014103773B4 (de) 2020-07-16
US20170047315A1 (en) 2017-02-16
DE102014103773A1 (de) 2014-09-25
US20200083207A1 (en) 2020-03-12

Similar Documents

Publication Publication Date Title
CN104064544A (zh) 多芯片半导体功率器件
US9018744B2 (en) Semiconductor device having a clip contact
US10256119B2 (en) Method of manufacturing a semiconductor power package
US8916968B2 (en) Multichip power semiconductor device
EP3130009B1 (en) Dc-dc converter having terminals of semiconductor chips
JP6115738B2 (ja) 半導体装置およびその製造方法
CN104465557A (zh) 电子功率器件和制作电子功率器件的方法
US9147631B2 (en) Semiconductor power device having a heat sink
CN104303299B (zh) 半导体装置的制造方法及半导体装置
CN105023920A (zh) 包括多个半导体芯片和多个载体的器件
CN105845661A (zh) 在封装结构下方具有芯片的半导体装置
KR101014915B1 (ko) 반도체 패키지 및 그 제조 방법
CN104810343B (zh) 具有多个接触夹片的半导体器件
CN104620372A (zh) 半导体装置
CN104810330A (zh) 电子器件和用于制作电子器件的方法
CN104051397B (zh) 包括非整数引线间距的封装器件及其制造方法
JP6534677B2 (ja) スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ
CN106024773B (zh) 包括多层级载体的化合物半导体装置
CN104037152B (zh) 芯片载体结构、芯片封装及其制造方法
CN106067458A (zh) 包括具有用于线夹结合的接触电极的逻辑半导体芯片的装置
Gottwald et al. P2 Pack-the paradigm shift in interconnect technology
CN105990275A (zh) 功率模块封装件及其制作方法
CN107154389B (zh) 一种高散热能力的小型贴片固态继电器及其制造方法
Longford et al. Utilising advanced packaging technologies to enable smaller, more efficient GaN power devices
CN104882440B (zh) 具有安装到载体的多个芯片的半导体器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20140924

RJ01 Rejection of invention patent application after publication