CN111106077A - 集成电路（ic）芯片装置 - Google Patents

集成电路（ic）芯片装置 Download PDF

Info

Publication number
CN111106077A
CN111106077A CN201911016899.5A CN201911016899A CN111106077A CN 111106077 A CN111106077 A CN 111106077A CN 201911016899 A CN201911016899 A CN 201911016899A CN 111106077 A CN111106077 A CN 111106077A
Authority
CN
China
Prior art keywords
mosfet
semiconductor chip
package
conductive layer
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911016899.5A
Other languages
English (en)
Inventor
C·德耶拉希-切克
B·奥尔
M·拉杜纳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN111106077A publication Critical patent/CN111106077A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/40175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本文公开的示例涉及集成电路(IC)芯片装置。示例集成电路(IC)封装可以包括第一半导体芯片和第二半导体芯片，第一半导体芯片包括第一金属氧化物半导体场效应晶体管(MOSFET)，第二半导体芯片被安装在该IC封装的壳体内。第二半导体芯片可以包括第二MOSFET和配置有用于第一MOSFET的第一驱动器和用于第二MOSFET的第二驱动器的控制电路。第一半导体芯片可以与IC封装的基部相对地安装到第二半导体芯片。

Description

集成电路(IC)芯片装置
背景技术
集成电路(IC)可以包括电子电路的一个或多个部件。一个或多个部件可以被包括在半导体芯片(例如，硅芯片)内。在一些情况下，可以将多个半导体芯片组合以在单个封装壳体内形成电子电路。
发明内容
根据一些实施方式，一种集成电路(IC)封装可以包括第一半导体芯片和第二半导体芯片，第一半导体芯片包括第一金属氧化物半导体场效应晶体管(MOSFET)，第二半导体芯片被安装在该IC封装的壳体内。第二半导体芯片可以包括第二MOSFET和控制电路，控制电路配置有用于第一MOSFET的第一驱动器和用于第二MOSFET的第二驱动器。第一半导体芯片可以与IC封装的基部相对地被安装到第二半导体芯片。
根据一些实施方式，一种系统可以包括第一金属氧化物半导体场效应晶体管(MOSFET)；第二MOSFET，其中第一MOSFET的源极连接到第二MOSFET的漏极；以及控制电路，其用以控制到第一MOSFET或第二MOSFET的信号。第一MOSFET可以在第一半导体芯片上，并且第二MOSFET和控制电路可以在与第一半导体芯片分离的第二半导体芯片上。第一半导体芯片可以在IC封装的壳体内被安装到第二半导体芯片上。
根据一些实施方式，一种方法可以包括将第一半导体芯片安装到第二半导体芯片的导电层，使得第一半导体芯片和第二半导体芯片被配置成装配在集成电路(IC)封装的壳体内，其中第一半导体芯片包括第一金属氧化物半导体场效应晶体管(MOSFET)；以及将第二半导体芯片固定在IC封装的基部上，其中IC封装的基部对应于IC封装的引线框侧，其中导电层与IC封装的基部相对；并且其中第二半导体芯片包括：第二MOSFET和控制电路，控制电路包括用于第一MOSFET的第一驱动器和用于第二MOSFET的第二驱动器。
附图说明
图1A和图1B是与本文描述的示例集成电路封装相关联的图。
图2和图3是图1A的集成电路封装的示例实施方式的框图。
图4A-图4C是如本文所述的示例实施方式的图。
图5是与提供如本文所述的集成电路芯片装置相关联的示例方法的流程图。
具体实施方式
示例实施方式的以下详细描述参考附图。不同附图中的相同附图标记可以标识相同或相似的元件。
在一些情况下，多个半导体芯片要被包括在同一个集成电路(IC)封装内。例如，具有半桥(其包括一对金属氧化物半导体场效应晶体管(MOSFET))的IC封装可能要求在IC封装中包括多个半导体芯片(例如，这些MOSFET中的每个MOSFET在单独的半导体芯片上和/或半桥的控制电路在单独芯片上)。半桥可以用于打开电机驱动器。在一些实施方式中，在反向块应用中，用于MOSFET的驱动器(例如，栅极驱动器)可以被包括在与IC封装内的MOSFET分离的单独的半导体芯片上。
另外，为了将多个半导体芯片装配在单个封装内(并限制IC封装的面积的大小)，可以在IC封装内堆叠一个或多个半导体芯片。例如，各自包括半桥的一个MOSFET的半导体芯片可以固定到IC封装的引线框侧(例如，基部或端子侧)，并且通过芯片封装经由芯片彼此连接。在这种情况下，可以将包括控制电路的另一个半导体芯片胶合在包括MOSFET的半导体芯片中的一个之上(例如，与半导体芯片的引线框侧相对)。在一些情况下，两个MOSFET可以被制造在相同的半导体芯片上，而控制电路半导体芯片被胶合该半导体芯片之上。尽管这种半导体芯片可以使得多个半导体芯片能够装配在单个IC封装内，但是这种封装的生产可能是昂贵的并且需要相对大的封装尺寸。
在一些情况下，具有源极向下的半桥的第一MOSFET的芯片层叠实施方式在第一半导体芯片上，该第一半导体芯片胶合到具有漏极向下的半桥的第二MOSFET的第二半导体芯片。在这种情况下，如果IC封装的器件关断，则可能会阻挡流经半桥的电流。然而，制造具有源极向下的MOSFET的半导体芯片的这种技术可能相对昂贵。
根据本文描述的一些实施方式，使用芯片层叠技术来提供和/或构建具有半桥的IC封装。半导体芯片的示例导电层可以被配置或形成为半导体芯片的一部分，并且用作半桥电路的输出。另外，可以将用于构建半桥的半导体芯片安装到导电层，以使得能够简单地制造和/或组装IC封装。因此，可以不需要附加的导体材料来使用导电层将一个半导体芯片安装到另一个半导体芯片。另外，这种配置可以节省IC封装空间和/或IC封装尺寸，使得能够易于组装并降低成本(例如，与制造IC封装相关联的材料成本、硬件成本和/或组装成本)。因此，本文描述的一些实施方式可以通过使更多的IC封装和/或更多的用于IC封装的壳体能够由与之前的技术相同的材料量来制造，从而节省材料和/或制造资源。
图1A和图1B是与本文描述的示例实施方式相关联的图。在示例实施方式100中，IC封装110包括第一半导体芯片120和第二半导体芯片130。第一半导体芯片120和/或第二半导体芯片130可以由硅或任何其他类型的半导体形成和/或包括硅或任何其他类型的半导体。如图1A中所示，第一半导体芯片120被安装到第二半导体芯片的导电层140。导电层140可以是铜或任何其他类型的导体的层。
根据一些实施方式，可以使得用裸片附接(DA)材料和/或DA工艺将第一半导体芯片120安装到第二半导体芯片130。例如，可以使用焊接、烧结、粘结(例如，使用导电胶)等中的一种或多种将第一半导体芯片120附接到或安装到第二半导体芯片130(例如，到第二半导体芯片130的导电层)。根据一些实施方式，第一半导体芯片120可以在第一半导体芯片120的基部上(例如，对应于n型MOSFET(NMOS)的背面)包括一个或多个部件和/或部件的一个或多个端子，第一半导体芯片120的基部被安装到导电层140。第一半导体芯片120和第二半导体芯片130可以被安装在IC封装110的壳体(例如，非导电壳体)内。另外，当从上方(或下方)观察时，第一半导体芯片120的周界可以在第二半导体芯片130的周界内，使得第一半导体芯片120不延伸超过第二半导体芯片130的边缘。
如图1A中进一步所示，导电层140与第二半导体芯片130的基部相对。第二半导体芯片130的基部可以被安装到IC封装110的引线框150。因此，第二半导体芯片的导电层140可以被配置成与IC封装110的引线框侧相对。引线框150可以为IC封装110提供导电性和/或冷却。如图1A中所示，IC封装110的引线框150可以向IC封装110提供电源电压(Vs)。该电源电压可以向由IC封装110的第一半导体芯片120和第二半导体芯片130形成的电路提供电力。
另外，如图1A中所示，IC封装110可以包括接地端子160(GND)和IC输出端子170。接地端子160可以与电路(例如，印刷电路板(PCB)的电路)的接地通信耦合和/或接触。IC输出端子170可以是IC封装110的IC(例如，由第一半导体芯片120和第二半导体芯片130的部件形成)的输出，其可以与电路的一个或多个其他部件通信耦合(例如，经由PCB)。如图1A中所示，第二半导体芯片130的导电层140连接到IC输出端子170(例如，经由一个或多个键合线、一个或多个铜夹等)，并且第一半导体芯片120连接到接地端子160(例如，经由一个或多个键合线、一个或多个铜夹等)。
如图1B中所示，示例实施方式100的IC封装110可以包括半桥180。半桥包括低侧MOSFET 182和高侧MOSFET 184。在示例实施方式100中，低侧MOSFET 182在第一半导体芯片120上，并且高侧MOSFET 184在第二半导体芯片130上。在一些实施方式中，低侧MOSFET和高侧MOSFET是n型MOSFET(NMOS)。在一些实施方式中，低侧MOSFET 182是NMOS，而高侧MOSFET184是p型的(PMOS)。
如图1B中的半桥180的电路所示，低侧MOSFET 182的漏极与高侧MOSFET 184的源极通信耦合。另外，可以从通信耦合的低侧MOSFET 182的漏极和高侧MOSFET 184的源极提供来自半桥180的半桥输出186。如图1B中所示，半桥180的半桥输出186可以与第二半导体芯片130的导电层140通信耦合和/或对应。因此，因为导电层140与IC输出端子170通信耦合，所以半桥输出186可以对应于经由IC输出端子170的来自IC封装110的输出。如此，来自IC封装110的输出可以是半桥输出186。另外，高侧MOSFET 184的漏极可以与引线框150通信耦合，并且因此与IC封装110的电源电压(Vs)通信耦合。附加地或备选地，低侧MOSFET 182的源极可以与接地端子160通信耦合，并且因此与IC封装110的接地通信耦合。因此，半桥180可以通过IC封装110的端子(例如，经由PCB)形成和/或与电路的其他部件通信耦合。
在一些实施方式中，如本文中进一步所描述的，低侧MOSFET 182的栅极和/或高侧MOSFET 184的栅极可以由IC封装110的控制电路的一个或多个驱动器(例如，栅极驱动器)控制。
如上面所指示的，仅作为示例提供图1A和图1B。其他示例是可能的，并且可能与关于图1A和图1B描述的示例不同。
图2是图1A的集成电路封装110的示例实施方式200的框图。如图2中所示，IC封装110包括第一半导体芯片120和第二半导体芯片130。第一半导体芯片120和第二半导体芯片可以被包围在图2的IC封装110的壳体内。如本文所述，第一半导体芯片120可以被安装到第二半导体芯片130。
如图2中进一步所示，第一半导体芯片120包括低侧MOSFET 182。第二半导体芯片130包括高侧MOSFET 184和控制电路，控制电路包括驱动器控制器210、低侧驱动器220和高侧驱动器230。在示例实施方式200中，驱动器控制器210可以控制低侧驱动器220和高侧驱动器230，低侧驱动器220驱动低侧MOSFET 182(例如，经由低侧MOSFET 182的栅极)，并且高侧驱动器230驱动高侧MOSFET 184(例如，经由高侧MOSFET 184的栅极)。
示例驱动器控制器210可以包括一个或多个部件和/或模块，以控制低侧驱动器220和/或高侧驱动器230。例如，驱动器控制器210可以包括电源电压监控模块、过压保护模块、电压传感器、内部电源、智能锁存器、一个或多个输出、一个或多个输入以及驱动器逻辑(例如，利用快速脉冲宽度调制(PWM))、负载电流传感器、输出电压限制器等。低侧驱动器220可以经由功率放大器来实施和/或可以包括低侧栅极控制(例如，利用快速PWM)、低侧过电流保护模块、过电压钳位模块、低侧温度监控器等。附加地或备选地，高侧驱动器230可以经由类似的功率放大器来实施和/或类似地可以包括高侧栅极控制(例如，利用电荷泵)、高侧过电流保护模块、过压钳位模块、高侧温度监控器等。
相应地，如图2的示例实施方式200所示，第一半导体芯片120可以包括低侧MOSFET182，并且第二半导体芯片130可以包括高侧MOSFET 184和用于低侧MOSFET 182和高侧MOSFET 184(它们形成由控制电路控制的半桥)的控制电路。第二半导体芯片130上的控制电路可以包括用于低侧MOSFET 182和高侧MOSFET 184的两个驱动器(低侧驱动器220和高侧驱动器230)。
作为示例提供图2中所示的元件和/或部件的数量和布置。实际上，与图2所示的元件和/或部件相比，可以存在附加的元件和/或部件、更少的元件和/或部件、不同的元件和/或部件或不同地布置的元件和/或部件。另外，图2中所示的两个或多个元件和/或部件可以在一个电路内实施，或者图2中所示的单个元件或部件可以被实施成多个分布式元件或部件。附加地或备选地，IC封装110的一组电路(例如，一个或多个电路)可以执行被描述为由IC封装110的另一组电路执行的一个或多个功能。
图3是图1A的集成电路封装110的示例实施方式300的框图。与示例实施方式200类似，在示例实施方式300中，IC封装110包括第一半导体芯片120和第二半导体芯片130(例如，被包围在图3的IC封装110的壳体内)。如本文所述，第一半导体芯片120可以被安装到第二半导体芯片130。
在示例实施方式300中，IC封装110可以包括半桥(或降压转换器)，该半桥包括反向块，如由附图标记302所示。因此，可以有一个低侧MOSFET 182和两个高侧MOSFET(示为高侧MOSFET 184和高侧MOSFET 384)。因此，第二半导体芯片130可以包括驱动器控制器310，其被配置成控制低侧驱动器320和两个高侧驱动器330、340，两个高侧驱动器330、340分别驱动高侧MOSFET 184、384。驱动器控制器310，低侧驱动器320和高侧驱动器330、340可以以分别与示例实施方式200的驱动器控制器210、低侧驱动器220和高侧驱动器230类似的方式配置，和/或包括与示例实施方式200的驱动器控制器210、低侧驱动器220和高侧驱动器230类似的部件或模块。
因此，如所示的，根据本文所述的示例实施方式，可以在IC封装110内配置具有反向块的半桥(如由附图标记302所示)。
作为示例提供图3中所示的元件和/或部件的数量和布置。实际上，与图3所示的元件和/或部件相比，可以存在附加的元件和/或部件、更少的元件和/或部件、不同的元件和/或部件，或不同地布置的元件和/或部件。另外，图3中所示的两个或多个元件和/或部件可以在一个电路内实施，或者图3中所示的单个元件或部件可以被实施成多个分布式元件或部件。附加地或备选地，IC封装110的一组电路(例如，一个或多个电路)可以执行被描述为由IC封装110的另一组电路执行的一个或多个功能。
图4A-图4C是如本文所述的实施方式的图。在图4A-图4C的示例实施方式中，示出了IC封装110的俯视图。如图4A中所示，其示出了第一半导体芯片120的第一MOSFET(例如，低侧MOSFET 182)的顶部金属层410和栅极420。第一半导体芯片120被示为安装到第二半导体芯片130的导电层140(例如，顶金属层)。在一些实施方式中，第二半导体芯片130的第二MOSFET(例如，高侧MOSFET 184)基本上被导电层140覆盖(关于图4A-图4C的俯视图)。如所示的，第二半导体芯片130包括低侧驱动器220和高侧驱动器230。
如图4B中所示，IC芯片110包括引线框430(如所示的，其可以包括一个或多个端子)。第一组键合线440将低侧驱动器220(例如，低侧驱动器220的输出)连接到第一半导体芯片120的第一MOSFET的栅极420，第二组键合线450将第一半导体芯片120的第一MOSFET的源极连接到引线框430，并且第三组键合线460将导电层140连接到引线框430，以用作IC封装110的输出(即，第二半导体芯片130的源极和/或第一半导体芯片120的漏极)。
如图4C中所示，一个或多个夹可以用作图4B的一个或多个键合线的备选方案。例如，在图4C中，第一夹470可以用于将第一半导体芯片120的源极连接到引线框430，并且第二夹480可以用于将导电层140连接到引线框430。在一些实施方式中，第三夹(未示出)可以代替第一组键合线440，以用作栅极420和低侧驱动器220的输出之间的连接。
作为示例提供图4A-图4C中所示的元件和/或部件的数量和布置。实际上，与图4A-图4C所示的元件和/或部件相比，可以存在附加的元件和/或部件、更少的元件和/或部件、不同的元件和/或部件，或不同地布置的元件和/或部件。另外，图4A-图4C中所示的两个或多个元件和/或部件可以在一个电路内实施，或者图4A-图4C中所示的单个元件或部件可以被实施成多个分布式元件或部件。
图5是与提供如本文所述的集成电路芯片装置相关联的示例方法500的流程图。在一些实施方式中，图5的一个或多个方法框可以由与制造集成电路封装相关联的机器来执行，该集成电路封装包括如本文所描述的集成电路芯片装置。
如图5中进一步所示，方法500可以包括将第一半导体芯片安装到第二半导体芯片的导电层，使得第一半导体芯片和第二半导体芯片被配置成装配在IC封装的壳体内(框510)。第一半导体芯片可以包括第一MOSFET。
在一些实施方式中，在将第二半导体芯片固定到IC封装的基部之后，通过将第一半导体芯片焊接、烧结或粘附到导电层中的至少一项，将第一半导体芯片安装到导电层。在一些实施方式中，第二半导体芯片的周界在第一半导体芯片的周界内。
如图5中所示，方法500可以包括将第二半导体芯片固定在IC封装的基部上(框520)。IC封装的基部可以对应于IC封装的引线框侧。导电层可以与IC封装的引线框侧相对，并且第二半导体芯片可以进一步包括第二MOSFET和控制电路，控制电路包括用于第一MOSFET的第一驱动器和用于第二MOSFET的第二驱动器。在一些实施方式中，第一MOSFET可以对应于半桥电路的高侧MOSFET，并且第二MOSFET可以对应于半桥电路的低侧MOSFET。
在一些实施方式中，导电层可以被配置和/或提供为由第一MOSFET和第二MOSFET形成的半桥电路的输出。在一些实施方式中，第一MOSFET可以是n型MOSFET(NMOS)，并且第二MOSFET可以是NMOS。在一些实施方式中，第一MOSFET是n型MOSFET(NMOS)，并且第二MOSFET是p型MOSFET(PMOS)。在一些实施方式中，第一半导体芯片仅包括第一MOSFET和到第一MOSFET的连接。在一些实施方式中，IC封装的引线框(对应于引线框侧)可以连接到IC封装的一个或多个端子。在一些实施方式中，第二半导体芯片可以包括第三MOSFET，并且控制电路可以包括用于第三MOSFET的第三驱动器。
尽管图5示出了方法500的示例框，但是在一些实施方式中，与图5中所示的那些框相比，方法500可以包括附加的框、更少的框，不同的框或不同地布置的框。例如，在一些实施方式中，可以在框510的过程之前执行框520的过程。附加地或备选地，可以并行地执行方法500的两个或多个框。
前述公开内容提供了说明和描述，但并不旨在穷举或将实施方式限制为所公开的精确形式。鉴于以上公开，修改和变化是可能的，或者可以从对实施方式的实践中获得修改和变化。
如本文所使用的，术语“部件”旨在被广义地解释为硬件、固件，或硬件和软件的组合。
尽管在权利要求中陈述和/或在说明书中公开了特征的特定组合，但这些组合不旨在限制可能的实施方式的公开。实际上，许多这些特征可以以权利要求书中未具体叙述和/或说明书中未公开的方式组合。尽管下面列出的每个从属权利要求可能仅直接从属于一个权利要求，但可能的实施方式的公开内容包括每个从属权利要求与权利要求集中的每个其他权利要求的组合。
除非明确地如此描述，否则本文中使用的元件、动作或指令均不应当被解释为关键或必要的。另外，如本文所使用，冠词“一”和“一个”旨在包括一个或多个项目，并且可以与“一个或多个”互换使用。另外，如本文所使用的，术语“组”旨在包括一个或多个项目(例如，相关项目、不相关项目、相关和不相关项目的组合等)，并且可以与“一个或多个”互换使用。在旨在使用仅一个项目的情况下，使用术语“一个”或类似的语言。而且，如本文所使用的，术语“具有”、“包括”、“包含”等旨在是开放式术语。另外，短语“基于”旨在意指“至少部分地基于”，除非另有明确说明。
示例
1.一种集成电路(IC)封装，包括：
第一半导体芯片，包括第一金属氧化物半导体场效应晶体管(MOSFET)；以及
第二半导体芯片，安装在所述IC封装的壳体内，
其中所述第二半导体芯片包括：
第二MOSFET；以及
控制电路，配置有用于所述第一MOSFET的第一驱动器和用于所述第二MOSFET的第二驱动器，
其中所述第一半导体芯片与所述IC封装的基部相对地被安装到所述第二半导体芯片。
2.根据示例1所述的IC封装，其中所述第二半导体芯片包括导电层，并且所述第一半导体芯片被安装到所述导电层。
3.根据示例2所述的IC封装，其中所述导电层对应于由所述第一MOSFET和所述第二MOSFET形成的半桥电路的输出。
4.根据示例2-3中任一项所述的IC封装，其中通过将所述第一半导体芯片焊接、烧结或胶合到所述导电层中的至少一项，将所述第一半导体芯片安装到所述导电层。
5.根据示例2-4中任一项所述的IC封装，其中所述第一MOSFET对应于半桥电路的低侧MOSFET，并且所述第二MOSFET对应于所述半桥电路的高侧MOSFET。
6.根据示例2-5中任一项所述的IC封装，其中所述第一MOSFET是n型MOSFET(NMOS)，并且所述第二MOSFET是NMOS。
7.根据示例2-6中任一项所述的IC封装，其中所述第一MOSFET是n型MOSFET(NMOS)，并且所述第二MOSFET是p型MOSFET(PMOS)。
8.根据示例2-7中任一项所述的IC封装，其中所述第一半导体芯片仅包括所述第一MOSFET以及到所述第一MOSFET的连接。
9.根据示例2-8中任一项所述的IC封装，其中所述第二半导体芯片包括第三MOSFET，并且所述控制电路包括用于所述第三MOSFET的第三驱动器。
10.根据示例2-9中任一项所述的IC封装，其中所述IC封装的所述基部对应于所述IC封装的引线框侧，
其中所述IC封装的引线框连接到所述IC封装的一个或多个端子。
11.一种系统，包括：
第一金属氧化物半导体场效应晶体管(MOSFET)；
第二MOSFET，
其中所述第一MOSFET的源极连接到所述第二MOSFET的漏极；以及
控制电路，用于控制到所述第一MOSFET或所述第二MOSFET的信号，
其中所述第一MOSFET在第一半导体芯片上，并且所述第二MOSFET和所述控制电路在与所述第一半导体芯片分离的第二半导体芯片上，
其中所述第一半导体芯片在IC封装的壳体内被安装在所述第二半导体芯片上。
12.根据示例11所述的系统，其中所述第一半导体芯片包括导电层，并且所述第二半导体芯片被安装到所述导电层。
13.根据示例11至12中任一项所述的系统，其中所述第一MOSFET的所述漏极和所述第二MOSFET的所述源极连接到所述导电层。
14.根据示例11-13中任一项所述的系统，其中所述导电层对应于由所述第一MOSFET和所述第二MOSFET形成的半桥电路的输出。
15.根据示例11至14中任一项所述的系统，其中经由将所述第一半导体芯片焊接、烧结或胶合到所述导电层中的至少一种，而将所述第一半导体芯片安装到所述导电层。
16.根据示例11-15中任一项所述的系统，所述控制电路包括：
用于驱动所述第一MOSFET的第一驱动器；以及
用于驱动所述第二MOSFET的第二驱动器。
17.根据示例11-16中任一项所述的系统，还包括：
第三MOSFET，
其中所述第三MOSFET的源极连接到所述第二MOSFET的漏极，所述第三MOSFET在所述第二半导体芯片上，并且所述控制电路被配置成控制到所述第三MOSFET的信号。
18.一种方法，包括：
将第一半导体芯片安装到第二半导体芯片的导电层上，使得所述第一半导体芯片和所述第二半导体芯片被配置成装配在集成电路(IC)封装的壳体内，
其中所述第一半导体芯片包括第一金属氧化物半导体场效应晶体管(MOSFET)；以及
将所述第二半导体芯片固定在所述IC封装的基部上，
其中所述IC封装的所述基部对应于所述IC封装的引线框侧，
其中所述导电层与所述IC封装的所述基部相对，并且
其中所述第二半导体芯片包括：
第二MOSFET，以及
控制电路，包括用于所述第一MOSFET的第一驱动器和用于所述第二MOSFET的第二驱动器。
19.根据示例18所述的方法，其中在将所述第二半导体芯片固定到所述IC封装的所述基部之后，通过将所述第一半导体芯片焊接、烧结或粘附到所述导电层中的至少一项，将所述第一半导体芯片安装到所述导电层,
其中所述第一半导体芯片的周界在所述第二半导体芯片的周界内。
20.根据示例18-19中的任一项所述的方法，其中所述第二MOSFET对应于半桥电路的高侧MOSFET，并且所述第一MOSFET对应于所述半桥电路的低侧MOSFET。
21.一种方法，包括：
将第一半导体芯片固定在集成电路(IC)封装的基部上，
其中所述IC封装的所述基部对应于所述IC封装的引线框侧，并且
其中所述第一半导体芯片包括：
与所述第一半导体芯片的所述基极相对的导电层，
第一金属氧化物半导体场效应晶体管，以及
包括用于所述第一MOSFET的第一驱动器的控制电路系统；
将第二半导体芯片安装到所述第一半导体芯片的所述导电层，使得所述第一半导体芯片和所述第二半导体芯片被配置成装配在所述IC封装的壳体内，
其中所述第二半导体芯片包括第二MOSFET，并且所述第一半导体芯片还包括用于所述第二MOSFET的第二驱动器。
22.根据示例21所述的方法，其中通过将所述第二半导体芯片焊接、烧结或粘附到所述导电层中的至少一项，将所述第二半导体芯片安装到所述导电层，
其中所述第二半导体芯片的周界在所述第一半导体芯片的周界内。
23.根据示例21至22中任一项所述的方法，其中所述第一MOSFET对应于半桥电路的高侧MOSFET，并且所述第二MOSFET对应于所述半桥电路的低侧MOSFET。

Claims (20)

1.一种集成电路(IC)封装，包括：
第一半导体芯片，包括第一金属氧化物半导体场效应晶体管(MOSFET)；以及
第二半导体芯片，安装在所述IC封装的壳体内，
其中所述第二半导体芯片包括：
第二MOSFET；以及
控制电路，配置有用于所述第一MOSFET的第一驱动器和用于所述第二MOSFET的第二驱动器，
其中所述第一半导体芯片与所述IC封装的基部相对地安装到所述第二半导体芯片。
2.根据权利要求1所述的IC封装，其中所述第二半导体芯片包括导电层，并且所述第一半导体芯片被安装到所述导电层。
3.根据权利要求2所述的IC封装，其中所述导电层对应于由所述第一MOSFET和所述第二MOSFET形成的半桥电路的输出。
4.根据权利要求2所述的IC封装，其中通过将所述第一半导体芯片焊接、烧结或胶合到所述导电层中的至少一项，将所述第一半导体芯片安装到所述导电层。
5.根据权利要求1所述的IC封装，其中所述第一MOSFET对应于半桥电路的低侧MOSFET，并且所述第二MOSFET对应于所述半桥电路的高侧MOSFET。
6.根据权利要求1所述的IC封装，其中所述第一MOSFET是n型MOSFET(NMOS)，并且所述第二MOSFET是NMOS。
7.根据权利要求1所述的IC封装，其中所述第一MOSFET是n型MOSFET(NMOS)，并且所述第二MOSFET是p型MOSFET(PMOS)。
8.根据权利要求1所述的IC封装，其中所述第一半导体芯片仅包括所述第一MOSFET以及到所述第一MOSFET的连接。
9.根据权利要求1所述的IC封装，其中所述第二半导体芯片包括第三MOSFET，并且所述控制电路包括用于所述第三MOSFET的第三驱动器。
10.根据权利要求1所述的IC封装，其中所述IC封装的所述基部对应于所述IC封装的引线框侧，
其中所述IC封装的引线框连接到所述IC封装的一个或多个端子。
11.一种系统，包括：
第一金属氧化物半导体场效应晶体管(MOSFET)；
第二MOSFET，
其中所述第一MOSFET的源极连接到所述第二MOSFET的漏极；以及
控制电路，用以控制到所述第一MOSFET或所述第二MOSFET的信号，
其中所述第一MOSFET在第一半导体芯片上，并且所述第二MOSFET和所述控制电路在与所述第一半导体芯片分离的第二半导体芯片上，
其中所述第一半导体芯片在IC封装的壳体内被安装在所述第二半导体芯片上。
12.根据权利要求11所述的系统，其中所述第一半导体芯片包括导电层，并且所述第二半导体芯片被安装到所述导电层。
13.根据权利要求12所述的系统，其中所述第一MOSFET的所述漏极和所述第二MOSFET的所述源极连接到所述导电层。
14.根据权利要求12所述的系统，其中所述导电层对应于由所述第一MOSFET和所述第二MOSFET形成的半桥电路的输出。
15.根据权利要求12所述的系统，其中通过将所述第一半导体芯片焊接、烧结或胶合到所述导电层中的至少一项，将所述第一半导体芯片安装到所述导电层。
16.根据权利要求11所述的系统，所述控制电路包括：
用于驱动所述第一MOSFET的第一驱动器；以及
用于驱动所述第二MOSFET的第二驱动器。
17.根据权利要求11所述的系统，还包括：
第三MOSFET，
其中所述第三MOSFET的源极连接到所述第二MOSFET的漏极，所述第三MOSFET在所述第二半导体芯片上，并且所述控制电路被配置成控制到所述第三MOSFET的信号。
18.一种方法，包括：
将第一半导体芯片安装到第二半导体芯片的导电层，使得所述第一半导体芯片和所述第二半导体芯片被配置成装配在集成电路(IC)封装的壳体内，
其中所述第一半导体芯片包括第一金属氧化物半导体场效应晶体管(MOSFET)；以及
将所述第二半导体芯片固定在所述IC封装的基部上，
其中所述IC封装的所述基部对应于所述IC封装的引线框侧，
其中所述导电层与所述IC封装的所述基部相对，并且
其中所述第二半导体芯片包括：
第二MOSFET，以及
控制电路，包括用于所述第一MOSFET的第一驱动器和用于所述第二MOSFET的第二驱动器。
19.根据权利要求18所述的方法，其中在将所述第二半导体芯片固定到所述IC封装的所述基部之后，通过将所述第一半导体芯片焊接、烧结或粘附到所述导电层中的至少一项，将所述第一半导体芯片安装到所述导电层,
其中所述第一半导体芯片的周界在所述第二半导体芯片的周界内。
20.根据权利要求18所述的方法，其中所述第二MOSFET对应于半桥电路的高侧MOSFET，并且所述第一MOSFET对应于所述半桥电路的低侧MOSFET。
CN201911016899.5A 2018-10-25 2019-10-24 集成电路（ic）芯片装置 Pending CN111106077A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/170,761 US10580762B1 (en) 2018-10-25 2018-10-25 Integrated circuit (IC) chip arrangement
US16/170,761 2018-10-25

Publications (1)

Publication Number Publication Date
CN111106077A true CN111106077A (zh) 2020-05-05

Family

ID=69645507

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911016899.5A Pending CN111106077A (zh) 2018-10-25 2019-10-24 集成电路（ic）芯片装置

Country Status (3)

Country Link
US (1) US10580762B1 (zh)
CN (1) CN111106077A (zh)
DE (1) DE102019128736A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641887A (zh) * 2004-01-16 2005-07-20 株式会社瑞萨科技 半导体器件
CN1835232A (zh) * 2005-03-18 2006-09-20 株式会社理光 多芯片型半导体装置及其制造方法
CN101419964A (zh) * 2007-10-26 2009-04-29 英飞凌科技股份公司 具有多个半导体芯片的装置
US20110024884A1 (en) * 2009-07-31 2011-02-03 Yan Xun Xue Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors
US20150303128A1 (en) * 2014-04-16 2015-10-22 Infineon Technologies Ag Device Including Multiple Semiconductor Chips and Multiple Carriers
CN105283956A (zh) * 2013-04-11 2016-01-27 德克萨斯仪器股份有限公司 具有竖直堆叠的半导体芯片的集成化多路输出电源转换器
CN105702665A (zh) * 2014-12-11 2016-06-22 株式会社东芝 半导体装置
US20170207195A1 (en) * 2016-01-14 2017-07-20 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048338B2 (en) * 2011-11-04 2015-06-02 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
US9385070B2 (en) * 2013-06-28 2016-07-05 Delta Electronics, Inc. Semiconductor component having a lateral semiconductor device and a vertical semiconductor device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641887A (zh) * 2004-01-16 2005-07-20 株式会社瑞萨科技 半导体器件
CN1835232A (zh) * 2005-03-18 2006-09-20 株式会社理光 多芯片型半导体装置及其制造方法
US20080246534A1 (en) * 2005-03-18 2008-10-09 Ricoh Company, Ltd. Multi-chip semiconductor device with high withstand voltage, and a fabrication method of the same
CN101419964A (zh) * 2007-10-26 2009-04-29 英飞凌科技股份公司 具有多个半导体芯片的装置
US20110024884A1 (en) * 2009-07-31 2011-02-03 Yan Xun Xue Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors
CN105283956A (zh) * 2013-04-11 2016-01-27 德克萨斯仪器股份有限公司 具有竖直堆叠的半导体芯片的集成化多路输出电源转换器
US20150303128A1 (en) * 2014-04-16 2015-10-22 Infineon Technologies Ag Device Including Multiple Semiconductor Chips and Multiple Carriers
CN105023920A (zh) * 2014-04-16 2015-11-04 英飞凌科技股份有限公司 包括多个半导体芯片和多个载体的器件
CN105702665A (zh) * 2014-12-11 2016-06-22 株式会社东芝 半导体装置
US20170207195A1 (en) * 2016-01-14 2017-07-20 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Also Published As

Publication number Publication date
US10580762B1 (en) 2020-03-03
DE102019128736A1 (de) 2020-04-30

Similar Documents

Publication Publication Date Title
US7777315B2 (en) Dual side cooling integrated power device module and methods of manufacture
US9906165B2 (en) Semiconductor module
US8067979B2 (en) Semiconductor device and power supply device using the same
US8946880B2 (en) Packaged semiconductor device having multilevel leadframes configured as modules
US7149088B2 (en) Half-bridge power module with insert molded heatsinks
CN105981170B (zh) 具有半导体芯片端子的dc-dc转换器
EP1881530A1 (en) Power semiconductor apparatus
CN108511396B (zh) 电子装置
CN107742620B (zh) 用于电机驱动的集成功率模块和智能功率模块
KR20120123254A (ko) 전력 공급 모듈 및 이의 패키징 및 집적 방법
US9196561B2 (en) Semiconductor device to be attached to heat radiation member
US20140210061A1 (en) Chip arrangement and chip package
TWI452662B (zh) 雙邊冷卻整合電源裝置封裝與模組及製造方法
CN111816572A (zh) 芯片封装及其形成方法、半导体器件及其形成方法、半导体装置及其形成方法、三相系统
JP2002083927A (ja) 半導体装置
US8987880B2 (en) Chip module and a method for manufacturing a chip module
JP2006216989A (ja) 半導体装置およびそれを用いたインバータ回路
JP2002057282A (ja) 半導体装置およびそれを用いたインバータ回路
CN109841598B (zh) 多相半桥驱动器封装以及制造方法
CN111106077A (zh) 集成电路（ic）芯片装置
US8198134B2 (en) Dual side cooling integrated power device module and methods of manufacture
EP3370332B1 (en) Stray inductance reduction in packaged semiconductor devices and modules
JP5407244B2 (ja) モータ駆動装置
CN107658283B (zh) 用于电机驱动的集成功率模块和智能功率模块
JP2005051109A (ja) パワー半導体モジュール

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination