CN1344014A - 半导体器件和半导体组件 - Google Patents

半导体器件和半导体组件 Download PDF

Info

Publication number
CN1344014A
CN1344014A CN01112389A CN01112389A CN1344014A CN 1344014 A CN1344014 A CN 1344014A CN 01112389 A CN01112389 A CN 01112389A CN 01112389 A CN01112389 A CN 01112389A CN 1344014 A CN1344014 A CN 1344014A
Authority
CN
China
Prior art keywords
conductive path
semiconductor device
insulating resin
described conductive
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01112389A
Other languages
English (en)
Other versions
CN1244139C (zh
Inventor
坂本则明
小林义幸
阪本纯次
真下茂明
大川克实
前原荣寿
高桥幸嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1344014A publication Critical patent/CN1344014A/zh
Application granted granted Critical
Publication of CN1244139C publication Critical patent/CN1244139C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905Shape
    • H01L2224/49051Connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01021Scandium [Sc]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01059Praseodymium [Pr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

采用薄型、轻量的封装。但是,因薄型而产生封装弯曲,因与安装基片的热膨胀系数不同而引起问题,例如发生半导体器件中设置的导电通路的断线,与金属细线的连接不良,半导体器件的可靠性存在问题。提供在绝缘树脂44中埋置比Z轴方向大的X轴-Y轴方向结晶所构成的导电通路40,导电通路40的里面从绝缘树脂44露出地封装的半导体器件。由此,可以抑制绝缘树脂44中埋置的导电通路40的断线。

Description

半导体器件和半导体组件
本发明涉及半导体器件和半导体组件,具体地涉及防止在安装基片上安装半导体器件时因热膨胀系数失配而产生不配合的技术。
以往,电子设备中装备的混合集成电路装置,例如在印刷基片、陶瓷基片或者金属基片上形成导电图形,在其上安装LSI或者分离TR等有源元件、片状电容器、片状电阻或者线圈等无源元件。这样,电连接所述导电图形和所述元件来实现预定功能的电路。
作为该电路的一个例子,如图24所示,该电路是音频电路,其中所示的元件按图25的形式安装。
图25中,最外侧的矩形线是至少表面进行绝缘处理的安装基片1。在其上,贴装Cu制成的导电图形2。该导电图形2由向外引出用电极2A、布线2B、管芯焊盘2C、键合焊盘2D、固定无源元件3的电极4等构成。
TR、二极管、复合元件或者LSI等按裸芯片状通过焊锡固定在管芯焊盘2C上。将如此固定的芯片上的电极通过金属细线5A、5B、5C与所述键合焊盘2D电连接。这些金属细线一般分为小信号和大信号用的,小信号类的采用约40μmφ的Au线或Al线5A,大信号类采用约100~300μmφ的Au线或Al线。特别是大信号线由于线径大,考虑到成本,选择150μmφ的Al线5B、300μmφ的Al线5C。
而且,为了防止芯片温度上升,将流过大电流的功率TR6固定在管芯焊盘2C上的热沉7上。
为了使所述向外引出用电极2A、管芯焊盘2C、键合焊盘2D、电极4形成电路,布线2B向各处延伸。而且,在为使芯片位置、布线延伸方式配合,对布线彼此交叉的情况,采用跳线8A、8B。
另一方面,作为在此基片1上安装的半导体器件,是用绝缘树脂封装的半导体器件。例如有,将半导体芯片安装在引线框架上,用绝缘树脂封装的引线框架型半导体器件;采用陶瓷基片、印刷基片或柔性片作为支撑基片,在其上安装半导体器件,用绝缘树脂封装的支撑基片型半导体器件;或者将半导体芯片安装在电镀电极上,含有电镀电极的封装的电镀型半导体器件。电镀型半导体器件详细公开在例如特开平3-94431号公报上。
其概略图如图26A所示。标号10A-10D是由镀膜形成的导电通路,在管芯焊盘10A上固定半导体芯片11,半导体芯片11的键合焊盘和电镀构成的键合焊盘10B通过金属细线12电连接。电极10C和电极10D之间通过焊料固定无源元件13。这种半导体器件由于不使用支撑基片,把镀膜埋置在绝缘树脂中,所以可制成薄型半导体器件。
在所述安装基片1上采用各种方法安装封装半导体器件。但是引线框架型半导体器件,由于引线突出封装,所以存在安装基片的专用面积大而导致安装基片大型化的问题。并且,存在切割引线框架,使得引线产生毛刺的问题。支撑基片型半导体器件,由于使用支撑基片而使半导体器件加厚,由此存在重量增大的问题。电镀型半导体器件由于不使用支撑基片,引线也不跳出封装,所以可以实现薄尺寸的小型半导体器件,但存在以下问题。
图26B是对此进行说明的图示,是对图26A部分的模式放大。三角锥的集合体所示的标号10B是由电镀形成的导电通路,标号17是焊锡。标号15是安装基片,16是在安装基片15上贴装的导电图形。
此镀膜一般是电解电镀成膜的,具有前端变细的柱状结晶结构。如图中三角锥所示。由于该膜的膜厚较薄,是多晶结构,所以机械强度弱,而且存在与绝缘树脂的热膨胀系数不同而容易产生裂缝的缺点。而且,外来物质容易扩散进晶界。例如焊锡中使用的熔剂和湿气等外部气氛气体,通过晶界侵入金属细线12的连接部位,存在连接强度劣化的问题。而且由Cu电镀形成电极11B时,下层的焊锡扩散,存在镀膜本身被焊锡侵蚀,与金属细线的连接强度劣化的问题。
如果形成细长的镀膜作为布线,则由于与绝缘树脂的热膨胀系数失配而产生布线断线。同样,在这种电镀型半导体器件安装在安装基片上时,由于与安装基片的热膨胀系数失配而布线同样发生裂缝,存在断线和布线电阻增大的问题。特别是电镀电极10B形成为细长布线的情况,与长度成比例地产生应力。因此,与绝缘树脂14或安装基片15的热膨胀系数不同,镀膜的缺点更多,存在可靠性更为降低的问题。
针对上述问题,本发明的第一解决方案包括,由X、Y方向结晶生长的导电材料构成的多个导电通路;与所述导电通路电连接的半导体芯片;覆盖所述半导体芯片,并且填充所述导电通路之间分离沟,露出所述导电通路里面,一体支撑的绝缘树脂。
如图1A所示,Z轴方向生长大于X轴-Y轴方向生长的膜称为Z膜,X轴-Y轴方向生长大于Z轴方向生长的膜称为X-Y膜。例如Z膜是通过电解、无电解而生长的镀膜,X-Y膜是通过压延形成的膜,例如压延铜箔。
如图1C所示,这是X-Y膜剖面,该膜的各个结晶在X-Y轴方向扩展层叠,晶界的面积比图1A的Z膜更为受到抑制。因此,通过晶界的扩散或渗透现象大幅度被抑制。而图1B的Z膜,对应于弯曲、沿左右施加外力的应力,其结构非常之弱。但是,如图1C所示,对应于X-Y膜自身的弯曲、断裂,X-Y膜是比Z膜更强的膜。因此,可以防止因封闭导电通路的绝缘树脂的热膨胀系数的不同而产生的导电通路裂缝。而且由于结晶尺寸大,可以降低全部导电通路本身的电阻。特别是,其封装厚度在0.5mm以下,其中埋置导电通路的情况,由于平面尺寸比厚度更大,因导电通路和绝缘树脂的热膨胀系数的差异,在X-Y方向施加应力。然而,一个一个的结晶在X-Y方向较大地生长,所以构成应力强的结构。
例如,压延Cu箔制成的电极埋置在绝缘树脂中的情况,埋置电镀Cu的电极时,在与所述应力对应的强度方面,压延铜箔是良好的,在因扩散产生的接触部位的污染方面,压延铜箔也是良好的。
本发明的第二解决方案是,所述绝缘树脂的里面和所述导电通路的侧面,成为实质上同样的腐蚀面。
由后续制造方法可以明了,半腐蚀之后,为了埋置绝缘树脂,半腐蚀的弯曲结构成为绝缘树脂的形状。这样具有在产生铰钉(ハ一フェッチング)效果的同时降低里面的接触电阻的特点。因此容易进行半导体器件本身的移动、自定位。
本发明的第三解决方案是,所述导电通路的里面形成为比所述分离沟的里面更为凹进。
通过导电通路形成为凹进,可使在此导电通路形成的焊锡较厚,而且通过形成绝缘树脂的凸部,使相邻焊锡不产生接触。
本发明的第四解决方案是,在与所述绝缘树脂接触的导电通路的表面,形成所述导电材料的氧化物。
在导电通路、特别是以Cu为主材料的金属表面形成氧化铜,可以提高与绝缘树脂的粘合性。
本发明的第五解决方案是,所述绝缘树脂的厚度实质上比1mm更薄,所述导电通路的厚度是压延工序可能形成的厚度。
本发明的第六解决方案包括,比Z轴更大的X、Y方向的结晶所形成的多个导电通路;在所述导电通路上面形成的,比X轴、Y轴方向更大的主要是Z轴方向的结晶所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路里面,一体支撑的绝缘树脂。
作为原则,电极和布线形成的导电图形由X-Y膜形成,仅只必须电连接的部分生长Z膜,这样使比全部导电图形由Z膜形成更为优异的特性可以发挥出来。例如,在制成断线和接触部位污染方面表现更为优异的半导体器件。
本发明的第七解决方案包括,比Z轴更大的X、Y方向的结晶所形成的多个导电通路;在所述导电通路上面形成的,比X轴、Y轴方向更大的主要是Z轴方向的结晶所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路里面,一体支撑的绝缘树脂,
所述绝缘树脂的里面和所述导电通路的侧面,成为实质上同样的腐蚀面。
本发明的第八解决方案包括,比Z轴更大的X、Y方向的结晶所形成的多个导电通路;在所述导电通路上面形成的,通过电镀主要是Z轴方向的结晶生长的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路里面,一体支撑的绝缘树脂,
所述导电通路的侧面被腐蚀成弯曲,所述绝缘树脂里面的至少一部分是与腐蚀面连续的曲面。
本发明的第九解决方案是,所述腐蚀面是与通过非各向异性腐蚀形成的面连续的曲面。
本发明的第十解决方案是,所述导电通路的里面形成为比所述绝缘树脂里面更为凹进。
本发明的第十一解决方案是,与所述绝缘树脂接触的所述导电通路,在表面形成氧化物。
本发明的第十二解决方案是,在所述导电通路的里面形成导电被膜。
在导电通路的里面被覆的例如金属膜、焊锡等,可以防止导电通路的氧化。因此,即使用焊料连接安装基片上的电路图形和所述导电通路,由于导电通路没有氧化物,所以能大幅度抑制不合格产品。
本发明的第十三解决方案是,所述导电被膜在所述导电通路的表面构成房檐。
由于能在导电通路和导电被膜或者导电通路本身实现房檐形状,所以表现出铰钉效果、可抑制导电通路的剥离。
本发明的第十四解决方案是,从所述绝缘树脂露出的导电通路,除了电连接部位之外,其余被绝缘树脂覆盖。
有各种形状的导电通路的情况,在全部区域浸润焊料。因此,在焊锡量不同的同时,其尺寸、表面张力、自重使得焊锡厚度不同。在露出的导电通路形成焊锡浸润不良的膜,由此控制焊锡的浸润面积,在导电通路里面形成期望厚度的焊锡。
本发明的第十五解决方案是,设置布线作为所述导电通路,从所述绝缘树脂露出的导电通路,除了电连接部位之外,其余被绝缘被膜覆盖。
本半导体器件的结构,是导电通路的里面从绝缘树脂露出的结构。为此,如图6、图7、图11所示,布线的里面也长距离露出延伸。因此,在安装基片上安装半导体器件时,安装基片的导电图形与布线短路。但是通过形成绝缘被膜即可防止短路。
本发明的第十六解决方案是,半导体器件包括,X、Y方向结晶生长的比Z轴更大的导电材料所形成的多个导电通路;在所述导电通路的上面形成的,主要是Z轴方向的结晶生长所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路的里面,一体支撑的绝缘树脂;半导体器件通过所述露出部位在安装基片上。
本发明的第十七解决方案是,半导体器件包括,X、Y方向结晶生长的比Z轴更大的导电材料所形成的多个导电通路;在所述导电通路的上面形成的,主要是Z轴方向的结晶生长所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路的里面,一体支撑的绝缘树脂,所述绝缘树脂的里面和所述导电通路的侧面是实质上连续的曲面;半导体器件通过所述露出部位在安装基片上。
本发明的第十八解决方案是,半导体器件包括,X、Y方向结晶生长的比Z轴更大的导电材料所形成的多个导电通路;在所述导电通路的上面形成的,通过电镀主要是Z轴方向的结晶生长大的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路的里面,一体支撑的绝缘树脂,所述导电通路的侧面腐蚀成为弯曲,所述绝缘树脂的里面至少一部分是与该腐蚀面实质上一致;半导体器件通过所述露出部位安装在所述安装基片上。
本发明的第十九解决方案是,所述导电通路的里面和所述安装基片通过焊料连接,在所述导电通路的里面或/和所述安装基片上的连接图形设置防止焊料流动的被膜。
在采用尺寸不同的多个导电通路的情况,焊料在导电通路的全部区域浸润扩展,在半导体器件里面形成的焊料,其厚度不同。这样,在安装基片侧的导电图形也发生同样的现象。由这种现象使得安装基片和导电通路之间的间隙狭窄。但是至少在一方形成对焊料浸润差的膜,由此可以抑制焊料的扩展,能够保持一定的间隙。
本发明的第二十解决方案是,所述腐蚀面是与非各向异性腐蚀所形成的面实质上相同的曲面。
本发明的第二十一解决方案是,所述导电通路的里面形成为比所述绝缘树脂的里面更为凹进。
本发明的第二十二解决方案是,与所述绝缘树脂接触的所述导电通路,其表面上形成氧化物。
本发明的第二十三解决方案是,在所述导电通路的里面形成导电被膜。
本发明的第二十四解决方案是,所述导电被膜在所述导电通路表面构成房檐。
图1是说明本发明的半导体器件中采用的X-Y膜的图。
图2是说明图1的X-Y膜的特性的图。
图3是说明本发明的半导体器件中采用的X-Y膜的图。
图4是说明X-Y膜表面结构的图。
图5是说明本发明的半导体器件的图。
图6是说明本发明的半导体器件的图。
图7是说明本发明的半导体器件的图。
图8是说明本发明的半导体器件的图。
图9是说明本发明的半导体器件的图。
图10是说明本发明的半导体器件的图。
图11是说明本发明的半导体器件中采用的导电图形的图。
图12是说明本发明的半导体器件的图。
图13是说明安装本发明的半导体器件的安装基片的图。
图14是说明本发明的半导体器件的制造方法的图。
图15是说明本发明的半导体器件的制造方法的图。
图16是说明本发明的半导体器件的制造方法的图。
图17是说明本发明的半导体器件的制造方法的图。
图18是说明本发明的半导体器件的制造方法的图。
图19是说明本发明的半导体器件的制造方法的图。
图20是说明本发明的半导体器件的制造方法的图。
图21是说明本发明的半导体器件的制造方法的图。
图22是说明本发明的半导体器件的尺寸的图。
图23是说明安装本发明的半导体器件的混合集成电路基片的图。
图24是说明采用本发明的半导体器件的电路例子的图。
图25是说明使用图24的电路的已有混合集成电路基片的图。
图26是说明已有半导体器件的图。
说明X-Y膜的第一实施方式
首先参照图5说明本半导体器件的尺寸。采用的半导体芯片30,由于这里使用TR芯片,所以约为0.55×0.55mm,厚0.24mm。而且半导体器件31的平面尺寸是1.6×2.3mm,厚0.5mm。半导体器件平面尺寸是芯片平面尺寸的2倍以上,封装厚度是芯片厚度两倍左右以下,特别是在倒装安装的情况,金属细线不向上延伸的状态,可以更为薄型化。也就是说薄型,通过所述的半导体器件、无源元件的组合,平面尺寸从1mm×2mm左右到远远超过该尺寸的尺寸,可以扩展到各种尺寸。
如下所述,如果一起考虑图6B、图7、图10、图11可知,本半导体器件,是从分离的封装到构成电路和系统的封装都可以是薄型的半导体器件。
本半导体器件在一个面露出导电通路32-34,绝缘树脂35从该导电通路32-34向另一面覆盖。由此,绝缘树脂35的收缩率大,具有作为整体容易弯曲的结构。因此,要求采用耐应力的导电通路32-34。特别是布线越长这种问题就越重要。
而且,同时考虑半导体器件的成本的增加,由于导电通路32-34薄到约30-50μm以下,综合考虑通过晶界的界面的杂质和气体的扩散、电连接部位的劣化,是必要的。而且,在安装功率半导体元件的情况,考虑电流容量和发热,导电通路的膜厚最好在100-200μm。
一般,作为电极采用的材料,有如图1A所示的Z膜、图1C所示的X-Y膜两种。正如发明目的所述那样,由Z膜构成的导电通路40的里面,存在多个界面,如箭头所示,其结构是外来污染物质通过晶界41易于扩散。例如,作为污染物质有外部气氛的气体、湿气等。而且在采用焊料的情况,有熔剂等污染物质。这样,意味着固定于Z膜的金属细线42的固着力不好,而且与Z膜管芯键合的芯片43的固着力不好。
而且,如图1B所示,与因绝缘树脂44的收缩而发生的弯曲相反,Z膜40发生断线49,即使不发生断线49,各个晶粒45之间的间隔也会扩大,因此存在电阻大的问题。为了防止这些问题,必须增厚Z膜40,层叠多层Z膜。但是这样存在成膜时间延长、成本增加的问题。
另一方面,如图1C所示,X-Y膜构成的导电通路46的里面,界面47的露出量比Z膜40的少。而且朝向X-Y方向的结晶生长大,由于晶粒48层叠多层,如箭头所示,具有可以防止通过晶界47外来的污染物质的扩散的特点。这样,意味着可以大幅度抑制所述扩散产生的导电通路46表面的污染。
而且,与绝缘树脂44的收缩产生的弯曲相反,X-Y膜46不易发生断线,具有电阻小的特点。例如,可列举出压延处理的金属材料构成的导电箔作为X-Y膜。
图2展示了以Cu为主材料的压延导电箔(X-Y膜)和电解处理的电解箔(Z膜)的屈服特性。确认压延后退火的导电箔、仅压延的导电箔与电解箔相比,没有断裂而是坚固的。
如图1D所示,长度和面积均较大的导电通路,例如管芯焊盘、键合焊盘或布线采用这种X-Y膜,从而可知具有作为导电通路的优异特性。如图6-图11所示布线如果采用X-Y膜,则可知呈现比采用Z膜的布线更优异的特性。
但是如果考虑成本和电阻,以Cu作为主材料的压延铜箔为好。但是Cu的表面容易氧化,如果考虑金属细线的键合能力(ボンダビリティ)差,与Au凸起(バンプ)的接合性差,如图3所示那样,在这些电连接部位配置Z膜40则是重要的。即使发生弯曲,Z膜40产生裂缝49,由于X-Y膜46在下层稳定地配置,所以可防止断线。
而且对于Ag镀膜,2-10μm左右的膜厚在键合性方面是优异的,如果超过此膜厚成膜,可以说键合性劣化。而且对于Au镀膜,可知在0.2μm左右得到良好的键合性。这里,膜厚越厚,各种晶粒生长率差异开始变大,可以说是在其表面产生凹凸的原因。键合连接的球与Z膜之间,球仅与存在凹凸的Z膜接合,两者之间连接强度弱,可以说接触电阻大。但是采用薄的Z膜,虽然键合性高,但布线和管芯焊盘容易发生裂缝和断裂,可靠性相反降低。
因此,本发明的例如布线50、管芯焊盘、键合焊盘51的导电通路采用断裂强度高的X-Y膜46,支撑膜根据要求适当采用X-Y膜46,在此X-Y膜46上形成Z膜40。例如,在要求键合性和焊锡附着性的部分,根据要求采用Ag、Au、Ni、Pd等镀膜。但是如果考虑连接强度和成本,这种Z轴生长膜40采取上述那样的薄膜膜厚。因此,全部导电通路不仅由Z膜构成,而且X-Y膜46起支撑膜、保护膜的作用,通过在其上设置Z膜40,可以防止导电通路断裂、电阻增大等特性劣化。
图3对这方面进行说明。图3中,Z膜40产生裂缝49,分裂成两个区域40A、40B。但是,由于两个Z轴生长膜40A、40B与X-Y膜46电连接,所以等同于两个Z轴生长膜形成电连接,说明没有造成断线缺陷。箭头表示X-Y膜46构成针对外部气氛侵入的阻挡膜,防止Z膜40表面被污染。
在图1D和图3B中,除了上述特征之外,还有以下特征。在X-Y膜46的侧面,设置了弯曲结构52或房檐53,通过这种结构,埋置了绝缘树脂44的X-Y膜46不会被剥离,具有稳定的埋置状态的特点。因此在其上设置的Z膜40就能够保持更稳定的状态。
图4展示了用绝缘树脂44封装之前经半腐蚀的导电箔54。除了形成Z膜40的区域的表面上,生成Cu氧化膜(Cu2O、CuO)55,通过氧化膜55提高了与封装材料的绝缘树脂44的化学接合性,提高了导电通路与绝缘树脂的接合性。
而且在图4A中,在导电通路56上面全部区域都形成Z膜40,图4B中,除了主区域之外露出氧化膜55。图4B中,由于与图4A相比露出氧化铜55,所以导电通路56上面的接合性更为提高了。
在导电通路56提高半腐蚀形成分离沟57时,采用非各向异性腐蚀,产生以下效果。首先,由于产生弯曲结构52和房檐53,与产生铰钉效果的同时,氧化铜55的区域比平直的分离沟要扩大了,具有提高与绝缘树脂的接合性的优点。
最后参考图2B对刚性进行说明。图2B的下图展示的是把本导电箔54A处理成引线框架的形状,安装在模具中。半导体制造商采用引线框架输送模,这里采用的金属模具在半导体器件制造方面具有优点。本发明的构成明确地由图14~说明了,但是由于对导电箔54进行半腐蚀,将其安装在金属模具中,所以如果考虑容易处理,上下金属模具夹持的情况,则要求具有刚性。通过压延的导电箔,在制造方法简单地加入杂质,就可提高其刚性。如图2B所示,给出了杂质的重量百分比。类型A主要采用Ni、Si、Zn、Sn作为杂质。而类型B则掺入Zn、Sn、Cr作为杂质。再有,类型C掺入Zn、Fe、P。该表所示的杂质种类、重量百分比是一个例子,以Cu为主材料的导电箔如果具有刚性则是较好的。
另一方面,如果仅由镀膜构成导电箔,则制造方法上难以掺入杂质,实质上是由Cu构成的。因此产生导电箔软、操作性差的问题,必须设置支撑导电箔的支撑基片。
一般,引线框架的尺寸越大,半导体器件的安装数量就越多。但是,尺寸大的情况,相反由于弯曲,所以操作性降低。根据本发明,采用长220mm、宽45mm、厚70μm的矩形导电箔。而且,一般采用的引线框架,长度在~250mm、宽度在~75mm左右,厚度在~0.5mm左右,如果采用作为行业标准使用的导电箔,可以使用引线框架模具采用的金属模具。
以下针对具体的半导体器件结构进行说明。
本发明可以大致分类为,封装了一个TR的分离型,封装了一个IC或LSI的BGA型,安装了多个TR或多个IC的多片型,或者安装了多个TR、多个IC和/或无源元件、使用布线作为导电通路构成要求电路的混合型等。重要的是采用该方法就能实现半导体器件的大部分封装。
以下说明分离型半导体器件的第二实施例。
图5中对TR封装、将其埋置在绝缘树脂35中,露出导电通路32-34的里面。
标号32-标号34是构成集电极、基极和发射极的电路,在其表面被覆作为Z膜36的Ag,如图5C所示。此Z膜36是能够构成引线键合、管芯键合的膜,除此之外,考虑Au、Pd、Ni等。此导电通路32-34由于进行非各向异性腐蚀,其侧面形成弯曲结构52,而且在导电通路表面可以形成房檐53。因此通过采用这些中的至少一种,可以产生与绝缘树脂35的铰钉效果。而且,绝缘树脂35埋置在通过半腐蚀形成的分离沟57中,从半导体器件31里面露出的绝缘树脂35,构成封装外形。通过半腐蚀形成分离沟57,由于底部弯曲,具有减小芯片的摩擦系数的特点。由于分离沟57的底部向导电通路32-34的里面更为突出,所以具有可以防止导电通路之间短路,而且可以在该部分形成更厚的焊锡等连接材料的优点。
图5E展示了半导体芯片30按倒装法安装的半导体器件。例如,在半导体元件里面形成焊料球,熔融在导电通路。半导体芯片30与导电通路之间非常狭窄,在绝缘树脂35的浸透性差的情况,采用粘度低容易浸透间隙的底填(ァンダ—フィル)材料37。这种情况,与图5D不同,底填材料37填充分离沟57,形成外形的一部分。而且如图5D、5E所示,导电通路露出。因此,为了与安装基片的电路图形电连接,选择适当的导电材料覆盖。例如,如图5F所示,在露出部位形成焊锡等焊料材料SL、Au、Ag等电镀材料、导电膏等。
由于露出的导电通路面积不同,焊料材料厚度不同,最好如图5G所示,绝缘被膜38被覆在里面,露出形状实质上一定。
如发明实施例开始所述那样,即使成形为约0.55×0.55mm、厚0.24mm的半导体芯片,作为半导体器件31,可以实现1.6×2.3mm、厚0.5mm以下非常薄的半导体器件,可知适用于便携式机器、计算机等。
以下说明多片型(或者混合型)半导体器件的第二实施例。
接着,图6展示了混合型或者多片型的半导体器件60。仅由晶体管芯片构成的是多片型,其中如果安装了电容器、电阻等无源元件则就构成了混合型。
图24是音频电路,从左开始用粗的点划线包围地表示Audio Amp1ch电路部分、Audio Amp 2ch电路部分、切换电源电路。
在各个电路中,形成实线包围的电路作为半导体器件。首先用三种类半导体器件制备Audio Amp 1ch电路部分,用两种半导体器件一体制备2ch电路部分。
这里,作为一个例子图6展示了半导体器件60。如图6A所示,一体形成由TR1、TR2构成的电流密勒(カレントミラ一)电路、和由TR3、TR4构成的差动电路。该半导体器件60如图6B-图6E所示。这里,采用4个0.55×0.55mm、厚0.24mm的晶体管芯片,用Au细线键合。而且,半导体器件60的尺寸是2.9×2.9mm、厚0.5mm。图6C展示了Z膜36形成的管芯焊盘61、Z膜36形成的键合焊盘62、以及电连接管芯焊盘和键合焊盘的布线63。特别是,布线63图中设置得非常短,但是实际上如图11所示,也可以形成得较长。
该布线63是本发明的特征,具有采用压延铜箔作为布线主材料的特征。布线长度取决于图6A所示电路的规模,但是如果封装全部平面尺寸大,则配置的布线长度就长。再有绝缘树脂35和导电通路的热膨胀系数不同,每当发热就产生弯曲。但是如图2A所示,由于压延铜箔(X-Y膜)具有耐受这种反复弯曲(弯曲性)特性,可以抑制布线的断线。
以下是说明BGAA型半导体器件的第三实施例。
首先参考图7说明半导体器件70。图中,以下构成要素埋置在绝缘树脂71中。键合焊盘72A…,与该键合焊盘72A…一体的布线72B,与布线72B一体构成、在该布线72B另一端设置的外部连接电极72C被埋置。还有,包围导电图形72A-72C的区域设置的散热用电极72D,在散热用电极72D上设置的半导体元件73也被埋置。而且,半导体元件73通过绝缘性接合部件AD固定在所述散热用电极72D上,图7A中如点划线所示。为了可以键合,使键合焊盘72A位于半导体元件73周围那样地布图,半导体元件73的键合电极74和键合焊盘72A通过金属细线W电连接。
所述导电图形72A-72D的侧面,进行非各向异性腐蚀,这里具有由湿法腐蚀形成的弯曲结构,利用该弯曲结构产生铰钉效果。
本结构中,由半导体元件73、多个导电图形72A-72C、散热用电极72D、金属细线W、绝缘性接合部件AD、埋置这些的绝缘树脂71构成。在半导体元件73的配置区域,导电图形72B-72D上及其之间的分离沟75中形成所述绝缘性接合部件AD,特别是通过腐蚀形成的分离沟75中,设置所述绝缘性接合部件AD。因此,按导电图形72A-72D里面露出那样地封装绝缘树脂71。
作为绝缘性接合部件,最好是绝缘材料构成的接合剂、接合性的绝缘片。通过以下的制造方法即可知道,但最好是能够与晶片整体贴合,并且能够通过光刻布图的材料。
作为绝缘树脂可以使用环氧树脂等热固性树脂,聚酰亚胺树脂,对聚苯硫等热塑性树脂。绝缘树脂如果是采用模具加固的树脂、可以浸渍、涂敷覆盖的树脂,则可以全部采用树脂。
作为导电图形72A-72D,考虑半腐蚀性、电镀形成性、耐热应力、耐弯曲性,最好是压延形成的以Cu为主材料的电镀材料、压延铜箔。
本发明中,由于在所述分离沟75中填充绝缘树脂71和绝缘性接合部件AD,具有可以防止导电图形剥离的特点。作为腐蚀采用干法腐蚀、或者湿法腐蚀,进行非各向异性腐蚀,由此在导电图形侧面形成弯曲结构,可以产生铰钉效果。结果,可以实现导电图形72A-72D不会从绝缘树脂71剥离的结构。
但是,导电图形72A-72D的里面,在封装里面露出。因此,散热用电极72D的里面可以与安装基片上的电极固定,通过这种结构,从半导体元件73产生的热量可以在安装基片上的电极散热,可以防止半导体元件73温度上升,可以实现能够增大这部分半导体元件73的驱动电流的结构。而且作为散热用电极72D和安装基片上的电极的热接合的方法,也可以用焊料或导电膏连接,也可以在其间配置硅酮等热传导优异的绝缘材料。
由于本半导体器件是采用作为导电图形72A-72D的封装树脂的绝缘树脂71来支撑的,所以无需支撑基片。这种结构是本发明的特征。以往的半导体器件的导电通路,由于采用支撑基片(挠性片、印刷基片或陶瓷基片)来支撑,采用引线框架来支撑,所以即使本来不需要,也要附加良好的结构。但是,由于本电路装置由必需的最小限度的构成要素构成,不需要支撑基片,所以具有结构形状薄、重量轻,而且因为可以抑制材料费用从而廉价的特点。
而且,封装的里面露出导电图形72A-72D。如果用例如焊锡等焊料被覆此区域,为了扩展散热用电极72D的面积,需要浸润厚的焊料。由此,在安装基片上固定的情况,外部连接电极72C里面的焊料未在安装基片上的电极浸润,必定形成连接不良。
为了解决这种问题,在半导体器件70里面形成绝缘被膜76。如图7A的虚线所示的○,展示的是从绝缘被膜76露出的外部连接电极72C…、散热用电极72D。也就是除○之外的被绝缘被膜76覆盖,由于○部分的尺寸是实质上相同的尺寸,这里形成的焊料厚度实质上相同。这样,即使焊锡印刷之后,回流焊(リフロ一)之后也是同样的。即使是Ag、Au、Ag-Pd等导电膏也是同样的。采用这种结构,可以抑制电连接不良。考虑到半导体元件的散热性,散热用电极72D的露出部位77最好形成得比外部连接电极72C的露出尺寸大。由于外部连接电极72C…全部是实质上同一的尺寸,外部连接电极72C在全部区域过渡露出,散热用电极72D的里面的一部分最好按与外部连接电极72C实质上是同一尺寸地从绝缘被膜76露出。
通过设置树脂绝缘被膜76,在安装基片上设置的布线可以在半导体器件的里面延伸。一般,在安装基片侧设置的布线围绕所述半导体器件的固定区域迂回配置,通过形成所述绝缘被膜18,可以不迂回地配置。但是由于绝缘树脂71、绝缘性接合部件AD比导电图形更为突出,所以可以在安装基片侧的布线与导电图形之间形成间隙,可以防止短路。
以下是说明BGA型半导体器件78的第四实施例。
首先在图8中,倒装地安装半导体元件73,在导电图形上配置防止流动膜DM,采用底填材料AF代替绝缘性接合部件AD,除此之外,其余均相同,所以仅针对不同点进行说明。
首先,利用焊锡等焊料、导电膏、各向异性导电树脂等电连接部件SD,对半导体元件73的键合电极74与焊盘72A进行电连接。
为了防止电连接部件SD流动,在导电图形设置防止流动膜DM。例如,以焊锡为例,在导电图形72A-72C的至少一部分形成防止流动膜DM,用该膜阻止焊锡的流动。作为防止流动膜是与焊锡的浸润性差的膜,例如高分子膜(焊锡保护膜)或者是在Ni表面形成的氧化膜等。
至少在配置焊锡的区域周围设置该防止流动膜,防止焊锡等焊料、Ag膏等导电膏、导电树脂的流动,并与这些电连接部件的浸润性差。例如,在设置焊锡的情况,焊锡熔融时利用防止流动膜DM来阻挡,通过表面张力形成良好半球形的焊锡。在附着焊锡的半导体器件的键合电极74的周围,由于形成钝化(パシベ一ション)膜,焊锡仅浸润键合电极。因此如果通过焊锡连接半导体元件和焊盘,则保持一定高度的贝壳柱状的焊锡。而且由于可以利用焊锡量来调节高度,所以可在半导体元件与导电图形之间设置一定的间隙,在其间浸入清洗液,而且浸入粘性低的粘结剂(这里是底填材料)液成为可能。并且,通过在连接区域之外的全部区域被覆防止流动膜DM,可以提高与底填材料AF的接合性。
本结构由半导体元件73、多个导电图形72A-72C、散热用电极72D、底填材料AF、埋置这些的绝缘树脂71构成。如上所述,在半导体元件73的配置区域,导电图形72A-72C之上和它们之间的分离沟中填充所述底填材料AF。特别是在通过腐蚀形成的分离沟75中填充所述底填材料AF,用绝缘树脂71对包含这些的全部进行封装。这样利用绝缘树脂71和底填材料AF,支撑所述导电图形72A-72C、半导体元件73。
作为这种底填材料AF,最好是能够在半导体元件与导电图形之间浸透的材料,混入起隔离物的功能、赋予热传导的填料更好。
根据本发明,由于在所述分离沟75中填充绝缘树脂71和底填材料AF,所以具有利用铰钉效果能够防止导电图形剥离的特点。而且作为腐蚀,采用干法腐蚀或者湿法腐蚀,进行非各向异性腐蚀,由此可以把焊盘72A…的侧面形成弯曲结构。结果,可以实现导电图形72A-72D不会从封装中剥离的结构。
而且,导电图形72A-72D的里面从绝缘树脂71露出。特别是,散热用电极72D的里面,可以固定在图中未示出的安装基片上的电路图形。利用这种结构,从半导体元件73产生的热量可以在安装基片上的第二电路图形散热,可以防止半导体元件73的温度上升,可以增大这部分半导体元件73的驱动电流。而且,在不考虑散热性的情况下,也可以省略散热用电极72D。此时,可以省略安装基片的电路图形。
本半导体器件由于用作为封装树脂的绝缘树脂71和底填材料AF支撑导电图形72A-72C,所以不需要支撑基片。这种结构是本发明的特征。即使象已有技术部分说明的那样,以往的半导体器件的铜箔图形由支撑基片(挠性片、印刷基片或陶瓷基片),由引线框架支撑,所以即使本来不需要,也要附加良好的结构。但是,本电路装置,由于由必要的最小限度的构成要素来构成,不需要支撑基片,所以具有形状薄、重量轻,无需耗费更多材料费从而廉价的特点。
本半导体器件具有通过外部连接电极72C、焊料的第一散热通道,和通过散热用电极72D、焊料的第二散热通道,通过这些可以提高半导体元件的驱动能力。
半导体元件73的里面最好从绝缘树脂膜71露出。通过这种露出可以提高散热部件与半导体元件73的热结合。但是,在半导体元件73与散热部件的电结合没有被阻止的情况,在其间设置硅酮树脂等绝缘材料。这种硅酮树脂耐热性强,通过混入填料可使热传导性优异,以往经常采用。
以下是说明BGA型半导体器件79的第五实施例。
在图8中,在焊盘72A一体形成布线72B、外部连接电极72C,但是如图9所示,焊盘72A的里面构成外部连接电极。
由于键合焊盘72A构成矩形,所以从绝缘被膜76露出的散热用电极72D的图形也形成为同一图形。而且考虑绝缘性接合部件AD的固着性,散热用电极72D被分割成多部分地形成沟80。而且,标号W是金属细线。
半导体元件73最好倒装地安装。这种情况,如图8所示,采用底填材料。根据本实施例,不设置布线和外部连接电极,可以扩大散热用电极72D,具有提高半导体元件散热的优点。
以下是说明多片型半导体器件81的第六实施例。
应用图9的的安装方法,参考图10对安装了多个半导体芯片72A、72B的半导体器件81进行说明。
根据本实施例,采用桥接(ブリッヂ)83电连接第一半导体芯片73A和第二半导体芯片73B。如果用引线框架形成这种桥接83,则由于形成岛状,必须用悬吊簧片或接合带支撑。但是正如从后续的制造方法可知那样,导电箔的半腐蚀、树脂模制之后,由于分离导电通路,所以具有不需要这些支撑部件的优点。哪个半导体芯片82A、82B都是由连接的金属细线W通过球形键合来连接,由于在桥接83侧形成自动点焊键合,所以具有自动点焊键合的冲击不会施加到芯片的特点。
在键合焊盘72,如图7所示,布线、外部连接电极最好设计成为一体。这种情况,第一管芯焊盘82A、第二管芯焊盘82B的尺寸比半导体芯片的尺寸小,最好扩大布线、外部连接电极的延伸区域。而且半导体芯片73和管芯焊盘82用焊锡等焊料电连接。但是在所述布线或外部连接电极在半导体芯片之下延伸的情况,考虑到防止短路,最好设置绝缘性接合部件AD。
另一方面,也可以倒装地安装半导体芯片73。如图10C所示。该结构实质上与图8是相同的。为了采用焊锡等焊料连接半导体芯片和焊盘,在其间浸透底填材料AF等。
以下是说明半导体器件的特征及其制造方法的第七实施例。
图12-13所示特征,形成由绝缘树脂90构成的突出部位91,导电通路92比所述突出部位91更向内侧深入,在此形成凹进部位93。由此,可以实现增大焊锡94的连接强度、防止焊锡或导电通路92彼此的短路、半导体器件里面的摩擦系数的减小。
以下参考图14-图21说明制造方法。
首先如图14所示,制备片状的导电箔100。考虑焊料的附着性、键合性、电镀性,选择该导电箔100的材料,采用以Cu为主材料的压延导电箔作为材料。为了在各工序容易处理,进行杂质扩散,增加导电箔的刚性。而且,杂质一例如2B所示。
考虑到后续的腐蚀,导电箔的厚度最好在35um-300μm左右,这里采用70μm(2盎司)的铜箔。但是,即使在300μm以上、35μm以下基本也是良好的。如下所述,可以形成比导电箔100的厚度要浅的分离沟101。考虑到后续的输送模、一般后续工序使用的输送模的模具、这里采用的标准的导电箔,则导电箔的尺寸最好是,长度为~220m左右,宽度为~75mm,厚度为~300mm左右,切成长方形。如果采用这种尺寸,则可以使用市售的输送模装置、模具、导电箔,成本上具有优点。
而且,按预定宽度制备片状导电箔100,卷绕成辊状,在后续的各工序中容易搬运。(参见以上图14)。
接着,对至少除去导电通路102的区域的导电箔100,按比导电箔100的厚度更薄地进行去除工序。
首先,在Cu箔100上形成光刻胶(耐腐蚀掩模)PR,对光刻胶PR进行布图,以便使除导电通路102的区域之外的导电箔100露出(以上参见图15)。
这样,如图16所示,通过所述光刻胶PR进行腐蚀。
通过腐蚀形成的分离沟101的深度例如是50μm,其侧面通过腐蚀处理或粗糙化处理,形成粗糙面,因此提高了与绝缘树脂103的接合性。
而且该分离沟101的侧面利用去除方法形成不同的结构。该去除工序可以采用湿法腐蚀、干法腐蚀、激光蒸发、芯片切割(ダィシング)。也可以压制形成。湿法腐蚀情况的腐蚀,主要采用氯化铁或氯化铜,所述导电箔浸渍在腐蚀剂中,用腐蚀剂淋浴。这里,湿法腐蚀由于一般是非各向异性的腐蚀,所以侧面如图16B、图16C所示那样地成为弯曲结构。例如在图16B中,选择贴合性良好的耐腐蚀掩模,如果采用Ni等,则形成房檐。导电通路本身构成房檐,与在导电通路上形成导电被膜一起地形成房檐。根据耐腐蚀掩模的形成方法,如图16C所示,成为半圆的情况。无论在哪种情况都形成弯曲结构104,所以具有产生铰钉的效果。
而且在干法腐蚀的情况,可以进行各向异性、非各向异性的腐蚀。现在,不可能通过反应性离子腐蚀去除Cu,但是可以通过溅射去除。根据溅射的条件可以进行各向异性、非各向异性腐蚀。
至于激光,可以直接照射激光形成分离沟,这种情况,在提到的那些分离沟101的侧面形成为平直。
至于芯片切割,不可能形成曲折复杂的图形,但是可以形成栅格状的分离沟。
而且,在图16中,代替光刻胶PR,可以选择地被覆对腐蚀液有耐蚀性的导电被膜。如果在构成导电通路的部分选择地被覆,则该导电被膜构成腐蚀保护膜,不采用光刻胶也可以腐蚀成分离沟。考虑作为这种导电被膜的材料,有Ni、Ag、Au、Pt或Pd等。而且这些耐蚀性导电被膜具有可以作为管芯焊盘、键合焊盘原样应用的特点。
例如Ag被膜,与Au接合,或与焊料接合。由此如果在芯片里面被覆Au被膜,则可以直接在导电通路51上的Ag被膜上热压芯片,可以通过焊锡等焊料固定芯片。而且,由于Au细线可以接合在Ag的导电被膜,所以能够引线键合。因此,这些导电被膜具有可以直接作为管芯焊盘、键合焊盘应用的优点。(以上参见图16)
接着,如图17所示,是在形成了分离沟101的导电箔100上电连接安装电路元件105的工序。
作为电路元件105,如图1-图13说明那样,有晶体管、二极管、IC芯片等半导体元件105A,片式电容器、片式电阻等无源元件105B。厚度加厚,可以安装晶片级CSP等代表的CSP、BGA等倒装型半导体元件。
这里,作为半导体裸芯片的晶体管芯片105A与导电通路102A管芯键合,通过利用热压的球形键合或者超声波的湿法键合等固定的金属细线106,连接发射极和导电通路105B、基极与导电通路105B。而且105B是片式电容器等无源元件和/或有源元件,这里采用片式电容器,利用焊锡等焊料或者导电膏107固定。(以上参见图17)
再有,如图18所示,是在所述导电箔100和分离沟101上附着绝缘树脂103的工序。这可以通过输送模、注射成型、或浸渍来实现。作为树脂材料,环氧树脂等热固化树脂可以用输送模实现,聚酰亚胺树脂、对聚苯硫等热塑性树脂可以用注射成型来实现。
本实施例的特征是调整导电箔100表面被覆的绝缘树脂的厚度,以便从电路元件最顶部被覆约100μm。该厚度既可以考虑强度从而加厚,也可以减薄。
本工序的特征是,被覆绝缘树脂103,直到作为导电通路102的导电箔100成为支撑基片。例如,采用印刷基片或柔性片的CSP,采用本来不需要的支撑基片(印刷基片或柔性片)形成导电通路,但是本发明中,作为支撑基片的导电箔100是作为导电通路的必要材料,因此,具有尽可能地节省构成材料制作的优点,可以实现成本降低。
而且,分离沟101由于比导电箔厚度形成得更浅,所以导电箔100不必分别地分离作为导电通路102。因此,从电路元件的安装到芯片切割的处理,特别是模制绝缘树脂时,向模具的输送,向模具的安装的操作非常容易。而且如上所述,由于添加了杂质,导电箔被赋予了刚性,更加提高了操作性。
接着,是对导电箔的里面进行化学和/或物理地去除,分离成为导电通路102的工序。这里,除此之外的工序是进行研磨、研削、腐蚀、激光的金属蒸发等工序。
采用该分离法形成的半导体器件如图21A-图21C所示。
首先,在图21A中,研磨最终的里面,使导电通路102的里面与分离沟101的里面一致。
接着,在图21B中,从至少分离沟101露出的前部进行腐蚀。一般,由于完全分离导电通路102,由于进行过腐蚀,所以导电通路102一侧比分离沟101的里面更为凹进。
在图21C中,通过图18的阶段,在导电箔100的里面的成为外部连接电极的部位形成耐腐蚀掩模,通过该掩模进行腐蚀。由此,形成比分离沟101的里面更突出的导电通路102的一部分。
而且,在图21A、B所示的露出面如图18的虚线所示。
图19中展示了导电通路102分离的半导体器件的一个例子。而且是通过湿法腐蚀进行分离的。
并且,为了防止与安装基片上的布线短路,在半导体器件的里面形成绝缘被膜108。而且,109是焊锡等焊料。绝缘被膜108由于不浸润焊料,所以形成完好的半球状焊料。
结果,分离成约40μm厚的导电通路102。(以上参见图20)
而且,最好在导电通路102的里面被覆Au或Ag导电被膜。在图14-图17的导电箔的里面,最好如上述那样形成导电被膜。被覆方法例如是电镀。该导电被膜最好是耐腐蚀的材料。
在本制造方法中,在导电箔100仅安装了半导体芯片和片式电容器,但是也可以按矩阵形式对其进行配置成为一个单元。这种情况下,进行芯片切割以便分离成为每一个单元。
正如从上述制造方法可知,通过本制造方法可以制造各种半导体器件。安装作为有源元件(半导体芯片)的晶体管、二极管、IC或者安装了一个LSI的分离型或BGA型、或者安装多个上述有源元件的多片型,再有,安装作为有源元件(半导体芯片)的晶体管、二极管、IC或LSI,作为无源元件的片式电阻、片式电容器,为了实现要求的电路形成布线作为导电通路,可以开发如此构成的混合IC型等各种半导体器件。
根据以上制造方法,在绝缘树脂中埋置导电通路,可以实现在绝缘树脂的里面露出导电通路51的里面的半导体器件。
本制造方法具有应用绝缘树脂作为支撑基片、可以进行导电通路的分离操作的特点。绝缘树脂是埋置导电通路的材料所必需的材料,不必需要不要的支撑基片。因此,具有可以用最小限度的材料制造,可以实现降低成本的特点。
正如从上述制造方法可知那样,通过导电通路的分离方法,如图12A所示,能够在导电通路的里面形成凹进部位93。而且构成导电通路侧面的曲面与分离沟侧面的曲面一致的封装。分离沟的底部由于是通过非各向异性腐蚀形成的,呈现曲面,如三角形所示的空白区域93A。
利用该分离沟的曲面,即使熔融的焊锡设置在分离沟的部位,但由于分离沟呈现倾斜并且如箭头所示因焊锡表面张力而使焊锡流动,可能形成全部分离的岛状半球焊锡。由于设置空白区域93A,所以形成焊锡脱离区域,可以抑制熔融的焊锡邻接成一体从而短路的现象。
图12B是分离沟的突出部位成为一部分平坦化。在腐蚀的情况下,通过导电通路的间隔,使分离沟的深度不同,突出部位91的高度成为不同。这种情况下,可以假设半导体器件不能水平地配置的情况,此时,分离导电通路之后,研磨半导体器件的里面,使突出部位的高度全部统一。FL所示部位是平坦化的部位。
图13展示了在安装基片520上安装半导体器件的结构。在该安装基片的导电通路上形成的电路图形521,由于半导体芯片与连接的导电通路522键合,所以具有能够使半导体芯片的热量向电路图形散热的优点。
图12所示的标号H是表示突出部位91的顶部从导电通路的里面突出。H约是20μm。在导电通路里面固化的焊料在固化状态,必须形成得比突出部位91更高。但是在熔融时,由于元件的自重、外力使焊锡94弄坏,突出部位91成为阻挡部位,如图13所示突出部位与安装基片520接触。但是由于突出部位91呈现弯曲,半导体器件的里面的摩擦系数小,半导体器件容易移动,具有容易进行自对准的特点。
图22是说明通过采用本发明的半导体器件,例如尺寸可以减小。图中的照片是同等倍率的,从左开始展示了采用引线框架的单品SMD、采用引线框架的复合SMD以及本发明的半导体器件。单品SMD是模制一个TR,复合TR是模制两个TR。本发明的半导体器件是安装图6所示电路的半导体器件,封装了4个TR。从图中可知,虽然封装了复合SMD的两倍元件,但是本发明的半导体器件的尺寸,仅比含有引线框架的复合SMD稍大一些。而且封装1个TR的半导体器件在右侧展示了一次。由此可知,根据本发明可以实现小型、薄型半导体器件,最适用于便携式电子装置。
最后安装本发明的半导体器件的安装基片如图23所示。是在图25所示的已有安装基片上重新形成电路图形,进行安装。正如从图23可见那样,简化了安装基片的电路图形,可以形成宽的间隔。这样,可以形成更密集的安装基片的电路图形,安装基片小型化成为可能。而且半导体芯片的管芯键合数量、引线键合数量减少,安装基片上的组装工序数量大幅度减少。而且对于安装基片可以采用任何种类的金属细线。例如在图25中,采用小信号类用的40μm的Au线或者Al线、大信号类用的150μm和300μm的Al线。在这三种之内,与至少一种的金属细线连接的半导体元件,如果全部采用本结构,则该金属细线的键合全部不需要。例如,Au线和Al线由于键合机构完全不同,分别采用各自的键合来连接。但是对用Au线连接的半导体元件全部利用这种结构封装,用Au线跳线的部分如果用Al代替,则安装基片的组装就全部不需要Au线的键合了。这样,大幅度简化了组装工序。
以往采用的引线框架的封装,在封装侧面必然露出切割的悬吊簧片、连杆等。因此考虑与该露出部分的接触,封装与封装不能接连配置。但是根据本发明,由于除里面之外全部用绝缘树脂封装,半导体器件与半导体器件可以接触地配置在安装基片上。
而且,在半导体器件的里面,由绝缘树脂构成的突出部位成为曲面,这种里面的摩擦系数非常小。而且还因半导体器件自身具有薄型轻量,因而具有施加焊锡时半导体器件自然进行自对准的特点。
如果采用金属基片作为安装基片,半导体器件的热量可以通过金属基片散热,可以抑制作为安装基片整体的组件的温度上升。
通过以上说明可知,根据本发明,可以以分离型、BGA型、多片型、混合型等各种范围的形式,安装成为薄型的半导体器件。由于是薄型的,存在半导体器件弯曲的问题,但由于采用压延的X-Y膜作为导电通路,所以能够防止因弯曲、树脂收缩引起的导电通路的断线。而且作为半导体器件采用的电连接部分,通过在下层采用X-Y膜,可以防止连接部位的污染,可以向用户提供在封装后的时效或次品率方面良好的半导体器件。而且细长形成的布线比其它导电通路容易施加应力,但通过采用X-Y膜可以抑制布线的断线。
由于采用本发明的方法,绝缘树脂里面和导电通路的侧面成为同一的腐蚀面。特别是,绝缘树脂里面形成弯曲,在与这种弯曲部位邻接的部位形成空白区域。由此,足以作为熔融的焊锡的流动区域,可以减小半导体器件里面的摩擦系数。
在半腐蚀之后,由于导电箔经过生成氧化膜的热处理工序,在其表面上形成Cu的氧化物。该氧化物可以提高导电箔与绝缘树脂的接合性。

Claims (24)

1.一种半导体器件,其特征在于包括:由比Z轴方向更大的X轴、Y轴方向的结晶构成的多个导电通路;与所述导电通路电连接的半导体芯片;覆盖所述半导体芯片,并且填充所述导电通路之间分离沟,露出所述导电通路里面,一体支撑的绝缘树脂。
2.根据权利要求1的半导体器件,其特征在于,所述绝缘树脂的里面和所述导电通路的侧面,成为实质上同样的腐蚀面。
3.根据权利要求1或2的半导体器件,其特征在于,所述导电通路的里面形成为比所述分离沟的里面更为凹进。
4.根据权利要求1的半导体器件,其特征在于,在与所述绝缘树脂接触的导电通路的表面,形成所述导电材料的氧化物。
5.根据权利要求1-4中任一项的半导体器件,其特征在于,所述绝缘树脂的厚度实质上比1mm更薄,所述导电通路的厚度是压延工序可能形成的厚度。
6.一种半导体器件,其特征在于包括:由比Z轴更大的X轴、Y轴方向的结晶所形成的多个导电通路;在所述导电通路上面形成的,比X轴、Y轴方向更大的主要是Z轴方向的结晶所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路里面,一体支撑的绝缘树脂。
7.一种半导体器件,其特征在于包括:由比Z轴更大的X轴、Y轴方向的结晶所形成的多个导电通路;在所述导电通路上面形成的,比X轴、Y轴方向更大的主要是Z轴方向的结晶所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路里面,一体支撑的绝缘树脂,
所述绝缘树脂的里面和所述导电通路的侧面,成为实质上同样的腐蚀面。
8.一种半导体器件,其特征在于包括:由比Z轴更大的X轴、Y轴方向的结晶所形成的多个导电通路;在所述导电通路上面形成的,通过电镀主要是Z轴方向的结晶生长大的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路里面,一体支撑的绝缘树脂,
所述导电通路的侧面被腐蚀成曲面,所述绝缘树脂里面的至少一部分是与腐蚀面连续的曲面。
9.根据权利要求6-8中任一项的半导体器件,其特征在于,所述腐蚀面是与通过非各向异性腐蚀形成的面连续的曲面。
10.根据权利要求6-9中任一项的半导体器件,其特征在于,所述导电通路的里面形成为比所述绝缘树脂里面更为凹进。
11.根据权利要求6-10中任一项的半导体器件,其特征在于,与所述绝缘树脂接触的所述导电通路,在表面形成氧化物。
12.根据权利要求6-8中任一项的半导体器件,其特征在于,在所述导电通路的里面形成导电被膜。
13.根据权利要求6-9中任一项的半导体器件,其特征在于,所述导电被膜在所述导电通路的表面构成房檐。
14.根据权利要求6-13中任一项的半导体器件,其特征在于,从所述绝缘树脂露出的导电通路,除了电连接部位之外,其余被绝缘树脂覆盖。
15.根据权利要求6-14中任一项的半导体器件,其特征在于,设置布线作为所述导电通路,从所述绝缘树脂露出的导电通路,除了电连接部位之外,其余被绝缘被膜覆盖。
16.一种半导体组件,其特征在于,半导体器件包括:由比Z轴更大的X轴、Y轴方向的结晶生长的导电材料所形成的多个导电通路;在所述导电通路的上面形成的,主要是Z轴方向的结晶生长所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路的里面,一体支撑的绝缘树脂;半导体器件通过所述露出部位安装在所述安装基片上。
17.一种半导体组件,其特征在于,半导体器件包括:由比Z轴更大的X轴、Y轴方向的结晶生长的导电材料所形成的多个导电通路;在所述导电通路的上面形成的,主要是Z轴方向的结晶生长所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路的里面,一体支撑的绝缘树脂,所述绝缘树脂的里面和所述导电通路的侧面是实质上连续的曲面;半导体器件通过所述露出部位在所述安装基片上安装半导体器件。
18.一种半导体组件,其特征在于,半导体器件包括:由比Z轴更大的X轴、Y轴方向的结晶生长的导电材料所形成的多个导电通路;在所述导电通路的上面形成的,主要是Z轴方向的结晶生长所形成的导电被膜;与所述导电被膜电连接的半导体芯片;覆盖所述半导体芯片,而且填充所述导电通路之间的分离沟,露出所述导电通路的里面,一体支撑的绝缘树脂,所述导电通路的侧面腐蚀成为弯曲,所述绝缘树脂的里面至少一部分是与该腐蚀面实质上一致;半导体器件通过所述露出部位安装在所述安装基片上。
19.根据权利要求16-18中任一项的半导体组件,其特征在于,所述导电通路的里面和所述安装基片通过焊料连接,所述导电通路的里面或/和所述安装基片上的连接图形,设置防止焊料流动的被膜。
20.根据权利要求16-18中任一项的半导体组件,其特征在于,所述腐蚀面是与通过非各向异性腐蚀所形成的面实质上相同的曲面。
21.根据权利要求16-19中任一项的半导体组件,其特征在于,所述导电通路的里面形成为比所述绝缘树脂的里面更为凹进。
22.根据权利要求16-21中任一项的半导体组件,其特征在于,与所述绝缘树脂接触的所述导电通路,其表面上形成氧化物。
23.根据权利要求16-18中任一项的半导体组件,其特征在于,在所述导电通路的里面形成导电被膜。
24.根据权利要求23的半导体组件,其特征在于,所述导电被膜在所述导电通路表面构成房檐。
CNB011123893A 2000-09-20 2001-02-15 半导体器件和半导体组件 Expired - Fee Related CN1244139C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000285562A JP3706533B2 (ja) 2000-09-20 2000-09-20 半導体装置および半導体モジュール
JP285562/00 2000-09-20

Publications (2)

Publication Number Publication Date
CN1344014A true CN1344014A (zh) 2002-04-10
CN1244139C CN1244139C (zh) 2006-03-01

Family

ID=18769610

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011123893A Expired - Fee Related CN1244139C (zh) 2000-09-20 2001-02-15 半导体器件和半导体组件

Country Status (6)

Country Link
US (1) US6528879B2 (zh)
EP (1) EP1191590A3 (zh)
JP (1) JP3706533B2 (zh)
KR (3) KR100443023B1 (zh)
CN (1) CN1244139C (zh)
TW (1) TW533754B (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679687B2 (ja) * 2000-06-08 2005-08-03 三洋電機株式会社 混成集積回路装置
JP4611569B2 (ja) * 2001-05-30 2011-01-12 ルネサスエレクトロニクス株式会社 リードフレーム及び半導体装置の製造方法
DE10148042B4 (de) * 2001-09-28 2006-11-09 Infineon Technologies Ag Elektronisches Bauteil mit einem Kunststoffgehäuse und Komponenten eines höhenstrukturierten metallischen Systemträgers und Verfahren zu deren Herstellung
US6903447B2 (en) * 2002-05-09 2005-06-07 M/A-Com, Inc. Apparatus, methods and articles of manufacture for packaging an integrated circuit with internal matching
US6828658B2 (en) * 2002-05-09 2004-12-07 M/A-Com, Inc. Package for integrated circuit with internal matching
JP2005524995A (ja) * 2002-05-09 2005-08-18 メイコム インコーポレイテッド 内部インピーダンス整合回路を有する集積回路
US20040037059A1 (en) * 2002-08-21 2004-02-26 Leon Stiborek Integrated circuit package with spacer
JP2004128228A (ja) 2002-10-02 2004-04-22 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004186460A (ja) * 2002-12-04 2004-07-02 Sanyo Electric Co Ltd 回路装置の製造方法
KR100688596B1 (ko) * 2003-03-06 2007-03-02 페어차일드코리아반도체 주식회사 몰디드 리드리스 패키지 및 그 제조 방법
US6870236B2 (en) * 2003-05-20 2005-03-22 Honeywell International, Inc. Integrated resistor network for multi-functional use in constant current or constant voltage operation of a pressure sensor
US20040262781A1 (en) * 2003-06-27 2004-12-30 Semiconductor Components Industries, Llc Method for forming an encapsulated device and structure
JP4744070B2 (ja) * 2003-09-30 2011-08-10 三洋電機株式会社 半導体装置
JP4744071B2 (ja) * 2003-09-30 2011-08-10 三洋電機株式会社 半導体モジュール
DE10348715B4 (de) * 2003-10-16 2006-05-04 Infineon Technologies Ag Verfahren zum Herstellen eines Flachleiterrahmens mit verbesserter Haftung zwischen diesem und Kunststoff sowie Flachleiterrahmen
JP4335720B2 (ja) * 2004-03-19 2009-09-30 Necエレクトロニクス株式会社 データ出力装置および半導体装置の製造方法
JP4972306B2 (ja) 2004-12-21 2012-07-11 オンセミコンダクター・トレーディング・リミテッド 半導体装置及び回路装置
JP2006229190A (ja) 2005-01-24 2006-08-31 Sanyo Electric Co Ltd 半導体装置
DE102005043657B4 (de) * 2005-09-13 2011-12-15 Infineon Technologies Ag Chipmodul, Verfahren zur Verkapselung eines Chips und Verwendung eines Verkapselungsmaterials
US7772036B2 (en) * 2006-04-06 2010-08-10 Freescale Semiconductor, Inc. Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
US20080079127A1 (en) * 2006-10-03 2008-04-03 Texas Instruments Incorporated Pin Array No Lead Package and Assembly Method Thereof
US8115285B2 (en) * 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US7834431B2 (en) * 2008-04-08 2010-11-16 Freescale Semiconductor, Inc. Leadframe for packaged electronic device with enhanced mold locking capability
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP4832486B2 (ja) * 2008-09-01 2011-12-07 三洋電機株式会社 回路装置
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
TW201039383A (en) * 2009-04-17 2010-11-01 Arima Optoelectronics Corp Semiconductor chip electrode structure and manufacturing method thereof
JP5195647B2 (ja) * 2009-06-01 2013-05-08 セイコーエプソン株式会社 リードフレームの製造方法及び半導体装置の製造方法
KR101645720B1 (ko) 2009-09-15 2016-08-05 삼성전자주식회사 패턴 구조물 및 이의 형성 방법.
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
WO2011145176A1 (ja) * 2010-05-18 2011-11-24 トヨタ自動車株式会社 半導体装置及びその製造方法
CN102543784B (zh) * 2012-03-28 2014-07-02 上海交通大学 一种使用镍微针锥的固态热压缩低温键合方法
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
CN105159177B (zh) * 2015-09-11 2018-11-02 湖北三江航天红峰控制有限公司 一种小型化电液舵机控制电路
JP6542112B2 (ja) * 2015-11-30 2019-07-10 大口マテリアル株式会社 多列型led用リードフレーム、並びにledパッケージ及び多列型led用リードフレームの製造方法
JP7304145B2 (ja) * 2018-11-07 2023-07-06 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
US20220157707A1 (en) * 2020-11-17 2022-05-19 Panjit International Inc. Thin semiconductor package and manufacturing method thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (ja) * 1983-05-12 1984-11-27 Sony Corp 半導体装置のパツケ−ジの製造方法
US5045408A (en) * 1986-09-19 1991-09-03 University Of California Thermodynamically stabilized conductor/compound semiconductor interfaces
JP2841386B2 (ja) * 1988-10-03 1998-12-24 松下電器産業株式会社 半導体装置およびその製造方法
JPH02240940A (ja) 1989-03-15 1990-09-25 Matsushita Electric Ind Co Ltd 集積回路装置の製造方法
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JP2840317B2 (ja) 1989-09-06 1998-12-24 新光電気工業株式会社 半導体装置およびその製造方法
JP2781018B2 (ja) 1989-09-06 1998-07-30 新光電気工業株式会社 半導体装置およびその製造方法
WO1995026047A1 (en) 1994-03-18 1995-09-28 Hitachi Chemical Company, Ltd. Semiconductor package manufacturing method and semiconductor package
FR2722915B1 (fr) * 1994-07-21 1997-01-24 Sgs Thomson Microelectronics Boitier bga a moulage par injection
FR2723257B1 (fr) * 1994-07-26 1997-01-24 Sgs Thomson Microelectronics Boitier bga de circuit integre
JP3304705B2 (ja) * 1995-09-19 2002-07-22 セイコーエプソン株式会社 チップキャリアの製造方法
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3521758B2 (ja) * 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
JPH11163024A (ja) * 1997-11-28 1999-06-18 Sumitomo Metal Mining Co Ltd 半導体装置とこれを組み立てるためのリードフレーム、及び半導体装置の製造方法
JPH11195742A (ja) * 1998-01-05 1999-07-21 Matsushita Electron Corp 半導体装置及びその製造方法とそれに用いるリードフレーム
JP3436159B2 (ja) * 1998-11-11 2003-08-11 松下電器産業株式会社 樹脂封止型半導体装置の製造方法

Also Published As

Publication number Publication date
KR20040071675A (ko) 2004-08-12
KR20030091865A (ko) 2003-12-03
JP3706533B2 (ja) 2005-10-12
US20020033530A1 (en) 2002-03-21
KR100459348B1 (ko) 2004-12-03
KR20020022527A (ko) 2002-03-27
CN1244139C (zh) 2006-03-01
TW533754B (en) 2003-05-21
EP1191590A3 (en) 2004-04-14
JP2002093847A (ja) 2002-03-29
US6528879B2 (en) 2003-03-04
KR100443023B1 (ko) 2004-08-04
EP1191590A2 (en) 2002-03-27
KR100550499B1 (ko) 2006-02-09

Similar Documents

Publication Publication Date Title
CN1244139C (zh) 半导体器件和半导体组件
CN1216419C (zh) 布线基板、具有布线基板的半导体装置及其制造和安装方法
CN1222995C (zh) 混合集成电路装置
CN1227957C (zh) 电路装置的制造方法及电路装置
CN1173400C (zh) 板状体和半导体器件的制造方法
CN1246901C (zh) 电路装置及其制造方法
CN1171298C (zh) 半导体器件
CN1096116C (zh) 半导体器件及其制造方法
CN1199269C (zh) 半导体装置及其制造方法和制造装置
CN1779951A (zh) 半导体器件及其制造方法
CN1320964A (zh) 半导体器件及其制造方法
CN1882224A (zh) 配线基板及其制造方法
CN1836325A (zh) 用于封装集成电路器件的方法和设备
CN1893051A (zh) 半导体器件
CN1723556A (zh) 可叠置的半导体器件及其制造方法
CN1574346A (zh) 一种制造半导体器件的方法
CN1441489A (zh) 半导体装置及其制造方法、电路板和电子仪器
CN1855479A (zh) 多层结构半导体模块及其制造方法
CN1697148A (zh) 半导体器件及制造该半导体器件的方法
CN101076884A (zh) 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
CN1873935A (zh) 配线基板的制造方法及半导体器件的制造方法
CN1197150C (zh) 半导体装置、安装基板及其制造方法、电路基板和电子装置
CN1351376A (zh) 半导体模块及其制造方法
CN1203543C (zh) 半导体器件和半导体模块
CN1722414A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060301

Termination date: 20150215

EXPY Termination of patent right or utility model