JP4832486B2 - 回路装置 - Google Patents
回路装置 Download PDFInfo
- Publication number
- JP4832486B2 JP4832486B2 JP2008223923A JP2008223923A JP4832486B2 JP 4832486 B2 JP4832486 B2 JP 4832486B2 JP 2008223923 A JP2008223923 A JP 2008223923A JP 2008223923 A JP2008223923 A JP 2008223923A JP 4832486 B2 JP4832486 B2 JP 4832486B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- conductive foil
- separation groove
- conductive pattern
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
、チップサイズと同等若しくは若干大きいサイズの半導体装置が開発されている。しかしながら一般的なCSPでは、装置全体を支持するために、ガラスエポキシ基板やセラミック基板等の支持基板が必須の構成要素であった。このことから、支持基板が厚い部材であるために半導体装置全体のサイズが大きくなってしまう等の問題があった。
プラズマガスを生成する。そしてプラズマガス中に存在するラジカルまたはイオンが、リードフレーム110の表面に衝突することによりリードフレーム110表面の洗浄が行われる。
り回路装置を製造する。プラズマの照射には2つの方法があり、第1の方法は回路素子22の実装を行う前にプラズマ照射を行う方法であり、第2の方法は回路素子22の実装を行った後にプラズマ照射を行う方法である。以下に上記した各工程の詳細を説明する。
11 分離溝
12 ブロック
22A 半導体素子
22B チップ部品
25 金属細線
30 プラズマ洗浄機
31 上段電極
32 下段電極
40 ダイシングライン
41 ブレード
Claims (3)
- 表面から分離溝を形成することにより半導体素子を実装する凸状の導電パターンが設けられた導電箔からなる導電部材を備えた回路装置において、
前記導電箔に設けられた前記分離溝の側面は粗化された表面であり、該分離溝には前記半導体素子を含む前記導電箔を封止する封止樹脂が充填されており、前記導電箔の裏面側において該分離溝内の前記封止樹脂が前記導電パターンから突出しており、
前記導電箔の裏面側において、前記半導体素子と電気的に接続された外部電極を備えており、更に、レジストが、前記導電パターン及び前記導電パターンから突出した前記封止樹脂を被覆しているとともに、
前記レジストの表面は平坦であり、その表面は前記外部電極の頂部よりも低いことを特徴とする回路装置。 - 前記分離溝の断面は、上端部が内側にオーバーハングする湾曲形状であることを特徴とする請求項1に記載の回路装置。
- 前記導電パターンから突出した封止樹脂の表面は凹凸形状であることを特徴とする請求項1または2に記載の回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008223923A JP4832486B2 (ja) | 2008-09-01 | 2008-09-01 | 回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008223923A JP4832486B2 (ja) | 2008-09-01 | 2008-09-01 | 回路装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006194079A Division JP2006279085A (ja) | 2006-07-14 | 2006-07-14 | 回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009010416A JP2009010416A (ja) | 2009-01-15 |
JP4832486B2 true JP4832486B2 (ja) | 2011-12-07 |
Family
ID=40325111
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008223923A Expired - Fee Related JP4832486B2 (ja) | 2008-09-01 | 2008-09-01 | 回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4832486B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3706533B2 (ja) * | 2000-09-20 | 2005-10-12 | 三洋電機株式会社 | 半導体装置および半導体モジュール |
JP2002057173A (ja) * | 2000-08-09 | 2002-02-22 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP3561683B2 (ja) * | 2000-09-04 | 2004-09-02 | 三洋電機株式会社 | 回路装置の製造方法 |
-
2008
- 2008-09-01 JP JP2008223923A patent/JP4832486B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009010416A (ja) | 2009-01-15 |
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