CN1096116C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1096116C
CN1096116C CN97117718A CN97117718A CN1096116C CN 1096116 C CN1096116 C CN 1096116C CN 97117718 A CN97117718 A CN 97117718A CN 97117718 A CN97117718 A CN 97117718A CN 1096116 C CN1096116 C CN 1096116C
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layer
insulating barrier
solder joint
groove
semiconductor device
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CN97117718A
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CN1174409A (zh
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M·B·亚南度
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明揭示一种半导体器件及其制造方法，包括在焊点(21)上形成格子状，在钝化介质层(22)的下面配置蚀刻阻挡层，在钝化介质层(22)和蚀刻阻挡层中、在焊点(21)上设置开口部(23)，在格子状的焊点(21)之间充满绝缘层(27)，将焊接线与格子状的焊点(21)连接。

Description

半导体器件及其制造方法 
本发明涉及具有基于金属丝编织工艺(damassin process)或者双金属丝编织工艺(dual damassin process)的多层布线结构的半导体器件及其制造方法。
在超大规模集成电路(ULSI)中，通常采用在三层以上的层中形成布线层的多层布线结构。
图22和图23表示基于以往的布线工艺的半导体器件。图23表示沿图22中XXIII-XXIII线的剖视图。
在半导体基片11上形成场氧化层12。在由场氧化层12包围的元件区域中形成具有源、漏区域13和栅极14的MOS晶体管。
在半导体基片11上形成完全覆盖MOS晶体管的绝缘层15。在绝缘层15形成从其表面到源、漏区域13的接触孔16。在绝缘层15上形成具有多条布线17的第1层的布线层。将多条布线17的每一条，经由接触孔16，与MOS晶体管的源、漏区域13相连。
在绝缘层15上形成完全覆盖多条布线17的层间介质层(interlayerdielectric)18。在层间介质层18形成从其表面到多条布线17的接触孔19。在层间介质层18上形成具有多条布线20的第2层的布线层。将多条布线20的每一条，经由接触孔19，与第1层的布线层的布线17相连。
此外，在布线层18上形成焊点21。在层间介质层18上形成完全覆盖布线层20和焊点21的钝化介质层(Passivation dielectric)22。在钝化介质层22中、在焊点21上形成开口部23。
在基于以往的布线工艺的半导体器件中，分别利用光刻工序(PEP)，即形成光刻图形并将这种光刻图形做成掩模、用各向异性蚀刻(RIE等)蚀刻金属层的工序，形成第1层的布线层的多条布线17、第2层的布线层的多条布线20的焊点21。
但是，在ULSI中，同一层的布线间的间隔很窄。
因此，第一，很难正确地对各布线层的布线17、20生成图形。这是因为形成光刻图形的曝光装置的清晰度达不到微细的布线图形的状态。
第二，很难利用绝缘层充满同一层的布线间的凹槽，在其布线之间形成空腔。这是因为绝缘层的台阶敷层性能差。这种空腔对多层布线技术产生不好的影响。
图24和图25表示基于双金属丝编织工艺的半导体器件。图25表示沿图24中XXV-XXV线的剖视图。
在半导体基片11上形成场氧化层12。在由场氧化层12包围的元件区域中形成具有源、漏区域13和栅极14的MOS晶体管。
在半导体基片11上形成完全覆盖MOS晶体管的绝缘层15、24。在绝缘层15、24形成从其表面到源、漏区域13的接触孔16a。
在绝缘层24上形成绝缘层25。在绝缘层25形成用于形成第1层的布线层的多条凹槽16b。多条凹槽16b的底部到达接触孔16a。
在接触孔16a和凹槽16b的内表面上形成阻挡金属17a。在阻挡金属17a上形成完成充满接触孔16a和凹槽16b的金属(或者金属合金)。成为第1层的布线层的多条布线，由阻挡金属17a和17b构成。
绝缘层25和第1层的布线层表面处于同一平面，而且表面平整。成为第1层的布线层的多条布线分别与MOS晶体管的源、漏区域13相连。
在绝缘层25上和第1层的布线层上形成层间介质层(interlay dielectric)18和绝缘层26。在层间介质层18、26形成从其表面到第1层的布线层的接触孔19a。
在绝缘层26上形成绝缘层27。在绝缘层27形成用于形成第2层的布线层的多条凹槽19b。多条凹槽19b的底部到达接触孔19a。
在接触孔19a和凹槽19b的内表面上形成阻挡金属20a。在阻挡金属20a上形成完成充满接触孔19a和凹槽19b的金属(或者金属合金)20b。成为第2层的布线层的多条布线，由阻挡金属20a和金属20b构成。
绝缘层27和第2层的布线层的表面处于同一平面，而且表面平整。成为第2层的布线层的多条布线分别与第1层的布线层相连。
在将第2层的布线层做成最上层的场合，第2层的布线层的一部分构成焊点21。与第2层的布线层相同，焊点21由金属(或者金属合金)构成。
在绝缘层27上、第2层的布线层上和焊点21上形成绝缘层(passivationdielectric)22。在钝化介质层22中、在焊点21上形成开口部部部23。
在基于这种双金属丝编织工艺的半导体器件中，能解决以往的布线工艺曝光时的布线图形模糊的问题和布线间的空腔的问题。
但是，在双金属丝编织工艺和金属丝编织工艺中，使用CMP(化学机械研磨)技术。在使用这种CMP技术形成焊点21的场合，过多地蚀刻焊点21的中央部分，产生焊点21成为碟状的所谓凹曲(dishing)。
图26表示产生凹曲的样子。
也就是说，CMP除机械蚀刻金属层21′外，还化学蚀刻金属层21′。因此，在与深度相比具有充分大的宽度(通常焊点的大小为100μm×100μm左右)的凹槽19b中残留金属(焊点)21的场合，主要是由于化学蚀刻过多地蚀刻凹槽19b的中央部分的金属21。
这种凹曲，在焊线时，会引起导线在焊点21上不能正确连接的焊接不良，成为制造成品率低的原因。
图27和图28表示为了解决凹曲问题而发明的基于双金属丝编织工艺的半导体器件。图28表示沿图27中XXVIII-XXVIII线的剖视图。
在半导体基片11上形成场氧化层12。在由场氧化层12包围的元件区域中形成具有源、漏区域13和栅极14的MOS晶体管。
在半导体基片11上形成完全覆盖MOS晶体管的绝缘层15、24。在绝缘层15、24形成从其表面到源、漏区域13的接触孔16a。
在绝缘层24上形成绝缘层25。在绝缘层25形成用于形成第1层的布线层的多条凹槽16b。多条凹槽16b的底部到达接触孔16a。
在接触孔16a和凹槽16b的内表面上形成阻挡金属17a。在阻挡金属17a上形成完全充满接触孔16a和凹槽16b的金属(或者金属合金)17b。成为第1层的布线层的多条布线，由阻挡金属17a和金属17b构成。
绝缘层25和第1层的布线层的表面处于同一平面，而且表面平整。成为第1层的布线层的多条布线分别与MOS晶体管的源、漏区域13相连。
在绝缘层25上和第1层的布线层上形成绝缘层(interlay dielectric)18和绝缘层26。在层间介质层18、26形成从其表面到第1层的布线层的接触孔19a。
在绝缘层26上形成绝缘层27。在绝缘层27形成用于形成第2层的布线层的多条凹槽19b。多条凹槽19b的底部到达接触孔19a。
在接触孔19a和凹槽19b的内表面上形成阻挡金属20a。在阻挡金属20a上形成完成充满接触孔19a和凹槽19b的金属(或者金属合金)20b。成为第2层的布线层的多条布线，由阻挡金属20a和金属20b构成。
绝缘层27和第2层的布线层的表面处于同一平面，而且表面平整。成为第2层的布线层的多条布线分别与第1层的布线层相连。
在将第2层的布线层做成最上层的场合，第2层的布线层的一部分构成焊点21。与第2层的布线层相同，焊点21由金属(或者金属合金)构成。
但是，为了防止CMP时的凹曲，将焊点21形成格子状。也就是说，在焊点21设置行列状地配置的点状的多个孔。
在绝缘层27上和第2层的布线层上形成绝缘层(passivation dielectric)22。在钝化介质层22中、在焊点21上形成开口部部部23。
在基于这种双金属丝编织工艺的半导体器件中，将焊点21形成格子状。因此，在使用CMP形成焊点21的场合，在焊点21上不会产生过多地被蚀刻的部分，能有效地防止凹曲。
接着，对图27和图28的半导体器件的制造方法进行说明。
首先，如图29所示，利用LOCOS法，在硅基片11上形成场氧化层12。然后，在由场氧化层12包围的元件区域中形成具有源、漏区域13和栅极14的MOS晶体管。
用例如CVD法，在硅基片11上形成完全覆盖MOS晶体管的1μm左右的绝缘层(BPSG(borophospho silicate glass)等)15。通过CMP、磨平绝缘层15的表面。
接着，如图30所示，利用例如CVD法，在绝缘层15上连续形成蚀刻阻挡层24和绝缘层25。绝缘层25由例如氧化硅构成。在绝缘层25由氧化硅构成的场合，蚀刻阻挡层24由对于RIE(反应离子蚀刻)的氧化硅的蚀刻选择比大的材料、例如氮化硅构成。
设定蚀刻阻挡层24的厚度为50nm左右，形成的绝缘层25的厚度与构成第1层的布线层的布线厚度相同、例如0.6μm左右。
接着，如图31所示，在绝缘层25形成多条凹槽16b。利用光刻工序，即向绝缘层25上涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的绝缘层25的蚀刻以及光刻胶的剥离，形成这种多条凹槽16b。蚀刻阻挡层24起到作为这种RIE的蚀刻阻挡的功能。
此外，多条凹槽16b的图形与构成第1层的布线层的布线图形相同。
接着，如图32所示，在绝缘层15、24形成接触孔16a。接触孔16a也与多条凹槽16b的形成相同。由光刻工序形成。也就是说，利用向绝缘层25上和凹槽16b内涂敷光刻胶、该光刻胶生成图形、基于将该光胶加以掩模的RIE的绝缘层15、24的蚀刻以及光刻胶的剥离，形成接触孔16a。
接着，如图33所示，利用CVD法或者PVD法，在绝缘层25上、接触孔16a的内表面和凹槽16b的内表面上形成阻挡金属17a。阻挡金属17a由例如钛和氮化钛的层积或氮化钛硅等构成。
接着，如图34所示，利用CVD法或者PVD法，在阻挡金属17a上形成完全充满接触孔16a和凹槽16b的金属(或者金属合金)17′。金属17′由例如铝、铜或者它们的合金等构成。
在使用PVD法形成金属17′时，使用高温PVD法或包含完全充满接触孔16a和凹槽16b的温度处理的PVD法。
接着，如图35所示，利用CMP法，对存在于接触孔16a和凹槽16b的外部的阻挡金属17a和金属17b进行蚀刻，并仅在接触孔16a和凹槽16b内部保留有阻挡金属17a和金属17b。
由此，在形成第1层的布线层的同时，形成电气连接第1层的布线层和基片中的扩散层(源、漏区域)的接触点。
接着，如图36所示，用CVD法，在绝缘层25上和第1层的布线层上形成厚度约1μm的绝缘层(氧化硅等)18。此外，利用例如CVD法，在层间介质层18上连续形成蚀刻阻挡层26和绝缘层27。绝缘层27由例如氧化硅构成。在绝缘层27由氧化硅构成的场合，蚀刻阻挡层26由对于RIE(反应离子蚀刻)的氧化硅的蚀刻选择比大的材料、例如氮化硅构成。
设定蚀刻阻挡层26的厚度为50nm左右，形成的绝缘层27的厚度与构成第2层的布线层的布线厚度相同、例如0.6μm左右。
接着，如图37和图38所示，在绝缘层25形成多条凹槽19b、19b′。利用光刻工序，即向绝缘层27上涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩膜的RIE的绝缘层27的蚀刻以及光刻胶的剥离，形成这种多条凹槽19b、19b′。蚀刻阻挡层26起到作为这种RIE的蚀刻阻挡的功能。
此外，凹槽19b的图形与构成第2层的布线层的布线图形相同，槽19b′的图形与焊点(格子状)的图形相同(第2层的布线层为最上层的场合)。
在层间介质层18、26形成接触孔19a。与多条凹槽19b、19b′的形成相同，也利用光刻工序、形成接触孔19a、也就是说，利用向绝缘层27上和凹槽19b、19b′内涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的层间介质层18、26的蚀刻以及光刻胶的剥离，形成接触孔19a。
接着，如图39和图40所示，利用CVD法或者PVD法，在绝缘层27上、接触孔19a的内表面和凹槽19b，19b′的内表面上形成阻挡金属20a。阻挡金属20a由例如钛和氮化钛的层积或氮化钛硅等构成。
利用CVD法或者PVD法，在阻挡金属20a上形成完全充满接触孔19a和凹槽19b，19b′的金属(或者金属合金)20b，21。金属20b，21由例如铝、铜或者它们的合金等构成。
在使用PVD法形成金属20b，21时，使用高温PVD法或包含完全充满接触孔19a和凹槽19b，19b′的温度处理的PVD法。
然后，利用CMP法，对存在于接触孔19a和凹槽19b，19b′的外部的阻挡金属20a和金属20b，21进行蚀刻，并仅在接触孔19a和凹槽19b，19b′的内部保留有阻挡金属20a和金属20b，21。
由此，在形成第2层的布线层和格子状的焊点的同时，形成电气连接第1层的布线层和第2层的布线层的接触点。
接着，如图41所示，利用例如CVD法，在绝缘层27上、第2层的布线层上和焊点上形成钝化介质层22。这种钝化介质层22由氧化硅等构成。
接着，如图42和图43所示，在钝化介质层22上形成开口部部部23。这种开口部部部23位于格子状的焊点21上，并利用光刻工序形成。也就是说，利用向钝化介质层22上涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的钝化介质层22的蚀刻以及光刻胶的剥离，形成开口部部部23。
在用于形成这种开口部部部23的RIE中，通常也同时地蚀刻绝缘层27。这是因为钝化介质层22和绝缘层27由相同材料(例如氧化硅)构成的缘故。
前述双金属丝编织工艺或者金属丝编织工艺的半导体器件的特点在于作为布线的金属本体不生成图形而绝缘层生成图形。也就是说，因为不存在所谓的在布线之间充满绝缘层的工艺，所以在布线之间不会形成空腔。
在布线中使用低电阻的铜的场合，已知对铜的图形生成非常困难。在双金属丝编织工艺或者金属丝编织工艺中，因不进行铜的图形生成，而借助于在绝缘层的槽中埋入铜形成布线，所以能实现由铜构成的布线。
此外，在双金属丝编织工艺中，因能同时形成布线和接触点，所以有能降低制造费用的优点。
在前述双金属丝编织工艺中，用在焊点21上设置开口部部部23时的RIE，也同时蚀刻绝缘层27。这里因为如前所述、钝化介质层22和绝缘层27由相同材料(例如氧化硅)构成的缘故。
这种场合，如图44和图45所示，在进行焊线时，因导线28挤碎格子状的焊点21，所以会发生焊接不良。这时因为格子状的焊点21之间有空隙、焊点21容易产生变形的缘故。
本发明为解决前述缺点，其目的在于，在基于双金属丝编织工艺或者金属丝编织工艺的半导体器件中，将焊点做成格子状，同时能防止格子状的焊点的变形、不会造成焊接不良，能有助于可靠性和制造成品率的改善。
为达到前述目的，本发明的半导体器件，利用在表面平坦的绝缘层的凹槽内充满的导电体、构成焊点，
所述半导体器件包括在所述绝缘层上形成的在所述焊点上具有开口部的蚀刻阻挡层、和
在所述蚀刻阻挡层上形成的在所述焊点上具有开口部并由与所述绝缘层相同材料构成的钝化介质层。前述绝缘层的凹槽具有格子状，前述焊点也具有格子状。前述绝缘层和前述钝化介质层由氧化硅构成，前述蚀刻阻挡层由氮化硅构成。
本发明的半导体器件的制造方法包括下述工序：在表面平坦的绝缘层设置凹槽；借助于在前述凹槽充满导电体、形成焊点；在前述绝缘层上和前述焊点上，形成由至少对于构成前述绝缘层的材料、能有选择地进行蚀刻的材料构成的蚀刻阻挡层；在前述蚀刻阻挡层上，形成由至少对于构成前述蚀刻阻挡层的材料、能有选择地进行蚀刻的材料构成的钝化介质层；仅去除位于前述焊点上的前述钝化介质层；仅去除位于前述焊点上的前述蚀刻阻挡层。
在前述绝缘层上形成完全充满前述凹槽的导电体后，借助于利用CMP研磨前述导电体，形成前述焊点。利用RIE、蚀刻前述钝化介质层，利用RIE或者CDE、蚀刻前述蚀刻阻挡层。
借助于在前述凹槽内充满导电体，与形成前述焊点一起也同时形成最上层的布线层。
图1表示与本发明实施例相关的半导体器件的平面图。
图2表示沿图1中II-II线的剖视图。
图3表示与本发明实施例相关的制造方法的一工序的剖视图。
图4表示与本发明实施例相关的制造方法的一工序的剖视图。
图5表示与本发明实施例相关的制造方法的一工序的剖视图。
图6表示与本发明实施例相关的制造方法的一工序的剖视图。
图7表示与本发明实施例相关的制造方法的一工序的剖视图。
图8表示与本发明实施例相关的制造方法的一工序的剖视图。
图9表示与本发明实施例相关的制造方法的一工序的剖视图。
图10表示与本发明实施例相关的制造方法的一工序的剖视图。
图11表示与本发明实施例相关的制造方法的一工序的平面图。
图12表示沿图11中XII-XII线的剖视图。
图13表示与本发明实施例相关的制造方法的一工序的平面图。
图14表示沿图13中XIV-XIV线的剖视图。
图15表示与本发明实施例相关的制造方法的一工序的剖视图。
图16表示与本发明实施例相关的制造方法的一工序的平面图。
图17表示沿图16中XVII-XVII线的剖视图。
图18表示与本发明实施例相关的制造方法的工序的平面图。
图19表示沿图18中XIX-XIX线的剖视图。
图20表示在图1的半导体器件中进行了焊线的状态的平面图。
图21表示沿图20中XXI-XXI线的剖视图。
图22表示以往的半导体器件的平面图。
图23表示沿图22中XXIII-XXIII线的剖视图。
图24表示以往的半导体器件的平面图。
图25表示沿图24中XXV-XXV线的剖视图。
图26表示以往的金属丝编织工艺的凹曲现象。
图27表示以往的半导体器件的平面图。
图28表示沿图27中XXVIII-XXVIII线的剖视图。
图29表示以往的制造方法的一工序的剖视图。
图30表示以往的制造方法的一工序的剖视图。
图31表示以往的制造方法的一工序的剖视图。
图32表示以往的制造方法的一工序的剖视图。
图33表示以往的制造方法的一工序的剖视图。
图34表示以往的制造方法的一工序的剖视图。
图35表示以往的制造方法的一工序的剖视图。
图36表示以往的制造方法的一工序的剖视图。
图37表示以往的制造方法的一工序的平面图。
图38表示图37中沿XXXVIII-XXXVIII线的剖视图。
图39表示以往的制造方法的一工序的平面图。
图40表示沿图39中XL-XL线的剖视图。
图41表示以往的制造方法的一工序的剖视图。
图42表示以往的制造方法的一工序的平面图。
图43表示沿图42中XLIII-XLIII线的剖视图。
图44表示在图27的半导体器件中进行了焊线的状态的平面图。
图45表示沿图44中XLV-XLV线的剖视图。
下面，参照附图对本发明的半导体器件及其制造方法详细地进行说明。
实施例
图1和图2表示与本发明实施例相关的基于双金属丝编织工艺的半导体器件。图2表示沿图1中II-II线的剖视图。
在半导体基片11上形成场氧化层12。在由场氧化层12包围的元件区域中形成具有源、漏区域13和栅极14的MOS晶体管。
在半导体基片11上形成完全覆复MOS晶体管的绝缘层15、24。在绝缘层15、24形成从其表面到源、漏区域13的接触孔16a。
在绝缘层24上形成绝缘层25。在绝缘层25形成用于形成第1层的布线层的多条凹槽16b。多条凹槽16b的底部到达接触孔16a。
在接触孔16a和凹槽16b的内表面上形成阻挡金属17a。在阻挡金属17a上形成完全充满接触孔16a和凹槽16b的金属(或者金属合金)17b。成为第1层的布线层的多条布线，由阻挡金属17a和17b构成。
连接第1层的布线层和MOS晶体管的源、漏区域13的接触点，也由阻挡金属17a和金属17b构成。
绝缘层25和第1层的布线层的表面处于同一平面，而且表面平整。
在绝缘层25上和第1层的布线层上形成层间介质层(interlayer dieldctric)18和绝缘层26。在层间介质层18、26形成从其表面到第1层的布线层的接触孔17a。
在绝缘层26上形成绝缘层27。在绝缘层27形成用于第2层的布线层的多条凹槽19b。多条凹槽19b的底部到达接触孔19a。
在接触孔19a和槽19b的内表面上形成阻挡金属20a。在相当金属20a上形成完全充满接触孔19a和凹槽19b的金属(或者金属合金)20b。成为第2层的布线层的多条布线，由阻挡金属20a和金属20b构成。
连接第1层的布线层和第2层的布线层的接触点，也由阻挡金属20a和金属20b构成。绝缘层27与第2层的布线层的表面处于同一平面，而且表面平整。
在将第2层的布线层做成最上层的场合，第2层的布线层的一部分构成焊点21。与第2层的布线层相同，焊点21由金属(或者金属合金)构成。但是，为了防止CMP时的凹曲，将焊点21形成例如格子状。
在绝缘层27和第2层的布线层上形成蚀刻阻挡层29。在蚀刻阻挡层29上形成钝化介质层(passivation dielectric)22。
蚀刻阻挡层29由对于构成绝缘层27和钝化介质层22的材料、能有选择地进行蚀刻的材料构成。例如，在绝缘层27和钝化介质层22由氧化硅构成的场合中，蚀刻阻挡层29由氮化硅构成。用约50nm的厚度，形成蚀刻阻挡层29。
在焊点21上、在钝化介质层22和蚀刻阻挡层29上形成开口部部部23。
在这种基于双金属丝编织工艺的半导体器件中，形成格子状的焊点21。因此，在使用CMP技术形成焊点21的场合，在焊点21上不会产生过多的蚀刻的部分，能有效地防止凹曲。
在格子状的焊点21之间完全充满绝缘层27。因此，在焊线的导线压接时，焊点21不会挤碎或者变形。因此，能抑制焊接不良的发生，并能有助于提高可靠性和制造成品率。
在钝化介质层22的下面，配置由对于构成钝化介质层22和绝缘层27的材料、能有选择地进行蚀刻的材料构成的蚀刻阻挡层29。因此，在钝化介质层22设置开口部部部23时，不会蚀刻格子状的焊点21之间的绝缘层27。
接着，对图1和图2的半导体器件的制造方法进行说明。
首先，如图3所示，利用LOCOS法，在硅基片11上形成场氧化层12。然后，在由场氧化层12包围的元件区域中形成具有源、漏区域13和栅极14的MOS晶体管。
例如，用CVD法，在硅基片11上形成完全覆复MOS晶体管的1μm左右的绝缘层(BP SG(borophospho silicate glass)等)15。通过CMP、磨平绝缘层15的表面。
接着，如图4所示，利用例如CVD法，在绝缘层15上连续形成蚀刻阻挡层24和绝缘层25。绝缘层25由例如氧化硅构成。在绝缘层25由氧化硅构成的场合，蚀刻阻挡层24由对于RIE(反应离子蚀刻)的氧化硅的蚀刻选择比大的材料、例如氮化硅构成。
设定蚀刻阻挡层24的厚度为50nm左右，形成的绝缘层25的厚度与构成第1层的布线层的布线厚度相同、例如0.6μm左右。
接着，如图5所示，在绝缘层25形成多条凹槽16b。利用光刻工序，即向绝缘层25上涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的绝缘层25的蚀刻以及光刻胶的剥离，形成这种多条凹槽16b。蚀刻阻挡层24起到作为这种RIE的蚀刻阻挡的功能。
此外，多条凹槽16b的图形与构成第1层的布线层的布线图形相同。
接着，如图6所示，在绝缘层15、24形成接触孔16a。接触孔16a也与多条凹槽16b的形成相同、由光刻工序形成。也就是说，利用向绝缘层25上和凹槽16b的涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的绝缘层15、24的蚀刻以及光刻胶的剥离，形成接触孔16a。
接着，如图7所示，利用CVD法或者PVD法，在绝缘层25上、接触孔16a的内表面和凹槽16b的内表面上形成阻挡金属17a。阻挡金属17a由例如钛和氮化钛的层积或氮化钛硅等构成。
接着，如图8所示，利用CVD法或者PVD法，在阻挡金属17a上形成完全充满接触孔16a和凹槽16b的金属(或者金属合金)17′。金属17′由例如铝、铜或者它们的合金等构成。
在使用PVD法形成金属17′时，使用高温PVD法或包含完全充满接触孔16a和槽16b的温度处理的PVD法。
接着，如图9所示，利用CMP法，对存储在于接触孔16a和凹槽16b的外部的阻挡金属17a和金属17b进行蚀刻，并仅在接触孔16a和槽16b内部保留有阻挡金属17a和金属17b。
由此，在形成第1层的布线层的同时，形成电气连接第1层的布线层和基片中的扩散层(源、漏区域)的接触点。
接着，如图10所示，用CVD法，在绝缘层25上和第1层的布线层上形成厚度约1μm的绝缘层(氧化硅等)18。此外，利用例如CVD法，在层间介质层18上连续形成蚀刻阻挡层26和绝缘层27。绝缘层27由例如氧化硅构成。在绝缘层27由氧化硅构成的场合，蚀刻阻挡层26由对于RIE(反应离子蚀刻)的氧化硅的蚀刻选择比大的材料、例如氮化硅构成。
设定蚀刻阻挡层26的厚度为50nm左右，形成的绝缘层27的厚度与构成第2层的布线层的布线厚度相同。
接着，如图11和图12所示，在绝缘层25上形成多条凹槽19b，19b′。利用光刻工序，即向绝缘层27上涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的绝缘层27的蚀刻以及光刻胶的剥离，形成这种多条凹槽19b、19b′。蚀刻阻挡层26起到作为这种RIE的蚀刻阻挡的功能。
此外，凹槽19b的图形与构成第2层的布线层的布线图形相同，凹槽19b′的图形与焊点(格子状)的图形相同(第2层的布线层为最上层的场合)。
接着，如图13和图14所示，在层间介质层18、26形成接触孔19a。与多条凹槽19b、19b′的形成相同，也利用光刻工序、形成接触孔19a。也就是说，利用绝缘层27上及凹槽19b、19b′内涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的层间介质层18、26的蚀刻以及光刻胶的剥离，形成接触孔19a。
然后，利用CVD法或者PVD法，在绝缘层27上、接触孔19a的内表面和凹槽19b、19b′的内表面上形成阻挡金属20a。阻挡金属20a由例如钛和氮化钛的层积或氮化钛硅等构成。
利用CVD法或者PVD法，在阻挡金属20a上形成完全充满接触孔19a和凹槽19b，19b′的金属(或者金属合金)20b，21。金属20b，21由例如铝、铜或者它们的合金等构成。
在使用PVD法形成金属20b，21时，使用高温PVD法或包含完全充满接触孔19a和槽19b，19b′的温度处理的PVD法。
然后，利用CMP法，对存在于接触孔19a和凹槽19b，19b′的外部的阻挡金属20a和金属20b，21进行蚀刻，并仅在接触孔19a和凹槽19b，19b′的内部保留有阻挡金属20a和金属20b，21。
由此，在形成第2层的布线层和格子状的焊点的同时，形成电气连接第1层的布线层和第2层的布线层的接触点。
接着，如图15所示，利用例如CVD法，在绝缘层27上、第2层的布线层上和焊点上连续形成蚀刻阻挡层29和钝化介质层22。
钝化介质层22由例如氧化硅构成。在钝化介质层22由氧化硅构成的场合，蚀刻阻挡层29由对于RIW(反应离子蚀刻)的氧化硅的蚀刻选择比大的材料、例如氮化硅构成。设定蚀刻阻挡层29的厚度为50nm左右。
接着，如图16和图17所示，在钝化介质层22形成开口部部部23。这种开口部部部23位于格子状的焊点21上，并利用光刻工序形成。也就是说，利用向钝化介质层22上涂敷光刻胶、该光刻胶生成图形、基于将该光刻胶加以掩模的RIE的钝化介质层22的蚀刻以及光刻胶的剥离，形成开口部部部23。
在用于形成这种开口部部部23的RIE中，因为蚀刻阻挡层29存在，所以绝缘层27不会被蚀刻。
接着，如图18和图19所示，仅去除存在于钝化介质层22的开口部部部23的底部的蚀刻阻挡层29。蚀刻阻挡层29的去除，除能利用RIE等的各向异性蚀刻进行外，也能利用CDE(化学干法蚀刻)等的各向同性蚀刻进行。
利用前述工序，完成前述的图1和图2的半导体器件。
前述制造方法的特点是在钝化介质层22的下面设置蚀刻阻挡层29。因此，在用于在焊点21上设置开口部部部23的RIE中，也不会蚀刻格子状的焊点21之间的绝缘层27。
也就是说，如20和图21所示，是在格子状的焊点21之间充满绝缘层27的状态，然后，即使进行焊线，导线28也不会挤碎格子状的焊点21或者使其变形。
因此不会发生焊接不良，能有助于可靠性和制造成品率的改善。
如前所述，采用本发明的半导体器件及其制造方法，则能达到以下的效果。
在钝化介质层的下面设置蚀刻阻挡层。因此，在焊点上设置开口部部部时的RIE，不会蚀刻格子状的焊点之间的绝缘层。也就是说，在格子状的焊点之间充满绝缘层。因此，即使然后进行焊线，也因导线不会挤碎格子状的焊点或者使其变形，所以不会发生焊接不良，能有助于可靠性和制造成品率的改善。

Claims (7)

1.一种半导体器件，利用在表面平坦的绝缘层的凹槽内充满的导电体、构成焊点，其特征在于，
所述半导体器件包括在所述绝缘层上形成的在所述焊点上具有开口部的蚀刻阻挡层、和
在所述蚀刻阻挡层上形成的在所述焊点上具有开口部并由与所述绝缘层相同材料构成的钝化介质层。
2.如权利要求1所述的半导体器件，其特征在于，所述绝缘层的凹槽具有格子状，所述焊点也具有格子状。
3.如权利要求1所述的半导体器件，其特征在于，所述绝缘层和所述钝化介质层由氧化硅构成，所述蚀刻阻挡层由氮化硅构成。
4.一种半导体器件的制造方法，所述半导体器件在表面平坦的绝缘层上设置凹槽，借助于在所述凹槽内充满导电体、形成焊点，其特征在于，所述半导体器件的制造方法包括下述工序：
在所述绝缘层上和所述焊点上，形成由至少对于构成所述绝缘层的材料、能有选择地进行蚀刻的材料构成的蚀刻阻挡层的工序；在所述蚀刻阻挡层上，形成由至少对于构成所述蚀刻阻挡层的材料、能有选择地进行蚀刻的材料构成的钝化介质层的工序；仅去除位于所述焊点上的所述钝化介质层的工序；仅去除位于所述焊点上的所述蚀刻阻挡层的工序。
5.如权利要求4所述的半导体器件的制造方法，其特征在于，利用在所述绝缘层上形成完全充满所述凹槽的导电体的工序和利用CMP研磨所述导电体的工序，形成所述焊点。
6.如权利要求4所述的半导体器件的制造方法，其特征在于，基于RIE蚀刻所述钝化介质层，基于RIE或者CDE蚀刻的所述蚀刻阻挡层。
7.如权利要求4所述的半导体器件的制造方法，其特征在于，借助于在所述凹槽内充满导电体，形成所述焊点，同时形成最上层的布线层。
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