CN1893078A - 电子基板、电子基板的制造方法、及电子设备 - Google Patents
电子基板、电子基板的制造方法、及电子设备 Download PDFInfo
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- CN1893078A CN1893078A CNA2006101011456A CN200610101145A CN1893078A CN 1893078 A CN1893078 A CN 1893078A CN A2006101011456 A CNA2006101011456 A CN A2006101011456A CN 200610101145 A CN200610101145 A CN 200610101145A CN 1893078 A CN1893078 A CN 1893078A
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- 239000000758 substrate Substances 0.000 title claims abstract description 146
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 34
- 238000003475 lamination Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 description 63
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 40
- 239000010703 silicon Substances 0.000 description 40
- 229910052710 silicon Inorganic materials 0.000 description 40
- 239000010410 layer Substances 0.000 description 31
- 239000010949 copper Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 9
- 230000001815 facial effect Effects 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000011651 chromium Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- BCMCBBGGLRIHSE-UHFFFAOYSA-N 1,3-benzoxazole Chemical compound C1=CC=C2OC=NC2=C1 BCMCBBGGLRIHSE-UHFFFAOYSA-N 0.000 description 1
- 208000019901 Anxiety disease Diseases 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000036506 anxiety Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
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- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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Abstract
一种电子基板,包括基板,该基板具有:第一面,其形成有有源区域;第二面,其上形成无源元件,且处于与所述第一面相反侧。
Description
技术领域
本发明涉及电子基板、电子基板的制造方法、及电子设备。
背景技术
近年,半导体装置伴随电子设备的小型化及高功能化,追求组件自身的小型化或高密度化。
因此,特开2002-164468号公报及特开2003-347410号公报中公开有如下技术:通过在基板的有源面(主面)上形成电感器元件,实现作为半导体装置(电子基板)的小型化及高功能化。
然而,在如上述的现有技术中,存在如以下的问题。
由于电感器元件等无源元件配置在有源元件的附近,因此产生如下问题:存在引起与有源元件的电耦合,导致有源元件的特性、或使用了该基板的半导体装置整体的特性变差之虞。
例如,在上述的技术中,产生了如下问题:因从电感器元件泄漏的电流而导致晶体管等的特性发生变化。
发明内容
本发明考虑如上述的方面而实现,目的在于提供即使基板上设置无源元件时也能够抑制有源元件的特性的恶化的电子基板与其制造方法、及具有该电子基板的电子设备。
为了达到上述的目的,本发明采用了以下的结构。
本发明的电子基板,包括基板,该基板具有:第一面,其形成有有源区域;第二面,其上形成有无源元件,且处于与所述第一面相反侧。
因此,在本发明的电子基板中,形成在第一面的有源区域的有源元件(布线形成在基板上的元件、或作为芯片部件搭载的元件)与夹着基板形成在第二面上的无源元件的间隔距离增大。
由此,在无源元件与有源元件之间不易引起电耦合。
因此,在本发明中,可抑制有源元件的特性或安装有该电子基板的系统整体的特性恶化。
在本发明的电子基板中,优选包含:贯通导电部,其贯通所述基板;电极,其形成在所述第一面上,所述无源元件,经由所述贯通导电部与所述电极电连接。
由此,在本发明中,经由形成在第一面上的电极,可容易地确保其他的元件与无源元件的电连接。
在本发明的电子基板中,优选包含配置在所述第二面上或所述第二面的上方的布线图案,所述无源元件由所述布线图案的一部分构成。
作为无源元件,可适宜地采用如下结构:使用配置在所述第二面上或所述第二面的上方的布线图案形成或连接的结构。
该情况下,可获得实现了薄型化的电子基板。
在本发明的电子基板中,优选所述布线图案由多个层叠层而形成。
使用布线图案形成无源元件时,无源元件可适宜地采用如下结构:使用叠层为多层的布线图案形成或连接的结构。
在该结构中,例如通过夹住电介质层(绝缘层)的布线图案,可容易地形成电容器等。
再有,不是由布线图案形成无源元件的结构,而是将具有无源元件的功能的芯片部件搭载于第二面的结构。
在本发明的电子基板中,优选包含外部连接端子,所述布线图案的至少一部分构成所述外部连接端子。
该情况下,可构成为,在所述外部连接端子的表面安装电子部件。
另外,还可适宜地构成为,该电子部件中包含所述无源元件。
在该结构中,可容易地实现其他的电子部件与无源元件、或有源元件的电连接。
在本发明的电子基板中,优选多个所述基板经由所述外部连接端子相互连接而叠层。
该情况下,可容易地形成具有叠层了多个基板的多层基板的组件。
在本发明的电子基板中,优选在所述第二面上设置应力缓冲层,所述无源元件的至少一部分形成在所述应力缓冲层上。
在该结构中,即使向第二面施加热应力,也可抑制无源元件的可靠性或寿命的降低。
另外,应力缓冲层作为绝缘层时,由于更加不易引起无源元件与有源元件的电耦合,所以可防止无源元件的特性等的恶化,获得可降低来自无源元件的寄生电容等效果。
在本发明的电子基板中,优选在所述第二面上形成有接地电极膜。
在该结构中,可获得有源元件等形成在第一面上的元件与无源元件之间的电磁屏蔽效果。
在本发明的电子基板中,优选所述接地电极膜形成在对应于形成在所述第一面上的有源区域的配置的位置。
由此,在本发明中,可获得对有源元件有效的电磁屏蔽效果,并且,可采用有效的噪音对策。
在本发明的电子基板中,优选所述接地电极膜基于配设在所述第二面上或所述第二面的上方的元件的阻抗而形成。
由此,在本发明中,通过调整接地电极膜的厚度或大小等形成接地电极膜的条件,可控制配设在第二面上或第二面的上方的元件的阻抗。
在本发明的电子基板中,优选所述第二面上具有至少保护所述无源元件的保护膜。
由此,在本发明中,可保护无源元件,防止腐蚀或短路。
在本发明的电子基板中,优选在所述有源区域形成有半导体元件。
该情况下,作为半导体元件,可采用通过形成在有源区域的布线图案而形成晶体管等开关元件的结构、或将内置半导体元件的半导体器件安装在有源区域的结构。
在本发明的电子基板中,优选在所述基板上,没有搭载半导体元件。
在本发明的电子基板中,优选在所述第一面上设置第二无源元件。
在本发明的电子基板中,优选所述第二无源元件由配置在所述第一面上或所述第一面的上方的布线图案的一部分构成。
在本发明的电子基板中,优选所述第二无源元件设于安装在所述第一面上或所述第一面的上方的器件上。
在本发明的电子设备中,安装有所述的电子基板。
因此,在本发明中,可抑制有源元件的特性或安装有该电子基板的系统整体的特性恶化,且可获得高质量的电子设备。
附图说明
图1是表示本发明的第一实施方式的图,是表示半导体装置的剖面图。
图2是图1的半导体装置的A向视图。
图3A~图3C是表示第一实施方式中的半导体装置的制造方法的剖面图。
图4A~图4C是表示第一实施方式中的半导体装置的制造方法的剖面图。
图5A~图5C是表示第一实施方式中的半导体装置的制造方法的剖面图。
图6是表示第一实施方式中的半导体装置的制造方法的立体图。
图7是表示第二实施方式中的半导体装置的剖面图。
图8是表示第三实施方式中的半导体装置的剖面图。
图9是表示搭载有本发明的电子基板的电子设备的立体图。
图10是表示另一实施方式的电子基板的一例的剖面图。
具体实施方式
以下,参照图1~图9对本发明的电子基板与其制造方法及电子设备的实施方式进行说明。
在此,采用如下例子进行说明:在基板的有源区域设置半导体元件,另外,作为无源元件,采用布线图案形成电容器及线圈(电感器)时的例子。
(第一实施方式)
图1是硅基板上形成有半导体元件的半导体装置(电子基板)1的剖面图。
该半导体装置1,如图1所示,具备:硅基板(基板)10;连接部20,其形成在硅基板10的第一面10a上;布线部41,其形成在硅基板10的第二面10b上。
连接部20电连接在印刷布线板等外部设备P上。
布线部41具有安装用的连接面(land)。
在硅基板10的第一面10a的规定区域(有源区域),形成有具有例如晶体管、存储元件的集成电路等半导体元件。
在硅基板10上,形成有在厚度方向上贯通的槽11。
在槽11的内部形成有填充了导电性材料的导电部(贯通导电部)12。
在槽11的侧壁设有绝缘膜13,导电部12与硅基板10电绝缘。
另外,在硅基板10的第二面10b的表面上,在形成有槽11的区域以外的区域形成有背面绝缘层14。
连接部20具备:衬底层(钝化)21;第一电极22及第二电极23;第一绝缘层24;布线部30。
衬底层21形成在硅基板10的第一面10a上。
第一电极22及第二电极23分别形成在衬底层21上的多个规定区域。
第一绝缘层24形成在形成有电极22、23的区域以外的区域。
布线部30形成在第一绝缘层24上。
衬底层21例如由氧化硅(SiO2)、氮化硅(Si3N4)等绝缘性材料形成。
另外,作为第一电极22及第二电极23的材料,可枚举钛(Ti)、氮化钛(TiN)、铝(Al)、铜(Cu)、或者含有这些的合金等。
再有,在硅基板10上,如图2的俯视图所示,也可形成有多个电极。
在本实施方式中,只对第一电极22及第二电极23进行说明。
第二电极23也可被覆在第一绝缘层24上。
第一电极22及第二电极23,电连接在上述的集成电路等半导体元件上。
布线部30,如图1及图2所示,具备:第一布线31;金属膜32;第二绝缘层(应力缓冲层)33;第二布线34;第三绝缘层35。
第一布线31与形成在第一绝缘层24上的第一电极22电连接。
金属膜32形成在第二电极23的表面。
第二绝缘层33形成在第一布线31及金属膜32上。
第二布线34形成在第二绝缘层33上,且与第一布线31电连接。
第三绝缘层35形成在第二布线34上。
另外,第一布线31的一部分,通过从第二绝缘层33露出,形成连接面部36。
连接面部36与第二布线34电连接。
第二布线34上形成有凸起37。
半导体装置1通过凸起37电连接在印刷布线板等外部设备P上。
第三绝缘层35形成为被覆第二绝缘层33上,另外,形成为被覆第二布线34上的形成凸起37的区域以外的区域。
第一电极22通过第一布线31及第二布线34与凸起37电连接。
第二电极23形成于硅基板10的第一面10a上形成的衬底层21上。
第二电极23,一部分(背面侧)露出在槽11。
由此,第二电极23,在第二电极23的背面23a,与槽11的内部的导电部12的第一端部12a电连接。
导电部12的第二端部12b,与形成在硅基板10的第二面10b上的布线42电连接。
即,第二电极23,可与设在硅基板10的第二面10b上的电子元件电连接。
作为第一布线31及第二布线34的材料,金(Au)、铜(Cu)、银(Ag)、钛(Ti)、钨(W)、钛钨(TiW)、氮化钛(TiN)、镍(Ni)、镍钒(NiV)、铬(Cr)、铝(Al)、钯(Pd)等。
作为第一布线31及第二布线34,即可为上述的材料的单层构造,也可多个组合形成叠层构造。
另外,第一绝缘层24、第二绝缘层33、第三绝缘层35,由树脂(合成树脂)形成。
作为用于形成第一绝缘层24、第二绝缘层33、第三绝缘层35的形成材料,可为聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、丙烯酸树脂、酚醛树脂、BCB(苯并环丁烯(benzocyclobutene))及PBO(聚苯并唑(benzoxazole))等,具有绝缘性的材料。
再有,第一绝缘层24,也可由氧化硅(SiO2)、氮化硅(Si3N4)等绝缘性材料形成。
另外,金属膜32的材料,优选为与第一布线31及第二布线34相同的材料。
作为金属膜32的材料,可使用Au、TiW、Cu、Cr、Ni、Ti、W、NiV、Al等金属。
另外,金属膜32也可叠层这些金属而形成。
再有,金属膜(叠层构造的情况,至少1层)32,优选使用耐腐蚀性比电极高的材料,例如Au、TiW、Cr而形成。
由此,可阻止电极的腐蚀,防止电连接不良的发生。
布线部41具备:衬底层(背面绝缘层、钝化)14;布线(布线图案)43;绝缘层44;布线42、45;布线46;覆盖布线(布线图案)42、45、46及衬底层14的一部分而形成的绝缘层47。
衬底层14形成在硅基板10的第二面10b上。
布线43形成在衬底层14上。
绝缘层44在衬底层14上覆盖布线43而形成。
布线42、45跨过衬底层14上及绝缘层44上而形成在其上。
布线46形成在绝缘层44上。
绝缘层47覆盖布线42、45、46及衬底层14的一部分而形成。
布线42的第一端部形成在衬底层14上,与导电部12的第二端部12b电连接。
布线42的第二端部配置在绝缘层44上。
布线42的一部分在绝缘层44上从绝缘层47的开口部露出。
由此,形成从绝缘层47的开口部露出的连接面部(外部连接端子)48。
布线45的端部形成在绝缘层44上,与布线43对向地配置。
即,布线45与布线43,夹持绝缘层44而对向,构成叠层的电容器(无源元件)C。
该情况下,作为绝缘层44由电介质形成。
绝缘层44、47及衬底层14,与上述第一绝缘层24、第二绝缘层33、第三绝缘层35相同,由作为电介质的聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、丙烯酸树脂、酚醛树脂、BCB(苯并环丁烯)及PBO(聚苯并唑)等绝缘性树脂形成。
布线45的一部分在绝缘层44上从绝缘层47的开口部露出。
由此,形成从绝缘层47的开口部露出的连接面部(外部连接端子)49。
布线46,构成例如形成为螺旋形状的螺旋(spiral)形电感器(无源元件)L。
再有,在图1中,简单化图示电感器L。
这些电容器C及电感器L,通过未图示的贯通导电部连接在形成于第一面10a上的第一电极22及半导体元件上。
上述的布线42、43、45、46,与第一布线31及第二布线34相同,由金(Au)、铜(Cu)、银(Ag)、钛(Ti)、钨(W)、钛钨(TiW)、氮化钛(TiN)、镍(Ni)、镍钒(NiV)、铬(Cr)、铝(Al)、钯(Pd)等单层材料、或多个组合这些的叠层构造的材料形成。
下面,参照图3A~图6对半导体装置1的制造方法进行说明。
在本实施方式中,如图6所示,在同样的硅基板(基板)100上,同时一并形成多个半导体装置1。
在图3A~图5C所示的以下的说明中,表示形成1个半导体装置1的情况。
首先,如图3A所示,在硅基板10的第一面10a上形成衬底层21后,在衬底层21上形成第一电极22及第二电极23。
之后,在第一电极22及第二电极23上形成第一绝缘层24,通过周知的光蚀刻法(photolithography)及蚀刻法(etching),除去覆盖第一电极22及第二电极23的绝缘材料。
再有,也可不必除去覆盖第二电极23的绝缘材料。
然后,在包含第一电极22的第一绝缘层24上形成第一布线31,在第二电极23的表面形成金属膜32。
作为第一布线31的形成方法,例如采用通过溅射法(spatter)按TiW、Cu的顺序形成后,由镀敷法形成Cu的方法。
然后,形成第二绝缘层33,以覆盖第一布线31及金属膜32,通过周知的光蚀刻法,除去第二绝缘层33的对应于连接面部36的区域,第一布线31的一部分露出成为连接面部36。
然后,在第二绝缘层33上形成第二布线34,以与连接面部36连接。
之后,形成第三绝缘层35,以覆盖第二绝缘层33上及第二布线34上的形成凸起部37区域以外的区域。
然后,如图3B所示,在硅基板10的第二面10b上涂布光致抗蚀剂(photoresist)40,对光致抗蚀剂40进行图案形成。
将形成图案后的光致抗蚀剂40使用作掩模,实施干式蚀刻,除去对应于第二电极23的位置的硅基板10及衬底层21。
由此,如图3C所示,进行蚀刻直至第二电极23的背面23a露出,从硅基板10的第二面10b朝向第一面10a形成被蚀刻的槽11。
再有,采用了将光致抗蚀剂40使用作掩模的结构,但并不限定于此,例如,作为硬掩模可使用SiO2膜,也可并用光致抗蚀剂掩模及硬掩模。
另外,作为蚀刻方法,并不限定于干式蚀刻,也可采用湿式蚀刻、激光加工,或者并用这些。
然后,如图4A所示,在硅基板10的第二面10b及槽11的内壁上形成背面绝缘层(衬底层)14及绝缘膜13。
背面绝缘层14及绝缘膜13,为了防止发生漏电、氧及水分等引起半导体基板10的浸蚀等而形成。
作为背面绝缘层14及绝缘膜13的材料,可使用:使用PECVD(PlasmaEnhanced Chemical Vapor Deposition:等离子增强化学汽相沉积)形成的正硅酸四乙酯(Tetra Ethyl Ortho Silicate:Si(OC2H5)4:以下,称为TEOS),即PE-TEOS;使用臭氧CVD形成的TEOS,即O3-TEOS;或使用CVD形成的氧化硅(SiO2)。
再有,背面绝缘层14及绝缘膜13,只要具有绝缘性,可为其他的物质,也可为树脂。
通过干式蚀刻或激光加工除去形成在第二电极23的背面23a部分的绝缘膜13,由此如图4B所示,只在槽11的侧壁形成绝缘层13。
然后,如图4C所示,采用电化学镀(ECP)法,对槽11的内部实施镀敷处理,在槽11的内侧配置用于形成导电部12的导电性材料。
导电部12的第一端部12a与在槽11的内部露出的第二电极23,在第二电极23的背面23a电连接。
作为用于形成导电部12的导电性材料,例如可使用铜(Cu),通过在槽11中埋入铜(Cu),形成导电部12。
在本实施方式中的形成导电部12的工序中,例如包括由溅射法形成(叠层)TiN、Cu的工序、和由镀敷法形成Cu的工序。
再有,也可包括由溅射法形成(叠层)TiW、Cu的工序、和由镀敷法形成Cu的工序。
再有,作为导电部12的形成方法,并不限定于上述的方法,也可将导电膏、熔融金属、金属丝等埋入槽11中。
另外,在本实施方式中,将槽11的内部由导电部12填埋,但即使不完全填埋,也可以沿槽11的内壁形成导电部12,导电部12在第二电极23的背面23a电连接。
然后,形成导电部12后,在硅基板10的第二面10b上对布线43进行成膜。
作为布线43的成膜方法,可采用溅射法、镀敷法、液滴吐出方式等。
对布线43成膜之后,覆盖布线43,且在导通部12以外的区域形成绝缘层44。
作为绝缘层44的形成方法,与上述的绝缘层24、33、35相同。
然后,如图5A所示,在绝缘层44上形成布线46,并且,形成跨过衬底层14及绝缘层44的布线42、45。
作为布线42、45的形成方法,与布线43相同,可采用溅射法、镀敷法、液滴吐出方式等。
若形成布线42、45、46,则如图5B所示,形成绝缘层47,以覆盖布线42、45、46及衬底层14的一部分。
之后,通过光蚀刻法及蚀刻法,如图5C所示,除去覆盖布线42、45且对应于连接面部48、49的绝缘材料,由此形成连接面部48、49。
然后,在形成于硅基板10的第一面10a上的第二布线34上,搭载例如由无铅焊料构成的凸起37。
再有,设置凸起37时,即可将焊料球搭载在第二布线34上,也可采用将焊料膏印刷在第二布线34上的方式。
通过以上的工序,如图6所示,在硅基板100上,同时一并形成多个半导体装置。
之后,如图6所示,通过切割装置110,切割(切断)硅基板100,使多个半导体装置1分别被单片化。
于是,在硅基板100上大约同时形成多个半导体装置1,之后,切断硅基板100,通过使半导体装置1单片化,可获得图1所示的半导体装置1。
于是,可高效率地制造半导体装置1,且可实现半导体装置1的低成本化。
如以上所说明,在本实施方式中,作为无源元件的电容器C或电感器L形成在第二面10b上,在与第二面10b相反的第一面10a的有源区域形成半导体元件等有源元件。
因此,可夹持硅基板10自身,增大有源元件与无源元件的隔离距离。
因此,在本实施方式中,不易引起有源元件与无源元件的电耦合,从而可抑制有源元件的特性的恶化。
因此,在本实施方式中,由于可抑制装备了半导体装置1的系统(电光学装置或电子设备)整体的特性恶化,因此可形成超高密度的组件。
尤其,在本实施方式中,由于在有源区域设有半导体元件,因此将p型或n型半导体阱层夹持在中间,从而更加不易引起有源元件与无源元件的电耦合。
另外,在本实施方式中,在还起到应力缓冲层的作用的绝缘层44上,配置有构成无源元件的一部分的布线45、46,因此,也不易引起半导体元件的背侧与无源元件的电耦合。
因此,还可抑制无源元件的特性降低,并且,还可抑制从无源元件产生寄生电容。
另外,在本实施方式中,由于配设有连接面部48、49,所以可容易地使半导体装置1与其他的电子部件连接。
(第二实施方式)
继而,参照图7对半导体装置(电子基板)的第二实施方式进行说明。
在该图中,对于图1~图6所示的与第一实施方式的构成要素相同的要素赋予同一符号,从而省略其说明。
第二实施方式为接地电极膜G被成膜的结构。
如图7所示,在本实施方式中,在衬底层14上进行了接地电极膜G的成膜。
接地电极膜G,通过连接于未图示的地线而接地,与布线43相同,采用同一工序、同一材料,且形成在与布线43隔开的区域。
更加详细为,接地电极膜G,配置在与第一面10a的有源区域的相反的位置、或被有源区域与无源元件夹持的位置。
在本实施方式的半导体装置1中,由于接地电极膜G起到电磁屏蔽的作用,所以可抑制无源元件相对有源元件的噪音、或有源元件反之相对无源元件的噪音。
另外,在本实施方式中,通过调整接地电极膜G的厚度或大小等形成接地电极膜G的条件,还可控制连接到连接面部48、49的电子部件(电子元件)的阻抗。
(第三实施方式)
下面,参照图8对半导体装置(电子基板)的第三实施方式进行说明。
在图8所示的半导体装置1中,在厚度方向上叠层有多个具有凸起110的半导体元件111。
凸起110连接在图1所示的连接面部48、49上。
这种半导体装置1,构成了叠层型半导体装置。
该情况下,作为半导体元件111,与第一实施方式相同,即可为具备有源元件及无源元件双方的结构,也可为只具备无源元件的结构。
在上述的结构的半导体装置1中,可进一步提高安装密度。
另外,在本实施方式中,通过叠层功能不同的半导体装置,还可构筑一个系统组件(system block)。
(电子设备)
图9是表示搭载了上述的半导体装置1的电子设备的一例的图,是表示移动电话300的图。
由于搭载了实现了小型化·薄型化及高功能化的本发明的电子部件,因此可实现高品质且小型的移动电话300。
另外,作为安装半导体装置1的电子设备,除了移动电话之外,还可使用作装备了液晶显示装置、或有机电致发光显示装置、等离子体型显示装置等电光学装置的电子设备。
以上,参照附图对本发明的适宜的实施方式进行了说明,但本发明并不限定于所述例子。
上述的例子所示的各构成构件的各形状或组合等只是一例,在不脱离本发明的宗旨的范围内,可基于设计要求等进行各种变更。
例如,在上述实施方式中,采用电子基板内置半导体元件的半导体装置的例子进行了说明,但作为本发明的电子基板,不需要必须内置半导体元件。
也可构成为,在有源区域安装半导体器件等外部器件。
另一方面,作为本发明的电子基板,不需要必须设有半导体元件。
例如,还包括在搭载半导体晶片等外部器件的区域(有源区域),未搭载外部器件(非搭载状态),在与搭载区域相反侧的面上形成有无源元件的硅基板。
另外,在上述实施方式中,设为在硅基板10中内置半导体元件等有源元件、电容器C或电感器L的结构,但并不限定于此。
也可构成为,在有源区域安装半导体晶片等有源元件,在与有源区域相反侧的面上安装具有电容器或电感器等功能的无源元件。
例如,如图10所示,可构成为,具有上述的无源元件的电子部件51的连接垫52、53连接在硅基板10的连接面部48、49的表面而安装。
在该结构中,也可获得与上述的实施方式相同的作用·效果。
此外,也可构成为,在图1所示的内置无源元件的硅基板10的连接面部48、49的表面,安装不具有无源元件的电子部件(半导体器件等)。
另外,在上述实施方式中,设为在硅基板10的第一面10a上设置半导体元件的结构进行了说明,但只要不与凸起37或第二布线34等干涉,也可设置其他的电子元件。
作为该情况下的电子元件,可选择半导体器件或上述的无源元件。
将无源元件作为第二无源元件设在第一面10a上时,与第二面10b上相同,即可为采用布线42形成无源元件的结构,也可构成为,将具有第二无源元件的电子器件安装在第一面10a上。
此外,在上述实施方式中,作为无源元件例示了电容器C及电感器L,但除此之外,也可构成为,通过调整一部分布线图案的厚度或宽度等形成电阻。
另外,在上述实施方式中,作为电感器L例示了螺旋型的结构,但除此之外,也可构成为,形成·安装环(toroidal)型的电容器。
另外,在上述实施方式中,构成为,通过贯通硅基板10的导通部12,连接第一面10a上的电极与第二面10b上的无源元件,但也可构成为,不采用如导通部12一样的贯通导电部,而采用例如形成在硅基板10的侧面(端面)的布线图案来连接。
另外,也可构成为,由焊料抗蚀剂等树脂材覆盖上述实施方式所示的硅基板10的第二面10b上,由此形成保护膜。
该保护膜,优选形成为至少覆盖无源元件,例如可通过采用光蚀刻法或液滴吐出方式、印刷法、分配(dispense)法等形成。
此外,在本实施方式中,采用形成有半导体元件的硅基板的例子进行了说明,但化合物半导体基板、或多晶硅等半导体形成在上面的玻璃基板、石英基板、有机半导体形成在上面的有机基板等,也可采用完全相同的构造。
Claims (23)
1.一种电子基板,其中,
包含基板,该基板具有:第一面,其形成有有源区域;第二面,其上形成有无源元件,且处于与所述第一面相反的一侧。
2.根据权利要求1所述的电子基板,其中,
包含:贯通导电部,其贯通所述基板;
电极,其形成在所述第一面上,
所述无源元件,经由所述贯通导电部与所述电极电连接。
3.根据权利要求1或2所述的电子基板,其中,
包含配置在所述第二面上或所述第二面的上方的布线图案,
所述无源元件由所述布线图案的一部分构成。
4.根据权利要求3所述的电子基板,其中,
所述布线图案由多个层叠层而形成。
5.根据权利要求3或4所述的电子基板,其中,
包含外部连接端子,
所述布线图案的至少一部分是所述外部连接端子。
6.根据权利要求5所述的电子基板,其中,
在所述外部连接端子的表面安装有电子部件。
7.根据权利要求6所述的电子基板,其中,
所述电子部件具有所述无源元件。
8.根据权利要求5~7中任一项所述的电子基板,其中,
多个所述基板经由所述外部连接端子相互连接而叠层。
9.根据权利要求1~8中任一项所述的电子基板,其中,
在所述第二面设置有应力缓冲层,
所述无源元件的至少一部分形成在所述应力缓冲层上。
10.根据权利要求1~9中任一项所述的电子基板,其中,
在所述第二面上形成有接地电极膜。
11.根据权利要求10所述的电子基板,其中,
所述接地电极膜形成在对应于所述有源区域的配置的位置。
12.根据权利要求10或11所述的电子基板,其中,
所述接地电极膜基于配设在所述第二面上或所述第二面的上方的元件的阻抗而形成。
13.根据权利要求1~12中任一项所述的电子基板,其中,
所述第二面上具有至少保护所述无源元件的保护膜。
14.根据权利要求1~13中任一项所述的电子基板,其中,
在所述有源区域形成有半导体元件。
15.根据权利要求14所述的电子基板,其中,
具有所述半导体元件的半导体器件安装在所述有源区域。
16.根据权利要求1~13中任一项所述的电子基板,其中,
在所述基板上,没有搭载半导体元件。
17.根据权利要求1~16中任一项所述的电子基板,其中,
在所述第一面上设有第二无源元件。
18.根据权利要求17所述的电子基板,其中,
所述第二无源元件由配置在所述第一面上或所述第一面的上方的布线图案的一部分构成。
19.根据权利要求17所述的电子基板,其中,
所述第二无源元件设于安装在所述第一面上或所述第一面的上方的器件上。
20.一种电子设备,其中,
安装有权利要求1~19中任一项所述的电子基板。
21.一种电子基板的制造方法,其中,
在基板的第一面形成有源区域,
在所述基板的与所述第一面相反侧的第二面上形成无源元件。
22.根据权利要求21所述的电子基板的制造方法,其中,
在所述第一面上形成电极,
形成贯通导电部,该贯通导电部贯通所述基板,连接所述电极与所述无源元件。
23.根据权利要求21或22所述的电子基板的制造方法,其中,
在所述第二面上形成接地电极膜。
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JP2007019149A (ja) | 2007-01-25 |
US9087820B2 (en) | 2015-07-21 |
TW200715708A (en) | 2007-04-16 |
US7746663B2 (en) | 2010-06-29 |
KR100821601B1 (ko) | 2008-04-15 |
KR20070005489A (ko) | 2007-01-10 |
US20130181357A1 (en) | 2013-07-18 |
US8284566B2 (en) | 2012-10-09 |
US9496202B2 (en) | 2016-11-15 |
US20070008705A1 (en) | 2007-01-11 |
US8416578B2 (en) | 2013-04-09 |
US20100226109A1 (en) | 2010-09-09 |
US20100223784A1 (en) | 2010-09-09 |
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