CN1877989A - 半导体装置、半导体装置的制造方法、电子器件、电路基板及电子设备 - Google Patents
半导体装置、半导体装置的制造方法、电子器件、电路基板及电子设备 Download PDFInfo
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- CN1877989A CN1877989A CNA2006100887627A CN200610088762A CN1877989A CN 1877989 A CN1877989 A CN 1877989A CN A2006100887627 A CNA2006100887627 A CN A2006100887627A CN 200610088762 A CN200610088762 A CN 200610088762A CN 1877989 A CN1877989 A CN 1877989A
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Abstract
一种半导体装置,包括:半导体基板,具有第一面、和与所述第一面相反的一侧的第二面;外部连接端子,形成于所述半导体基板的所述第一面上;第一电极,形成于所述半导体基板的所述第一面上,且与所述外部连接端子电连接;电子元件,形成于所述半导体基板的所述第二面上或者上方;第二电极,电连接于所述电子元件,且具有表面与背面;槽部,形成于所述半导体基板的所述第二面,且具有包含所述第二电极的所述背面的至少一部分的底面;以及导电部,形成于所述槽部的内部,且与所述第二电极的所述背面电连接。
Description
技术领域
本发明涉及半导体装置、半导体装置的制造方法、电子器件、电路基板、以及电子设备。
背景技术
近年,在移动电话或者电视接收机等电子设备中,例如,作为共振子或者带通滤波器等,使用具有弹性表面波元件(以下,适当称为“SAW(Surface Acoustic Wave面声波)元件”)的电子器件。
特开2002-290184号公报以及特开2002-290200号公报公开了与具有SAW元件的电子器件有关的技术的一例。
特开2002-290184号公报公开了与将SAW元件与驱动控制该SAW元件的集成电路配置于同一的空间内的电子器件的封装(package)有关的技术。
特开2002-290200号公报公开了与将SAW元件安装于第一基板上,将集成电路安装于第二基板上的电子器件的封装有关的技术。
另外,伴随着对安装具有SAW元件的电子器件的电子设备要求小型化,也对安装SAW元件等的电子元件的半导体装置或者安装有电子元件的电子器件要求小型化。
但是,在上述的特开2002-290184号公报公开的结构中,因为并联地配置SAW元件与集成电路,所以小型化较为困难。
同样地,在特开2002-290200号公报公开的结构中,因为配置为重叠安装有SAW元件的第一基板与安装有集成电路的第二基板,所以薄型化(小型化)较为困难。
又,不仅仅是具有SAW元件的电子器件,特别对具有水晶振子、压电振子、压电音叉等需要气密性的电子元件的电子器件也要求小型化。
发明内容
本发明是为了解决上述问题而作成的,其目的在于提供一种可以实现小型化、薄型化以及高功能化的半导体装置、半导体装置的制造方法、电子器件、电路基板以及电子设备。
为了达成上述目的,本发明提供以下的机构。
本发明的半导体装置包括:具备:半导体基板,其具有第一面、和与所述第一面相反的一侧的第二面;外部连接端子,其形成于所述半导体基板的所述第一面上;第一电极,其形成于所述半导体基板的所述第一面上,且与所述外部连接端子电连接;电子元件,其形成于所述半导体基板的所述第二面上或者上方;第二电极,其电连接于所述电子元件,且具有表面和背面;槽部,其形成于所述半导体基板的所述第二面,且具有包含所述第二电极的所述背面的至少一部分的底面;以及导电部,其形成于所述槽部的内部,且与所述第二电极的所述背面电连接。
在本发明的半导体装置中,因为在具有包含第二电极的背面的至少一部分的底面的槽部的内部形成导电部,所以可以利用导电部来电连接第二电极与电子元件。
又,因为第一电极电连接于外部连接端子上,所以可以实现可以与外部设备(例如,电路基板)等连接的半导体装置整体的小型化、薄型化以及高功能化。
又,在本发明的半导体装置中,优选具备:配线,其形成于所述半导体基板的所述第一面上,且电连接所述第一电极和所述外部连接端子;应力缓和层,其形成于所述半导体基板和所述外部连接端子之间。
在本发明的半导体装置中,因为利用配线来电连接第一电极与外部连接端子,由此在半导体装置中形成配线,所以外部连接端子的形状、配置的自由度增大。
又,通过形成应力缓和层,使得外部设备等与半导体装置的连接可靠性较高。
又,在本发明的半导体装置中,优选在所述第二电极的表面上形成与所述配线相同的材料的金属膜。
在本发明的半导体装置中,通常,作为配线的材料,使用耐腐蚀性高的材料。
因而,通过在第二电极的表面形成与配线相同的材料的金属膜,可以防止第二电极的表面的腐蚀,从而防止电方面不良的产生。
又,在本发明的半导体装置中,优选具有形成于所述半导体基板的所述第二面上且与所述导电部电连接的连接电极。
在本发明的半导体装置中,通过具有与导电部电连接的连接电极,例如,通过形成与电子元件的电极形状对应的连接电极,可以提高设计与电子元件的连接构造之际的自由度。
又,本发明的半导体装置的制造方法包括:包括:准备半导体基板的工序,该半导体基板具有第一面、和与所述第一面相反的一侧的第二面;在所述半导体基板的所述第一面上形成第一电极的工序;在所述半导体基板的所述第一面上形成具有表面与背面的第二电极的工序;将电连接于所述第一电极的配线形成于所述半导体基板的所述第一面上的工序;通过将电连接于所述配线的外部连接端子形成于所述半导体基板的所述第一面上,将所述第一电极和所述配线电连接的工序;在所述半导体基板和所述外部连接端子之间形成应力缓和层的工序;在所述半导体基板的所述第二面上形成具有包含所述第二电极的所述背面的至少一部分的底面的槽部的工序;在所述槽部的侧壁上形成绝缘膜的工序;以及将电连接电子元件和所述第二电极的导电部形成在所述槽部内的工序。
在本发明的半导体装置的制造方法中,因为由未形成有第二电极的半导体基板的第二面形成槽部,所以容易形成电连接于第二电极的导电部。
又,因为在槽部的侧壁上形成绝缘膜之后,在槽部形成与第二电极电连接的导电部,所以导电部与半导体基板成为良好地绝缘的状态。
以此,可以从第二电极经由导电部对电子元件正确地赋予电压,从而可以良好地驱动电子元件。
又,在本发明的半导体装置的制造方法中,形成所述槽部的工序优选使用光刻法以及蚀刻法。
在本发明的半导体装置的制造方法中,通过使用光刻法以及蚀刻硅,可以在半导体基板高精度地形成槽部。
又,在本发明的半导体装置的制造方法中,优选包含在所述半导体装置的所述第二面上形成与所述导电部电连接的连接电极的工序,从而所述连接电极与所述导电部一并形成。
在本发明的半导体装置的制造方法中,通过连接电极与导电部成批地形成,就可以有效地制造半导体装置,从而可以降低半导体装置的制造成本。
又,在本发明的半导体装置的制造方法中,优选包含:在所述半导体基板上一并形成多个半导体装置的工序;以及通过切断所述半导体基板,将所述半导体装置各自分割的工序,得到单片化的多个半导体装置。
在本发明的半导体装置的制造方法中,通过在基板上同时形成多个半导体装置,之后,按半导体装置切断该基板,可以高效地制造半导体装置,从而可以降低半导体装置的制造成本。
本发明的电子器件包括:半导体基板,具有第一面、和与所述第一面相反的一侧的第二面;外部连接端子,形成于所述半导体基板的所述第一面上;第一电极,形成于所述半导体基板的所述第一面上,且与所述外部连接端子电连接;电子元件,形成于所述半导体基板的所述第二面上或者上方;第二电极,电连接于所述电子元件;槽部,形成于所述半导体基板的所述第二面上,且具有包含所述第二电极的背面的至少一部分的底面;导电部,形成于所述槽部的内部,电连接于所述第二电极的背面,与所述电子元件电连接;以及密封部件,密封所述电子器件。
在本发明的电子器件中,通过在半导体基板的第二面上形成电子元件,且电连接该电子元件与导电部,可以利用导电部来电连接第二电极与电子元件。
又,因为第一电极与外部连接端子电连接,所以可以实现可以与外部设备等连接的电子器件整体的小型化以及薄型化。
进而,因为电子元件由密封部件密封,所以可以实现电子器件整体的小型化以及薄型化,且良好地驱动电子元件。
又,在本发明的电子器件中,优选所述密封部件,与所述半导体基板的所述第二面间隔配置,且具有所述密封部件中的与所述半导体基板的所述第二面对向的对向面,所述电子元件形成于所述对向面上。
在本发明的电子器件中,因为电子元件形成于密封部件的对向面上,所以通过电连接电子元件与导电部,可以进行电子元件的密封。
因而,通过简单的结构,可以得到密封的电子器件。
又,在本发明的电子器件中,优选包含保持所述电子元件的支持基板,所述密封部件,与所述半导体基板的所述第二面间隔配置,所述支持基板配置于所述密封部件和所述半导体基板之间。
在本发明的电子器件中,因为在支持基板上形成电子元件,所以可以在良好地支撑电子元件的状态下,电连接电子元件与导电部。
因而,可以良好地驱动电子元件。
又,在本发明的电子器件中,优选包含支持基板,该支持基板保持所述电子元件,且与所述半导体基板的所述第二面间隔配置,所述密封部件密封由所述支持基板保持的所述电子元件,并且具有电连接于所述电子元件的电子元件电极。
在本发明的电子器件中,因为保持于支持基板上的电子元件由密封部件密封,所以通过电连接形成于密封部件的电子元件电极与导电部,可以实现小型化、薄型化,且良好地驱动电子元件。
又,在本发明的电子器件中,优选具备连接电极,该连接电极形成在所述半导体基板的所述第二面上,且将所述导电部与所述电子元件电连接。
在本发明的电子器件中,例如,通过形成与电子元件的电极形状对应的连接电极,可以使电子元件与第二电极的导通状态良好。
本发明的电路基板安装上述的电子器件。
在本发明的电路基板上,可以提供安装有实现了小型化·薄型化的电子器件的电路基板(印刷配线板等)。
因而,即使在将该电路基板安装于电子设备等上之际,也可以防止电子设备整体的大型化。
本发明的电子设备安装上述的电子器件。
在本发明的电子设备中,可以提供安装有实现了小型化·薄型化的电子器件的电子设备。
因而,可以得到小型化的电子设备。
附图说明
图1是表示本发明的一实施方式的半导体装置的剖面图;
图2是图1的半导体装置的A向视的俯视图;
图3是图1的半导体装置的B向视的俯视图;
图4A~4C是表示本发明的一实施方式的半导体装置的制造方法的剖面图;
图5A~5C是表示本发明的一实施方式的半导体装置的制造方法的剖面图;
图6是表示本发明的一实施方式的半导体装置的制造方法的剖面图;
图7是表示本发明的第一实施方式的电子器件的剖面图;
图8是表示图7的电子器件的电极的俯视图;
图9是表示本发明的第二实施方式的电子器件的剖面图;
图10是表示本发明的第三实施方式的电子器件的剖面图;
图11是表示本发明的第四实施方式的电子器件的剖面图;
图12是表示搭载有本发明的电子器件的电子设备的图。
具体实施方式
[半导体装置的一实施方式]
接着,参照图1至图6说明本发明的半导体装置的一实施方式。
本发明的半导体装置如图1所示,具有硅基板(半导体基板)10、与连接部20。
连接部20形成于硅基板10的第一面10a上,电连接于作为外部设备的印刷配线板(电路基板)P、和形成于第一面10a上的电极或者配线。
如图1所示,在硅基板10中,在与第一面10a相反的一侧的第二面10b上形成有槽部11。
槽部11的底面包含有第二电极23的背面。
又,在槽部11的内部形成有填充有导电性材料的导电部12。
又,在槽部11的侧壁形成有绝缘膜13,导电部12与硅基板10电绝缘。
又,在硅基板10的第二面10b的表面上,在形成有槽部11的区域以外的区域上形成有背面绝缘层14。
如图3所示,在该背面绝缘层14上,作为电子元件,形成有例如与弹性表面波元件“SAW(Surface Acoustic Wave:表面声波)元件”的电极对应的背面电极(连接电极)15。
连接部20具有形成于硅基板10的第一面10a上的衬底层21、分别形成于衬底层21的多个规定区域上的第一电极以及第二电极23、第一绝缘层24、以及形成于该第一绝缘层24上的配线部30。
在此,衬底层21由例如氧化硅(SiO2)、氮化硅(Si3N4)等绝缘材材料形成。
又,作为第一电极22以及第二电极23的材料,能够列举钛(Ti)、氮化钛(TiN)、铝(Al)、通(Cu)、或者包含有它们的合金等。
又,第一绝缘层24形成于除了形成有第一电极22以及第二电极23的区域之外的硅基板10上。
另外,如图2所示,也可以在硅基板10上形成多个电极,不过在本实施方式中,只说明第一电极22以及第二电极23。
又,第二电极23也可以被第一绝缘层24覆盖。
另外,在衬底层21的下方形成有例如具有晶体管或者存储元件的集成电路。
而且,该集成电路与第一电极22以及第二电极23电连接。
如图1以及图2所示,配线部30具有第一配线(配线)31、金属膜32、第二绝缘层(应力缓和层)33、第二配线(配线)34、以及第三绝缘层35。
第一配线(配线)31电连接于形成在第一绝缘层24上的第一电极22上。
金属膜32形成于第二电极23的表面上。
第二绝缘层(应力缓和层)33形成于第一配线(配线)31以及金属膜32上。
第二配线(配线)34形成于第二绝缘层33上,且与第一配线31电连接。
第三绝缘层35形成于第二配线34上。
又,通过第一配线31的一部分从第二绝缘层33露出,形成台肩部36。
台肩部36与第二配线34电连接。
进而,在第二配线34上形成有凸起37,半导体装置1经由该凸起37而电连接于印刷配线板P上。
又,第三绝缘层35形成于除了形成有凸起37的区域之外的第二绝缘层33上以及第二配线34上。
又,第一电极22经由第一配线31以及第二配线34而与凸起37电连接。
又,第二电极23形成于衬底层21上,所述衬底层21形成于硅基板10的第一面10a上。
又,第二电极23的背面的一部分构成为槽部11的底面。
以此,在槽部11的内部,第二电极23的背面23a与导电部12的第一端部12a电连接。
又,导电部12的第二端部12b与形成于硅基板10的第二面10b上的背面电极15电连接。
即,第二电极23与形成于硅基板10的第二面10b上的电子元件电连接。
又,作为第一配线31以及第二配线34的材料,可以列举金(Au)、铜(Cu)、银(Ag)、钛(Ti)、钨(W)、钛钨(TiW)、氮化钛(TiN)、镍(Ni)、镍钒(NiV)、铬(Cr)、铝(Al)、以及钯(Pd)等。
第一配线31以及第二配线34的各自的构造可以是上述材料的单层构造,也可以是组合了多层而得到的叠层结构。
又,作为用于形成第一绝缘层24、第二绝缘层33、以及第三绝缘层35的材料,是聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、丙烯酸树脂、酚醛树脂、BCB(benzocyclobutene:苯环丁烯)以及PBO(polybenzoxazole聚苯并唑)等、具有绝缘性的材料即可。
另外,第一绝缘层24也可以由氧化硅(SiO2)、氮化硅(Si3N4)等绝缘性材料形成。
又,金属膜32的材料优选是与第一配线31以及第二配线34相同的材料。
作为金属膜32的材料,可以使用Au、TiW、Cu、Cr、Ni、Ti、W、NiV、Al等金属。
又,金属膜32也可以叠层这些金属而形成。
另外,金属膜(叠层结构的情况下,至少为1层)32优选使用比电极耐腐蚀性高的材料,例如,Au、TiW、Cr而形成。
于是,可以防止电极的蚀刻,从而防止电方面不良的产生。
[半导体装置的制造方法]
接着,参照图4A~4C以及图5A~5C,说明半导体装置1的制造方法。
在此,在本实施方式中,半导体装置1同时多个(参照图6)一并形成于同一的硅基板(半导体基板)100上。
以下说明的图4A~4C以及图5A~5C表示分别形成1个半导体装置1的情况。
首先,如图4A所示,在硅基板10的第一面10a上形成衬底层21。
然后,在衬底层21上形成第一电极22以及第二电极23。
然后,在第一电极22以及第二电极23上形成第一绝缘层24,通过众所周知的光刻法(photolithograph)以及蚀刻法,除去覆盖第一电极22以及第二电极23的绝缘材料。
另外,覆盖第二电极23的绝缘材料也可以不除去。
接着,在包含有第一电极22的第一绝缘层24上形成第一配线31,在第二电极23的表面形成金属膜32。
作为第一配线31的形成方法,例如,通过如下操作来进行:在以TiW、Cu的顺序通过溅射法形成之后,以镀敷法形成Cu。
接着,形成第二绝缘膜33使得其覆盖第一配线31以及金属膜32。
然后,通过众所周知的光刻法,除去第二绝缘层33的与台肩部36对应的区域。
以此,第一配线31的一部分露出,从而形成台肩部36。
接着,在第二绝缘层33上形成第二配线34,使其连接于台肩部36。
然后,除了第二绝缘层33上以及第二配线34上的形成凸起37的区域之外,形成第三绝缘层35,使其覆盖第二绝缘层33以及第二配线34。
接着,如图4B所示,通过在硅基板10的第二面10b上以光敏抗蚀剂40为掩模(mask)实施干式蚀刻法,除去与第二电极23对应的部分的硅基板10以及衬底层21。
以此,如图4C所示,从硅基板10的第二面10b开始进行蚀刻,直至形成于第一面10a上的第二电极23的背面23a露出为止,从而形成槽部11。
另外,以光敏抗蚀剂40为掩模,不过并不限定于此,例如,作为硬质掩模(hard mask),也可以使用SiO2膜,也可以同时使用光敏抗蚀剂掩模以及硬质掩模。
又,作为蚀刻方法,并不限定于干式蚀刻法,也可以使用湿式蚀刻、激光加工,或者将它们同时使用。
接着,如图5A所示,在硅基板10的第二面10b以及槽部11的内壁上,形成背面绝缘层14以及绝缘膜13。
背面绝缘膜14以及绝缘膜13防止漏电的产生、由于氧气以及水分等而导致半导体基板10的浸蚀等。
作为背面绝缘膜14以及绝缘膜13的材料,可以使用:使用PECVD(Plasma Enhanced Chemical Vapor Deposition:等离子增强化学汽相沉积)而形成的正硅酸四乙酯(Tetra Ethyl Ortho Silicate:Si(OC2H5)4:以下,称为TEOS),即PE-TEOS、以及使用臭氧CVD而形成的TEOS,即O3-TEOS或者使用CVD而形成的氧化硅(SiO2)。
另外,背面绝缘膜14以及绝缘膜13,只要绝缘性,就可以是其它材料,也可以是树脂。
然后,通过干式蚀刻或者激光加工,除去形成于第二电极23的背面23a上的绝缘膜13,由此,如图5B所示,第二电极23的背面23a露出。
又,在槽部11的侧壁上,残留绝缘膜13。
接着,使用电化学镀(ECP)法,对槽部11的内部实施镀敷处理,在槽部11的内侧形成用于形成导电部12的导电性材料,从而导电部12的第一端部12a与露出的第二电极23,在第二电极23的背面23a上电连接。
作为用于形成导电部12的导电性材料,可以使用例如铜(Cu)。
因而,在槽部11中埋入铜(Cu)。
在本实施方式中,在形成导电部12的工序中,包含有例如通过溅射法形成(叠层)TiN、Cu的工序、和通过镀敷法形成Cu的工序。
另外,也可以包含通过溅射法形成(叠层)TiW、Cu的工序、和通过镀敷法形成Cu的工序。
另外,作为导电部12的形成方法,并不限定于上述方法,也可以埋入导电糊、熔融金属、金属线等。
又,在本实施方式中,用导电部12填埋槽部11的内部,不过也可以并不完全填埋,而在槽部11的内壁上形成导电部12,从而在第二电极23的背面23a电连接。
形成导电部12之后,如图5C所示,在硅基板10的第二面10b上形成与导电部12电连接的背面电极15。
另外,也可以在形成背面电极15之际,同时形成背面电极15与导电部12。
即,也可以一并形成背面电极15与导电部12。
接着,在形成于硅基板10的第一面10a上的第二配线34上,搭载例如由铅软钎料构成的凸起37。
另外,在形成凸起37之际,可以将软钎料球搭载于第二配线34上,也可以将软钎料膏印刷于第二配线34上。
在以上的工序中,在一个硅基板100上同时一并形成多个半导体装置1。
接着,如图6所示,利用切割(dicing)装置110,按半导体装置1切割(切断)硅基板100。
这样,通过在硅基板100上大约同时形成多个半导体装置1,然后按半导体装置1切断该硅基板100,可以使如图1所示的半导体装置1单片化,从而得到多个。
这样就可以有效地制造半导体装置1,从而可以降低半导体装置1的制造成本。
根据本发明的半导体装置1,通过在达到第二电极23的槽部11的内部形成导电部12,可以经由导电部12电连接第二电极23与电子元件。
又,因为第一电极22与凸起37电连接,所以可以实现可以与外部设备等连接的半导体装置1的整体的小型化、薄型化以及高功能化。
[电子器件的第一实施方式]
接着,参照图7说明在上述半导体装置1上安装有作为电子元件的SAW元件(电子元件)60的电子器件50的第一实施方式。
另外,在以下说明的各实施方式中,对与上述一实施方式的半导体装置1具有共用的结构的部位标注同一附图标记,省略说明。
在使用于本实施方式的电子器件50中的半导体装置51中,除了未形成有背面电极15这一点之外,具有与上述半导体装置1相同的结构。
如图8所示,电子器件50具有压电薄膜、和与压电薄膜相接触的梳齿电极61。
而且,如图7所示,电子器件50形成于硅基板10的第二面10b上。
又,SAW元件60,与导电部12的第二端部12b电连接,直接形成于第二面10b上。
又,在硅基板10的第一面10a上,形成有例如具有晶体管、存储元件的集成电路。
导电部12的第一端部12a经由第二电极23,与该集成电路电连接。
因而,形成于硅基板10的第二面10b上的电子元件60、和形成于硅基板10的第一面10a上的集成电路经由导电部12电连接。
又,电子器件50具有密封部件52。
通过将SAW元件60配置于密封部件52与硅基板10的第二面10b之间,密封SAW元件60。
在本实施方式中,密封部件52由玻璃基板形成,不过也可以由硅基板形成。
密封部件52与硅基板10的第二面10b间隔配置。
硅基板10的第二面10b的周边部与密封部件52的内面52a的周边部由粘接剂层53粘接。
作为粘接剂层53,例如可以列举聚酰亚胺树脂等合成树脂。
而且,由硅基板10的第二面10b、密封部件52的内面52a、以及粘接剂层53包围的内部空间55大致密闭(气密性密封),在该内部空间55中配置SAW元件60。
[电子器件的制造方法]
接着,说明电子器件50的制造方法。
首先,在通过与上述半导体装置1的制造方法相同的工序,形成导电部12之后,在硅基板10的第二面10b上形成SAW元件60。
形成该SAW元件60的工序,包括:形成压电薄膜的工序、形成如图8所示的梳齿电极61使其与压电薄膜接触的工序、以及形成保护膜的工序。
进而,形成SAW元件60的工序,包括对SAW元件60照射等离子等从而进行调频的工序。
作为压电薄膜的材料,可以列举氧化锌(ZnO)、氮化铝(AlN)、铌酸锂(LiNbO3)、钽酸锂(LiTaO3)、铌酸钾(KNbO3)等。
作为梳齿电极61的材料,可以列举含铝的金属。
作为保护膜的材料,可以列举氧化硅(SiO2)、氮化硅(Si3N4)、氮化钛(TiN)等。
然后,形成的SAW元件60,在硅基板10的第二面10b上,与导电部12的第二端部12b电连接。
接着,在硅基板10的第二面10b以及密封部件52的内面52a中的至少一方上,形成用于形成粘接剂层53的粘接剂。
作为粘接剂层53,例如可以使用感光性聚酰亚胺粘接剂等。
然后,利用该粘接剂层53来接合硅基板10与密封部件52,使得硅基板10的第二面10b与密封部件52的内面52a对向。
以此,就能够得到如图7所示的电子器件50。
在此,作为密封SAW元件60的构造,采用使内部空间55为真空的真空密封、以N2、Ar、He等规定气体置换内部空间55中的气体的气体置换密封等的构造。
另外,在接合硅基板10与密封部件52时,也可以沿着硅基板10的第二面10b的周边部形成金属突起,在密封部件52的内面52a形成用于与所述金属突起粘接的金属层,从而利用金属突起以及金属层来接合硅基板10与密封部件52。
在密封部件52使用透射性的玻璃的情况下,也可以在密封工序之后,通过使激光等透过玻璃,进行SAW元件60的调频。
然后,在形成于硅基板10的第一面10a上的第二配线34上,搭载例如由铅软钎料构成的凸起37。
另外,在形成凸起37之际,可以在第二配线34上搭载钎料球,也可以在第二配线34上印刷钎料膏。
在这样的电子器件50的制造方法中,与半导体装置1的制造方法同样地,在同一硅基板(半导体基板)上同时一并形成半导体装置50、SAW元件60以及密封部件52等。
与半导体装置1的制造方法同样地,通过使用切割装置110,按电子器件50进行切割(切断)。
以此,就可以以低成本制造电子器件50。
制造的电子器件50利用凸起37而搭载于印刷配线板P等上。
在本实施方式的电子器件50中,在硅基板10的第二面10b上形成SAW元件60,并连接导电部12的第二端部12b与该SAW元件60。
在该情况下,通过预先在硅基板10的第一面10a上形成驱动控制SAW元件60的集成电路,可以经由导电部12来电连接SAW元件60与集成电路。
因而,可以实现电子器件50整体的小型化·薄型化,且良好地驱动SAW元件60。
而且,因为SAW元件60被密封在密封部件52与第二面10b之间,所以可以实现小型化·薄型化,且良好地密封SAW元件60,从而可以良好地驱动SAW元件60。
[电子器件的第二实施方式]
接着,参照图9说明在上述半导体装置1上安装有作为电子元件的SAW元件71的电子器件70的第二实施方式。
另外,在以下说明的各实施方式中,对与上述一实施方式的电子器件50的结构共用的部位标注同一附图标记,省略说明。
本实施方式的电子器件70在如下点上与第一实施方式不同:SAW元件71并不形成于硅基板10的第二面10b上,而是形成于与硅基板10的第二面10b间隔配置的密封部件52上。
SAW元件71形成于与硅基板10的第二面10b对向的密封部件52的内面(对向面)52a上。
又,在SAW元件71上形成有与硅基板10的第二面10b对向的端子72。
在半导体装置73上,在硅基板10的第二面10b的槽部11上形成有背面电极(连接电极)54。
而且,该背面电极54与导电部12的第二端部12b电连接。
背面电极54形成于与SAW元件71的端子72对应的位置上。
即,第二电极23利用导电部12以及背面电极54,与形成在密封部件52的内面(对向面)52a上的SAW元件71电连接。
又,密封部件52例如由硅基板、水晶基板、具有硅以及金刚石的基板构成。
说明电子器件70的制造方法。
首先,在密封部件52的内表面52a上预先形成SAW元件71。
接着,在硅基板10的第二面10b上形成背面电极54。
接着,在密封部件52的内面52a上形成SAW元件71。
另外,还形成端子72。
接着,利用粘接剂层53来接合硅基板10与密封部件52,使得背面电极54与端子72电连接。
以此,得到如图9所示的电子器件70。
另外,在接合背面电极54与端子72的工序中,也可以通过粘接剂层53的收缩来压接背面电极54与端子72。
根据本实施方式的电子器件70可知,因为在与硅基板10不同的部件即密封部件52上形成SAW元件71,所以SAW元件71不易受到被赋予给硅基板10的热应力或者膜应力的影响,从而可以得到良好的特性。
[电子器件的第三实施方式]
接着,参照图10说明在上述半导体装置1上安装有作为电子元件的SAW元件81的电子器件80的第三实施方式。
本实施方式的电子器件80在如下点上与第二实施方式不同:SAW元件81不形成于硅基板10的第二面10b上,SAW元件81形成于支持基板82上。
支持基板82配置于硅基板10的第二面10b、和与硅基板10的第二面10b间隔配置的密封部件52之间。
又,SAW元件81形成于与硅基板10的第二面10b对向的支持基板82的面82a上。
进而,在SAW元件81上,与电子器件70的第二实施方式同样地,形成有与硅基板10的第二面10b对向的端子83。
而且,该端子83与背面电极54电连接。
根据本实施方式的电子器件80可知,因为在与硅基板10不同的部件即支持基板82上形成SAW元件81,所以SAW元件81不易受到被赋予给硅基板10的热应力或者膜应力的影响,从而可以得到良好的特性。
又,可以在通过支持基板82来良好地支承SAW元件81的状态下,电连接SAW元件81与导电部12。
[电子器件的第四实施方式]
接着,参照图11说明在上述半导体装置1上安装有作为电子元件的AT振子(水晶振子)91的电子器件90的第四实施方式。
本实施方式的电子器件90在如下点上与第二实施方式不同:AT振子91在保持于支持基板92上的状态下由密封部件93密封。
支持基板92与硅基板10的第二面10b间隔配置。
AT振子91形成于与硅基板10的第二面10b对向的支持基板92的内面92a上。
AT振子91由形成于支持基板92与硅基板10的第二面10b之间的、由玻璃基板构成的密封部件93密封。
而且,由支持基板92的内面92a与密封部件93的内面93a包围的内部空间95被大致密闭(气密性密封)。
又,在密封部件93上,与硅基板10的第二面10b对向的面上形成有电子元件电极94。
又,电子元件电极94形成为覆盖密封部件93。
而且,该电子元件电极94与背面电极54电连接。
即,第二电极23利用形成于硅基板10上的导电部12、以及形成于硅基板10的第二面10b上的背面电极54,与AT振子91电连接。
又,硅基板10的第二面10b的周边部与支持基板92的周边部由密封部件96密封。
又,第二面10b与密封部件93之间由密封树脂96密封。
根据本实施方式的电子器件90可知,因为保持于支持基板92上的AT振子由密封部件93密封,所以可以电连接形成与密封部件93上的电子元件电极94与导电部12。
又,可以实现小型化、薄型化,且良好地驱动电子元件。
[电子设备]
图12是表示搭载有上述电子器件50、70、80、90的任一个的电子设备的一例的图,是表示移动电话300的图。
因为搭载有实现了小型化·薄型化以及高功能化的本发明的电子器件,所以可以实现小型的移动电话300。
另外,本发明的技术范围并不限定于上述实施方式,可以在不脱离本发明的宗旨的范围内,进行各种变更。
例如,在上述半导体装置1的一实施方式中,形成背面电极15,不过电子器件的电极也可以直接连接于导电部12的第二端部12b上。
又,优选在连接于SAW元件60、71、81或者AT振子91上的背面电极15、54的表面或者导电部12的第二端部12b的表面上,形成金等的表面处理、或者原料材(SnAg镀敷等),使得容易进行金属连接。
又,在上述各实施方式中,除了在最终工序中进行切割之外,也可以在适当的工序(中间工序)中进行单片化。
进而,在通过玻璃基板构成密封部件52、93的情况下,在切割(切断)由该玻璃基板构成的密封部件52、93之际,也可以通过参照图6说明的切割装置110来切割,不过也可以通过照射激光来进行切割,或者使用干式蚀刻或者湿式蚀刻的方法来进行切割。
又,作为本发明的电子元件,在第一、第二、第三实施方式中,使用SAW元件进行了说明,不过并不限定于此,也可以是需要密封构造的元件,例如,水晶振子、压电振子、压电音叉等。
又,在第四实施方式中,使用AT振子(水晶振子)进行了说明,不过并不限定于此,也可以是需要密封构造的元件,例如,SAW振子、压电振子、压电音叉等。
又,也可以根据需要,在将连接部30形成于硅基板10上之后,进行硅基板10的薄型化。
说明薄化硅基板10的方法。
首先,使用通过紫外光(UV光)的照射而可以剥离的粘接剂,在硅基板10的第一面10a侧贴附未图示的玻璃板。
该玻璃板是被称为WSS(Wafer Support System晶片支持系统)的系统的一部分,在玻璃板上支持硅基板10后,在贴附有该玻璃板的状态下,对于硅基板10的第二面10b实施抛光处理、干式蚀刻处理、或者湿式蚀刻处理等规定的处理。
以此,可以薄化硅基板10。
Claims (15)
1.一种半导体装置,其中,
具备:
半导体基板,其具有第一面、和与所述第一面相反的一侧的第二面;
外部连接端子,其形成于所述半导体基板的所述第一面上;
第一电极,其形成于所述半导体基板的所述第一面上,且与所述外部连接端子电连接;
电子元件,其形成于所述半导体基板的所述第二面上或者上方;
第二电极,其电连接于所述电子元件,且具有表面和背面;
槽部,其形成于所述半导体基板的所述第二面,且具有包含所述第二电极的所述背面的至少一部分的底面;以及
导电部,其形成于所述槽部的内部,且与所述第二电极的所述背面电连接。
2.如权利要求1所述的半导体装置,其中,
具备:
配线,其形成于所述半导体基板的所述第一面上,且电连接所述第一电极和所述外部连接端子;
应力缓和层,其形成于所述半导体基板和所述外部连接端子之间。
3.如权利要求1或者2所述的半导体装置,其中,
在所述第二电极的所述表面上,形成有与所述配线相同的材料的金属膜。
4.如权利要求1至3中任一项所述的半导体装置,其中,
具备连接电极,该连接电极形成于所述半导体基板的所述第二面上且与所述导电部电连接。
5.一种半导体装置的制造方法,其中,
包括:
准备半导体基板的工序,该半导体基板具有第一面、和与所述第一面相反的一侧的第二面;
在所述半导体基板的所述第一面上形成第一电极的工序;
在所述半导体基板的所述第一面上形成具有表面与背面的第二电极的工序;
将电连接于所述第一电极的配线形成于所述半导体基板的所述第一面上的工序;
通过将电连接于所述配线的外部连接端子形成于所述半导体基板的所述第一面上,将所述第一电极和所述配线电连接的工序;
在所述半导体基板和所述外部连接端子之间形成应力缓和层的工序;
在所述半导体基板的所述第二面上形成具有包含所述第二电极的所述背面的至少一部分的底面的槽部的工序;
在所述槽部的侧壁上形成绝缘膜的工序;以及
将电连接电子元件和所述第二电极的导电部形成在所述槽部内的工序。
6.如权利要求5所述的半导体装置的制造方法,其中,
形成所述槽部的工序使用光刻法以及蚀刻法。
7.如权利要求5或者6所述的半导体装置的制造方法,其中,
包含:在所述半导体基板的所述第二面上形成与所述导电部电连接的连接电极的工序,
所述连接电极及所述导电部一并形成。
8.如权利要求5至7中任一项所述的半导体装置的制造方法,其中,
包含:
在所述半导体基板上一并形成多个半导体装置的工序;以及
通过切断所述半导体基板,将所述半导体装置各自分割的工序,
得到单片化的多个半导体装置。
9.一种电子器件,其中,
包括:
半导体基板,具有第一面、和与所述第一面相反的一侧的第二面;
外部连接端子,形成于所述半导体基板的所述第一面上;
第一电极,形成于所述半导体基板的所述第一面上,且与所述外部连接端子电连接;
电子元件,形成于所述半导体基板的所述第二面上或者上方;
第二电极,电连接于所述电子元件;
槽部,形成于所述半导体基板的所述第二面上,且具有包含所述第二电极的背面的至少一部分的底面;
导电部,形成于所述槽部的内部,电连接于所述第二电极的背面,与所述电子元件电连接;以及
密封部件,密封所述电子器件。
10.如权利要求9所述的电子器件,其中,
所述密封部件,与所述半导体基板的所述第二面间隔配置,且具有所述密封部件中的与所述半导体基板的所述第二面对向的对向面,
所述电子元件形成于所述对向面上。
11.如权利要求9所述的电子器件,其中,
包含保持所述电子元件的支持基板,
所述密封部件,与所述半导体基板的所述第二面间隔配置,所述支持基板配置于所述密封部件和所述半导体基板之间。
12.如权利要求9所述的电子器件,其中,
包含支持基板,该支持基板保持所述电子元件,且与所述半导体基板的所述第二面间隔配置,
所述密封部件密封由所述支持基板保持的所述电子元件,并且具有电连接于所述电子元件的电子元件电极。
13.如权利要求9至12中任一项所述的电子器件,其中,
具备连接电极,该连接电极形成在所述半导体基板的所述第二面上,且将所述导电部与所述电子元件电连接。
14.一种电路基板,其中,
安装有如权利要求9至13中任一项所述的电子器件。
15.一种电子设备,其中,
安装有如权利要求9至13中任一项所述的电子器件。
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JP4311376B2 (ja) | 2005-06-08 | 2009-08-12 | セイコーエプソン株式会社 | 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 |
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