CN1171298C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN1171298C CN1171298C CNB961805099A CN96180509A CN1171298C CN 1171298 C CN1171298 C CN 1171298C CN B961805099 A CNB961805099 A CN B961805099A CN 96180509 A CN96180509 A CN 96180509A CN 1171298 C CN1171298 C CN 1171298C
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- semiconductor chip
- lead
- carrier band
- semiconductor device
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- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP1996/003407 WO1998022980A1 (fr) | 1996-11-21 | 1996-11-21 | Dispositif a semi-conducteur et son procede de fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1234909A CN1234909A (zh) | 1999-11-10 |
CN1171298C true CN1171298C (zh) | 2004-10-13 |
Family
ID=25744085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB961805099A Expired - Fee Related CN1171298C (zh) | 1996-11-21 | 1996-11-21 | 半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (2) | US6664616B2 (zh) |
KR (2) | KR100447313B1 (zh) |
CN (1) | CN1171298C (zh) |
AU (1) | AU7589196A (zh) |
WO (1) | WO1998022980A1 (zh) |
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JPH08222691A (ja) * | 1995-02-14 | 1996-08-30 | Fujitsu Ltd | 半導体装置 |
JP2944449B2 (ja) | 1995-02-24 | 1999-09-06 | 日本電気株式会社 | 半導体パッケージとその製造方法 |
-
1996
- 1996-11-21 AU AU75891/96A patent/AU7589196A/en not_active Abandoned
- 1996-11-21 US US09/308,620 patent/US6664616B2/en not_active Expired - Fee Related
- 1996-11-21 CN CNB961805099A patent/CN1171298C/zh not_active Expired - Fee Related
- 1996-11-21 KR KR10-1999-7004408A patent/KR100447313B1/ko not_active IP Right Cessation
- 1996-11-21 WO PCT/JP1996/003407 patent/WO1998022980A1/ja active IP Right Grant
- 1996-11-21 KR KR10-2004-7003121A patent/KR100447035B1/ko not_active IP Right Cessation
-
2003
- 2003-05-01 US US10/426,714 patent/US6759272B2/en not_active Expired - Fee Related
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US6759272B2 (en) | 2004-07-06 |
US6664616B2 (en) | 2003-12-16 |
KR100447313B1 (ko) | 2004-09-07 |
US20030162326A1 (en) | 2003-08-28 |
KR100447035B1 (ko) | 2004-09-07 |
WO1998022980A1 (fr) | 1998-05-28 |
KR20000057139A (ko) | 2000-09-15 |
CN1234909A (zh) | 1999-11-10 |
KR20040040450A (ko) | 2004-05-12 |
AU7589196A (en) | 1998-06-10 |
US20020180010A1 (en) | 2002-12-05 |
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