CN1282246C - 可阻断寄生损失电流的高功率射频集成电路及其制造方法 - Google Patents
可阻断寄生损失电流的高功率射频集成电路及其制造方法 Download PDFInfo
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 25
- 230000000903 blocking effect Effects 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
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- 239000000758 substrate Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 10
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- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005234 chemical deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 2
- 239000012071 phase Substances 0.000 claims 2
- 239000007792 gaseous phase Substances 0.000 claims 1
- 238000001459 lithography Methods 0.000 claims 1
- 230000005674 electromagnetic induction Effects 0.000 abstract description 6
- 238000000227 grinding Methods 0.000 abstract description 4
- 244000045947 parasite Species 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
本发明提供一种可阻断寄生损失电流的高功率射频集成电路及其制造方法,其是在高功率射频组件完成包括电感组件在内的半导体基底正面工艺步骤后,基底背面须经过研磨处理至一定厚度,之后可进行背面沟槽式接触窗的显影蚀刻步骤,并进行一背面氧化绝缘层的沉积,使此氧化绝缘层配置在基底中且正位于电感组件下方,以阻断电感组件在该基底中因电磁感应产生的损失寄生电流,并改进电感组件在高频操作下的效能。
Description
技术领域
本发明涉及一种高功率射频集成电路(RF IC)的技术,特别是关于一种可阻断内建电感组件产生的寄生损失电流的高功率射频集成电路及其制造方法。
背景技术
目前,射频集成电路组件广泛应用在各式无线通讯设备上,随着无线通讯的快速成长,射频半导体产业包含着快速变迁的技术,且因无线通讯设备变得越来越复杂,功能越来越多,这也就代表着需要更高的功率,换言之,随着无线通讯的应用日趋成熟,射频组件的功率也随之向上攀升。
现有的具有内建电感组件的硅芯片的剖视图如图1所示,其是在一硅基底10上形成有场氧化晶体管的有源组件,包括场氧化层12、栅极氧化层14、多晶硅层16、栅极间隙物(Spacer)18及源/漏极区域20;在有源组件形成后,接着在硅基底10上沉积一二氧化硅介电层22,并在该二氧化硅介电层22上方,以内建方式将电感组件24配置于硅基底10的场氧化层12的正上方,且此电感组件24包含多层的电感线圈242,各层电感线圈242之间以介电层作244为电性绝缘,且各层电感线圈242间以插塞246形成电性连接。
然而,内建电感组件24会因电磁感应而在硅基底10沿着电感线圈242的轴方向有寄生电流的流失,导致其Q值将会流失下降,进而影响到电感组件24在高频高功率操作下的表现,造成电感组件24的效能相对降低。
发明内容
本发明所要解决的技术问题是提供一种高功率射频集成电路及其制造方法,其在电感组件正下方形成氧化绝缘层,使电感组件下方的半导体基底均为绝缘层,以有效阻断电感组件因电磁感应而在基底中产生的寄生损失电流,同时可避免造成电感组件的Q值下降,进而改进电感组件在高频操作下的效能。
为了解决上述技术问题,本发明提供的高功率射频集成电路结构是:在一半导体基底上设置复数有源组件与用以隔离该等有源组件的复数隔离结构;至少一介电层位于该半导体基底上,使其覆盖该有源组件及隔离结构;并在该隔离结构上方的介电层表面配置数电感组件;及一沟槽式绝缘层,其配置在该电感组件下方的半导体基底中,使该沟槽式绝缘层直接连接隔离结构。
本发明还提供一种上述高功率射频集成电路结构的制造方法,首先,在一半导体基底上依序形成隔离结构、有源组件与介电层,并有数电感组件形成于该隔离结构上方的介电层表面;接着,在半导体基底上形成一保护层,以覆盖保护上述各组件;然后将半导体基底背面研磨至一定厚度后,利用光刻蚀刻工艺,在半导体基底背面形成一图案化光刻胶层;再以此图案化光刻胶层为掩模,蚀刻半导体基底背面直至该隔离结构为止,以形成一沟槽式接触窗,而后移除该图案化光刻胶;最后,在该沟槽式接触窗内进行气相绝缘层的沉积及平坦化,以形成一沟槽式绝缘层,使此沟槽式绝缘层能够直接连接至该隔离结构且位于电感组件正下方。
本发明可有效阻断电感组件因电磁感应而在基底中产生的寄生损失电流。以及可避免造成电感组件的Q值下降,进而改进电感组件在高频操作下的效能。
下面通过具体实施例配合附图进行详细说明,以进一步了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1是现有的具有内建电感组件的硅芯片的结构剖视图。
图2是本发明具有内建电感组件的射频集成电路组件的结构剖视图。
图3及图4是本发明在进行半导体基背面工艺的结构剖视图。
图5是本发明具有内建电感组件的射频集成电路组件的结构俯视图。
标号说明:
10 硅基底 12 场氧化层
14 栅极氧化层 16 多晶硅层
18 栅极间隙物 20 源/漏极区域
22 二氧化硅介电层 24 电感组件
242 电感线圈 244 介电层
246 插塞
30 半导体基底 302 有源区域
304 隔离区域 32 有源组件
34 栅极氧化层 36 多晶硅层
38 栅极间隙物 40 源/漏区域
42 场氧化隔离结构 44 介电层
46 电感组件 462 电感线圈
464 介电层 466 插塞
48 沟槽式绝缘层 50 保护层
52 图案化光刻胶层 54 沟槽式接触窗
具体实施方式
本发明高功率的射频集成电路(RF IC)组件是以沟槽式绝缘层的简单方式来阻断其内建电感组件在半导体基底内所产生的寄生损失电流。
图2是本发明具有内建电感组件的射频集成电路组件的结构剖视图,如图所示,一半导体基底30,通常为硅晶片,其上具有一有源区域302及一隔离区域304;在有源区域302内配置有多个有源组件32,有源组件32为由栅极氧化层34、多晶硅层36、栅极间隙物38和源/漏区域40所形成的场氧化晶体管结构,且该有源组件32除了场氧化晶体管之外,亦可是双偶极晶体管或二种晶体管的组合;并在半导体基底30上的隔离区域304内配置有如图所示的场氧化隔离结构42,用以隔离该等有源组件32,其中该隔离结构42亦可为浅沟槽隔离结构。
接着,在该半导体基底30上的有源区域302与隔离区域304上方沉积形成一介电层44,此介电层44为经过平坦化的二氧化硅或其它低介电常数(low K)的材质,使该介电层44覆盖该有源组件32及场氧化隔离结构42,并在该场氧化隔离结构42上方的介电层44表面形成多个电感组件46,其包含多层围绕如线圈结构的电感线圈462,各层电感线圈462之间以介电层464作为电性绝缘,且各层电感线圈462间并以插塞466形成电性连接,并通过介电层44绝缘隔离下方的有源区域302与隔离区域304和上方的电感组件46;最后,有一沟槽式绝缘层48形成于该电感组件46下方的半导体基底30中,使该沟槽式绝缘层48直接连接场氧化隔离结构42,且此沟槽式绝缘层48的材质是硅氧化物、硅氮化物或其它化学沉积绝缘物质。
其中,在高功率的RF IC组件依序完成场氧化隔离结构42、有源组件32、介电层44与电感组件46的前段工艺步骤之后,通常需要经过一基底背面研磨步骤。在进行研磨之前,先在该半导体基底30上形成一保护层50,如图3所示,使其覆盖上述各组件,避免破坏到基底30表面的各组件;接着将半导体基底30背面研磨至一定厚度后,其厚度约为100微米左右,再利用光刻蚀刻工艺,在半导体基底30背面形成一图案化光刻胶层52,并以该图案化光刻胶层52为光刻,蚀刻该半导体基底30背面直至场氧化隔离结构42为止,以形成一沟槽式接触窗54,而后移除该图案化光刻胶52。接续参阅图4所示,在该沟槽式接触窗54内进行气相绝缘层的沉积及平坦化的工艺,先利用化学气相沉积方式,沉积包含硅氧化物、硅氮化物或其它各类的化学沉积绝缘物质,沉积填充于沟槽式接触窗54内,再经由化学干蚀刻方式或化学机械研磨方式进行全面性平坦化处理,直至沉积绝缘物质仅填充于电感组件46下方的沟槽式接触窗54内,以形成一沟槽式绝缘层48,其直接连接至场氧化隔离结构42且正位于该电感组件46下方。
本发明在半导体基底中正位于电感组件及场氧化隔离结构下方配置一沟槽式绝缘层,使电感组件正下方于基底中均为非导电的绝缘体,将可阻断半导体基底中因电磁感应所产生的寄生损失电流,避免造成电感组件的Q值下降,进而改进电感组件在高频操作的效能。
图5为本发明的一个较佳实施例,其为具有内建电感组件的射频集成电路组件的结构俯视图,如图所示,其中位于电感组件46的下方,且位于半导体基底30中直接连接于氧化隔离结构42下方的沟槽式绝缘层48,使其可有效阻断因电感组件46因电磁感应所产生在X轴方向的寄生损失电流。
以上所述的实施例仅用于说明本发明的技术思想及特点,其目的在于使本领域内的普通技术人员能够了解本发明的内容并据以实施,并不能仅以此来限定本发明的专利范围,即凡依本发明所揭示的精神所作的同等变化或修饰,均应涵盖在本发明的专利范围内。
Claims (16)
1、一种可阻断寄生损失电流的高功率射频集成电路,其特征在于,其结构包括:
一半导体基底,其上具有一有源区域及一隔离区域;
多个有源组件,其配置在该半导体基底的有源区域内;
多个隔离结构,其设置在该隔离区域内,且用以隔离所述有源组件;
至少一介电层,其位于该半导体基底上,使其覆盖在该有源组件及该隔离结构上,以绝缘其上和其下的组件;
数个电感组件,其形成于该隔离结构上方的该介电层表面;及
一沟槽式绝缘层,其配置在该电感组件下方的所述半导体基底中,使该沟槽式绝缘层直接连接该隔离结构。
2、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中所述有源组件包括场氧化晶体管、双偶极晶体管或二种晶体管的组合。
3、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中该有源组件为由栅极氧化层、多晶硅层、栅极间隙物和源/漏区域形成的晶体管组件结构。
4、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中该隔离结构为场氧化隔离结构或浅沟槽隔离结构。
5、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中该介电层的材质是由二氧化硅或其它具有低介电常数的材质构成的。
6、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中该电感组件包括多层的电感线圈,各层电感线圈之间以介电层作为电性绝缘,且各层电感线圈间以插塞形成电性连接。
7、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中该沟槽式绝缘层的材质选自硅氧化物、硅氮化物及其它化学沉积绝缘物质所组成的群组。
8、根据权利要求1所述的可阻断寄生损失电流的高功率射频集成电路,其特征在于,
其中该沟槽式绝缘层先利用背面微影蚀刻工艺而形成一沟槽式接触窗,再利用化学气相沉积方法形成该沟槽式绝缘层。
9、一种可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其包括下列步骤:
提供一半导体基底;
在该半导体基底表面上依序形成隔离结构、有源组件与介电层,使该介电层覆盖该有源组件及该隔离结构上,以绝缘其上和其下的组件,并有数个电感组件形成于该隔离结构上方的该介电层上;
在该半导体基底上形成一保护层,以覆盖保护上述各组件;
将该半导体基底背面研磨至一定厚度后,在该半导体基底背面形成一图案化光刻胶层;
以该图案化光刻胶层为掩模,蚀刻该半导体基底背面直至该隔离结构,以形成一沟槽式接触窗,而后移除该图案化光刻胶;及
在该沟槽式接触窗内进行气相绝缘层的沉积及平坦化,以形成一沟槽式绝缘层,其直接连接至该隔离结构且位于该电感组件下方。
10、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其中该隔离结构为场氧化隔离结构或浅沟槽隔离结构。
11、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其中该有源组件包括场氧化晶体管、双偶极晶体管或二种晶体管的组合。
12、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其中该有源组件为由栅极氧化层、多晶硅层、栅极间隙物和源/漏区域形成的晶体管组件结构。
13、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其中该介电层的材质由二氧化硅或其它具有低介电常数的材质构成的。
14、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其中该电感组件包括多层的电感线圈,各层电感线圈之间以介电层作为电性绝缘,且各层电感线圈间以插塞形成电性连接。
15、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其中该沟槽式绝缘层的材质选自硅氧化物、硅氮化物及其它化学沉积绝缘物质所组成的群组。
16、根据权利要求9所述的可阻断寄生损失电流的高功率射频集成电路的制造方法,其特征在于,其中该气相绝缘层的沉积是利用化学气相沉积方式形成的。
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US10/922,981 US20050045985A1 (en) | 2003-09-01 | 2004-08-23 | High power radio frequency integrated circuit capable of impeding parasitic current loss |
US11/335,758 US7338853B2 (en) | 2003-09-01 | 2006-01-20 | High power radio frequency integrated circuit capable of impeding parasitic current loss |
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US8264065B2 (en) | 2009-10-23 | 2012-09-11 | Synopsys, Inc. | ESD/antenna diodes for through-silicon vias |
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