CN102726129B - 电子器件 - Google Patents
电子器件 Download PDFInfo
- Publication number
- CN102726129B CN102726129B CN201180005515.5A CN201180005515A CN102726129B CN 102726129 B CN102726129 B CN 102726129B CN 201180005515 A CN201180005515 A CN 201180005515A CN 102726129 B CN102726129 B CN 102726129B
- Authority
- CN
- China
- Prior art keywords
- mentioned
- terminal
- semiconductor chip
- electronic device
- passive device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 113
- 239000010410 layer Substances 0.000 claims description 102
- 230000004888 barrier function Effects 0.000 claims description 32
- 239000011229 interlayer Substances 0.000 claims description 28
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000000926 separation method Methods 0.000 abstract description 12
- 230000010354 integration Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 54
- 229910052751 metal Inorganic materials 0.000 description 54
- 239000000463 material Substances 0.000 description 42
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000011241 protective layer Substances 0.000 description 11
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 238000009434 installation Methods 0.000 description 8
- 239000000565 sealant Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011888 foil Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000003292 diminished effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
在将半导体芯片(半导体元件)及无源器件集成于多层布线板且半导体芯片及无源器件构成反馈电路的电子器件中,将半导体芯片(半导体元件)的输入端及输出端之间电气分离。该电子器件具备:多层布线板;半导体芯片,配置于上述多层布线板的主面上或内部;无源器件,配置于上述多层布线板的内部,具有与上述半导体芯片的输入端及输出端分别连接的第1端子及第2端子,构成上述多层布线板的导电性部件配置在使得其距上述第1端子及上述第2端子的至少一方的距离比上述第1端子及第2端子间的距离小的位置上。
Description
技术领域
本发明涉及在多层布线板上集成半导体芯片及无源器件而得到的高密度安装的电子器件。
背景技术
随着电子设备的小型化、轻量化、薄型化等,将电子器件复合化(将多个电子器件组合而做成1个电子器件)而高密度安装的电子器件的开发被不断推进。关于高密度安装,例如在多层布线板上集成半导体芯片(半导体元件)和无源器件(电感器、电容器、电阻器),而构成1个电子器件(例如,混合(混成)IC(集成电路))。
另一方面,为了构成以半导体芯片(半导体元件)为中心的反馈电路,在半导体芯片(半导体元件)上连接反馈(feedback)元件。例如,在半导体芯片(半导体元件)的输入端及输出端之间连接无源器件(反馈元件),构成为信号从输出侧向输入侧反馈(例如,参照专利文献1)。
在构成这样的反馈电路的情况下,需要将半导体芯片(半导体元件)的输入端及输出端之间电气分离。如果不良好地进行输入端及输出端之间的分离,则来自输出端的输出信号成为谐振状态,不能够得到希望的输出信号。进而,也有半导体芯片(半导体元件)自身因上述谐振的影响而被破坏的情况。
但是,在将半导体芯片(半导体元件)和无源器件装入到多层布线板上并高密度安装的电子器件中,因为使布线基板间窄小化等,因此设置上述那样的、能够将半导体芯片(半导体元件)的输入端及输出端之间电气分离那样的机构是困难的。
现有技术文献
专利文献
专利文献1:日本特开2001-085803公报
发明内容
发明概要
发明要解决的技术问题
本发明的目的是,在将半导体芯片(半导体元件)及无源器件集成于多层布线板且半导体芯片及无源器件构成反馈电路的电子器件中,能够将半导体芯片(半导体元件)的输入端及输出端之间电气分离。
用于解决技术问题的手段
有关本发明的一技术方案的电子器件,具备:多层布线板;半导体芯片,配置于上述多层布线板的主面上或内部;以及无源器件,配置于上述多层布线板的内部,具有与上述半导体芯片的输入端及输出端分别连接的第1端子及第2端子,构成上述多层布线板的导电性部件配置在使得其距上述第1端子及上述第2端子的至少一方的距离比上述第1端子及第2端子间的距离小的位置上。
发明的效果
根据本发明,在将半导体芯片(半导体元件)及无源器件集成于多层布线板且半导体芯片及无源器件构成反馈电路的电子器件中,能够将半导体芯片(半导体元件)的输入端及输出端之间电气分离。
附图说明
图1是表示有关本发明的第1实施方式的电子器件的剖视图。
图2是表示由图1所示的电子器件的半导体芯片和无源器件构成的电路的一例的电路图。
图3是将图1所示的电子器件的无源器件的附近放大表示的放大立体图。
图4是表示有关本发明的比较例的电子器件的剖视图。
图5是表示将图4所示的电子器件的半导体芯片及无源器件从上方观察的状态的俯视图。
图6是表示图1所示的电子器件的制造工序的图。
图7是表示图1所示的电子器件的制造工序的图。
图8是表示图1所示的电子器件的制造工序的图。
图9是表示图1所示的电子器件的制造工序的图。
图10是表示图1所示的电子器件的制造工序的图。
图11是表示图1所示的电子器件的制造工序的图。
图12是表示图1所示的电子器件的制造工序的图。
图13是表示有关本发明的第2实施方式的电子器件的剖视图。
图14是表示图13所示的电子器件的无源器件附近的俯视图。
图15是表示有关本发明的第3实施方式的电子器件的剖视图。
图16是表示由图1所示的电子器件的半导体芯片和无源器件构成的电路的一例的电路图。
具体实施方式
以下,参照附图详细地说明本发明的实施方式。
(第1实施方式)
图1是表示本发明的第1实施方式的电子器件100的剖视图。电子器件100具有多层布线板110、半导体芯片120、无源器件130、密封层140、及保护层150。
多层布线板110具有绝缘层111~115及布线层L1~L6。布线层L1~L6从下方朝向上方依次配置,分别通过绝缘层111~115而电气绝缘。另外,绝缘层111~115是由树脂等绝缘材料构成的层。此外,布线层L1~L6是具有由金属等导电性材料的图案构成的布线的层。布线层L1~L6间用导电性凸块等层间连接部B1~B5电气连接。
在本实施方式中,例如半导体芯片120由硅等半导体的芯片构成,构成放大器(例如,OP放大器)。此外,在半导体芯片120的上表面左端设有输入端121,在半导体芯片120的上表面右端上设有输出端122。半导体芯片120将输入到输入端121的信号放大,向输出端122输出。另外,输入端121及输出端122分别通过金属线W与多层布线板110的布线层L1内的布线连接。
在本实施方式中,无源器件130设置为在多层布线板110的内部即半导体芯片120的正下方对置。无源器件130的第1端子131及第2端子132分别通过焊料等连接在布线层L2上。结果,无源器件130的第1端子131及第2端子132分别经由布线层L2、层间连接部B1、布线层L1、金属线W连接在半导体芯片120的输入端121、输出端122上,构成反馈电路。
无源器件130是反馈元件,例如是构成电感器、电容器、电阻器等的芯片器件。
假如无源器件130是构成电阻器的芯片器件,则上述反馈电路构成图2所示那样的电路。即,构成将放大器AMP与反馈电阻元件R组合的模拟电路。
密封层140是用于将半导体芯片120密封、从外界进行保护的例如树脂的层。
保护层150是用于从外界进行保护布线层L6的例如抗蚀剂层。在保护层150上形成有开口,形成有用于与外部电路及外部元件电气连接的未图示的金属端子。
图3是将无源器件130的附近放大表示的放大立体图。图3为了使本实施方式的特征变得明确,与图1所示的电子器件相比,将上下倒转表示。
如图3所示,在无源器件130的第1端子131及第2端子132上,连接着构成多层布线板110的导电性部件、即布线层L2的布线L2a、L2b,布线层L4的布线L4a、L4b接近配置。此外,与第1端子131及第2端子132间的距离D2相比,将第1端子131及第2端子132与布线L4a、L4b的距离D1变小。
结果,从无源器件130的第1端子131及第2端子132产生的AC噪声被布线L4a、L4b吸收。因而,能够防止该AC噪声叠加在半导体芯片120上,所以能够进行半导体芯片120的输入端121及输出端122的电气分离。结果,能够防止半导体芯片120的谐振而得到希望的输出信号、并且能够防止半导体芯片120的破坏。
此外,能够将布线L4a、L4b接地。在此情况下,上述的AC噪声被释放到多层布线板即电子器件的外部,所以能够更有效地抑制AC噪声对于半导体芯片120的叠加,能够更可靠地进行半导体芯片120的输入端121及输出端122的电气分离。
另外,在本实施方式中,将布线L4a及布线L4b以距离D1分别相对于无源器件130的第1端子131及第2端子132接近配置,但只要将布线L4a及布线L4b的某一方以距离D1相对于第1端子131或第2端子132接近配置,就能够发挥上述作用效果。但是,如本实施方式所示,如果将布线L4a及布线L4b以距离D1分别相对于第1端子131及第2端子132接近配置,则能够更有效地发挥上述作用效果。
此外,在本实施方式中,无源器件130配置为在多层布线板110的内部且半导体芯片120的正下方对置。因而,无源器件130被位于其下方的布线层L3~L6及位于其上方的半导体芯片120屏蔽,能够减少外部噪声的流入。此外,通过将无源器件130配置在半导体芯片120的正下方,减小无源器件130与半导体芯片120间的布线长,所以能够进一步减小外部噪声对于无源器件130的影响。
另外,在本实施方式中,在多层布线板110中,使布线L4a及布线L4b位于无源器件130的下方,但也可以位于其上方。
(比较例)
图4是表示有关本发明的比较例的电子器件100X的剖视图。图5是表示将半导体芯片120X及无源器件130X从上方观察的状态的俯视图。电子器件100X具有多层布线板110X、半导体芯片120X、无源器件130X、密封层140X、及保护层150X。布线层L1X~L6X从下方朝向上方依次配置,分别通过绝缘层111X~115X电气绝缘。另外,绝缘层111X~115X是由树脂等绝缘材料构成的层。此外,布线层L1X~L6X是具有由金属等导电性材料的图案构成的布线的层。布线层L1X~L6X间通过导电性凸块等层间连接部B1X~B5X电气连接。
如图4及图5所示,在本比较例中,无源器件130X不配置在多层布线板110X的内部,而是在多层布线板110X的主面上与半导体芯片120X并列配置。无源器件130X的第1端子131X及第2端子132X分别连接在布线层L1X的布线L11X及L12X上,半导体芯片120X的输入端121X及输出端122X经由金属线Wx同样连接在布线层L1X的布线L11X及L12X上。
在电子器件100X中,由于在多层布线板110X上配置有半导体芯片120X及无源器件130X,所以必须将无源器件130X与半导体芯片120X充分离开地配置,以使由无源器件130产生的AC噪声不叠加在半导体芯片120X上。因而,难以得到高密度安装的电子器件。
此外,由于无源器件130X露出到表面上,所以该无源器件130X容易受到外部噪声的影响。因而,需要对无源器件130X另外设置屏蔽部件来削减外部噪声的影响。因而,通过设置屏蔽部件,难以得到高密度安装的电子器件,除此之外,设置屏蔽部件的新的制造工序被要求,所以电子器件100X的制造工序复杂化。
(电子器件100的制造方法)
以下,说明电子器件100的制造方法。
在制造电子器件100时,最先制作内置无源器件130的多层布线板110。此时,多层布线板110划分为上层部110A、中层部110B、下层部110C而进行制作。并且,通过将上层部110A、中层部110B、下层部110C合体而制作多层布线板110。
A.上层部110A的制作(图6)
上层部110A具有绝缘层111、布线层L1、L2、无源器件130。
(1)向金属箔21形成导电性凸块22(图6(a))
在作为布线层L1的金属箔(例如铜箔)21上,形成作为层间连接部B1的导电性凸块22。导电性凸块22例如可以通过导电性膏的丝网印刷而形成。导电性膏例如是使金属粒(银、金、铜、焊料等)分散到膏状树脂中、混合挥发性的溶剂而得到的物质。将导电性膏通过丝网印刷而印刷到金属箔21上,能够形成大致圆锥形的导电性凸块22。
(2)向金属箔21层叠预成型料(pre-preg)23(图6(b))
在形成有导电性凸块22的金属箔21上,层叠要做成绝缘层111的预成型料23。即,在金属箔21上配置预成型料23并加压。预成型料23例如是使环氧树脂那样的固化性树脂含浸到玻璃纤维那样的加强体中而成的。此外,在固化前处于半固化状态,具有热塑性及热固化性。在该层叠的阶段中,由于不加热,所以预成型料23被保持为未固化状态。
层叠的结果是,导电性凸块22将预成型料23贯通。这是因为,预成型料23具有热塑性、热固化性,以及导电性凸块22的形状是大致圆锥。
(3)金属箔21、预成型料23、金属箔24的层叠、加热(图6(c))在金属箔21、预成型料23的层叠体上层叠金属箔24,在加压的状态下加热。结果,预成型料23固化而成为绝缘层111,与金属箔21、24牢固地连接。此外,导电性凸块22(层间连接部B1)将金属箔21、24电气连接。
金属箔21、24的电气导通由导电性凸块22进行,不需要通孔形成等的工序。因此,不需要用于通孔形成的空间,高密度的安装较容易。
(4)金属箔21、24的图案化(图6(d))
金属箔21、24被图案化,形成布线层L1、L2。图案化例如可以通过由光致抗蚀剂的涂敷、基于曝光的掩模的形成、和通过该掩模的金属箔21、24的蚀刻等来执行。
(5)无源器件130的安装(图6(e))
在布线层L2上配置并固定无源器件130。
B.中层部110B的制作(图7)
中层部110B对应于绝缘层112、一部分绝缘层113、布线层L3。
(1)向金属箔31形成导电性凸块32(图7(a))
接着,在作为层间连接部B3的一部分的金属箔(例如铜箔)31上,形成作为层间连接部B3的一部分的导电性凸块32。
(2)向金属箔31层叠预成型料33(图7(b))
在形成有导电性凸块32的金属箔31上,层叠要作为绝缘层113的一部分的预成型料33。即,在金属箔31上配置预成型料23并加压。层叠的结果是,导电性凸块32将预成型料33贯通。
(3)金属箔31、预成型料33、金属箔34的层叠、加热(图7(c))
在金属箔31、预成型料33的层叠体上层叠金属箔34,在加压的状态下加热。结果,预成型料33固化而成为绝缘层33A,与金属箔31、34牢固地连接。此外,导电性凸块32(层间连接部B3的一部分)将金属箔31、34电气连接。绝缘层33A及后述的预成型料49对应于绝缘层113。
(4)金属箔31、34的图案化(图7(d))
金属箔31、34被图案,形成金属箔图案31A及布线层L3。金属箔图案31A、导电性凸块32及后述的导电性凸块48对应于层间连接部B3。
(5)向布线层L3形成导电性凸块35(图7(e))
在布线层L3上,形成作为层间连接部B2的导电性凸块35。
(6)向布线层L3层叠预成型料36(图7(f))
在布线层L3上,层叠要作为绝缘层112的预成型料36。即,在金属箔31上配置预成型料36并加压。层叠的结果是,导电性凸块35将预成型料36贯通。在该层叠的阶段中,由于不加热,所以预成型料36被保持为未固化状态。
(7)贯通孔37的形成(图7(g))
在金属箔31、预成型料33、金属箔34、预成型料36的层叠体上形成贯通孔37。该贯通孔37成为用于收容无源器件130的空间。在无源器件130为某种程度较厚的情况下,需要这样的贯通孔37。
通过以上,形成中层部110B。此时,预成型料36为与之后的上层部110A的连接准备,是未固化的状态。该中层部110B具有作为层间连接部B3的一部分的金属箔图案31A、导电性凸块32。在该例中,在预成型料36和布线层L3之下,配置有绝缘层33A、导电性凸块32、金属箔图案31A的组合。根据情况,可以进一步层叠该组合。
C.下层部110C的制作(图8)
下层部110C具有绝缘层114、115、布线层L4~L5。
(1)布线层L6、绝缘层115、布线层L5的层叠体的形成(图8(a))
通过以下的工序,形成布线层L6、绝缘层115、布线层L5的层叠体。
1)向金属箔41(对应于布线层L6)形成导电性凸块42(对应于层间连接部B5)
2)预成型料43的层叠
3)金属箔44的层叠、加热
4)金属箔41、44的图案化
该工序1)~4)与对应于已述的图6(a)~(d)及图7(a)~(d)的工序是同样的,所以省略详细的说明。
(2)向布线层L5形成导电性凸块45(图8(b))
在布线层L5上,形成作为层间连接部B4的导电性凸块45。
(3)向布线层L5层叠预成型料46(图8(c))
在形成有导电性凸块45的布线层L5上,层叠要作为绝缘层114的预成型料46。即,在布线层L5上配置预成型料46并加压。层叠的结果是,导电性凸块45将预成型料46贯通。
(4)金属箔47的层叠、加热(图8(d))
在预成型料46上层叠金属箔47,在加压的状态下加热。结果,预成型料46固化,成为绝缘层114,与布线层L5、金属箔47牢固地连接。此外,导电性凸块45(层间连接部B4)将布线层L5、金属箔47电气连接。
(5)金属箔47的图案化(图8(e))
金属箔47被图案化,形成布线层L4。
(6)向布线层L4形成导电性凸块48(图8(f))
在布线层L4上,形成作为层间连接部B3的一部分的导电性凸块48。
(7)向布线层L4层叠预成型料49(图8(g))
在形成有导电性凸块48的布线层L4上,层叠要作为绝缘层113的一部分的预成型料49。即,在布线层L4上配置预成型料49并加压。层叠的结果是,导电性凸块48将预成型料49贯通。
通过以上,形成下层部110C。此时,预成型料49为与之后的中层部110B的连接准备,是未固化的状态。该下层部110C具有作为层间连接部B3的一部分的导电性凸块48。
D.上层部110A、中层部110B、下层部110C的接合(图9、图10)
将上层部110A、中层部110B、下层部110C接合。即,将上层部110A、中层部110B、下层部110C层叠,在施加压力的状态下加热。此时,上层部110A与图6的状态上下相反地配置。
通过预成型料36、49固化,上层部110A、中层部110B、下层部110C接合。此时,无源器件130被收容、密封到贯通孔37内。此外,将导电性凸块48、金属箔图案31A、导电性凸块32连接,形成层间连接部B3。将预成型料49与绝缘层33A连接,形成绝缘层113。如以上这样,形成内置无源器件130的多层布线板110。
E.半导体芯片120的固定、密封(图11、图12)
在多层布线板110上固定半导体芯片120,用金属线W与多层布线板110电气连接。进而,用密封层140将半导体芯片120密封,用保护层150对多层布线板110的下表面进行保护。
如以上这样,形成内置作为反馈元件的无源器件130(例如,调整用的电阻元件)的电子器件100。
(第2实施方式)
图13是表示本发明的第2实施方式的电子器件200的剖视图,图14是表示图13所示的电子器件200的无源器件230附近的俯视图。
电子器件200与第1实施方式的电子器件100同样,具有多层布线板210、半导体芯片220、无源器件230、密封层240及保护层250。
多层布线板210具有绝缘层211~215及布线层L21~L26。布线层L21~L26从下方朝向上方依次配置,分别通过绝缘层211~215电气绝缘。另外,绝缘层211~215是由树脂等绝缘材料构成的层。此外,布线层L21~L26是具有由金属等导电性材料的图案构成的布线的层。布线层L21~L26间用导电性凸块等层间连接部B21~B25电气连接。
在本实施方式中,例如半导体芯片220由硅等半导体的芯片构成,构成放大器(例如,OP放大器)。此外,在半导体芯片220的上表面左端设有输入端221,在半导体芯片220的上表面右端上设有输出端222。半导体芯片220将输入到输入端221的信号放大,向输出端222输出。另外,输入端221及输出端222分别通过金属线W连接在多层布线板210的布线层L21内的布线上。
在本实施方式中,无源器件230设置为在多层布线板210的内部即半导体芯片220的正下方对置。无源器件230的第1端子231及第2端子232分别用焊料等连接在布线层L22上。结果,无源器件230的第1端子231及第2端子232分别经由布线层L22、层间连接部B21、布线层L21、金属线W连接在半导体芯片220的输入端221、输出端222上,构成反馈电路。
无源器件230是反馈元件,例如是构成电感器、电容器、电阻器等的芯片器件。
密封层240是用于将半导体芯片220密封、从外界进行保护的例如树脂的层。
保护层250是用于将布线层L26从外界进行保护的例如抗蚀剂层。在保护层250上形成有开口,形成有用于与外部电路及外部元件电气连接的未图示的金属端子。
如图13及图14所示,在无源器件230的第1端子231及第2端子232上,连接着构成多层布线板210的导电性部件、即布线层L22的布线L22a、L22b,接近配置有层间连接部B23。此外,与第1端子231及第2端子232间的距离D2相比,将第1端子231及第2端子232与层间连接部B23的距离D3变小。
结果,从无源器件230的第1端子231及第2端子232产生的AC噪声被层间连接部B23吸收。因而,能够防止该AC噪声叠加在半导体芯片220上,所以能够进行半导体芯片220的输入端221及输出端222的电气分离。结果,能够防止半导体芯片220的谐振而得到希望的输出信号,并且能够防止半导体芯片220的破坏。
此外,层间连接部B23可以接地。在此情况下,上述AC噪声被释放到多层布线板、即电子器件的外部,所以能够更有效地抑制AC噪声对于半导体芯片220的叠加,能够更可靠地进行半导体芯片220的输入端221及输出端222的电气分离。
另外,在本实施方式中,将层间连接部B23以距离D3分别相对于无源器件230的第1端子231及第2端子232接近配置,但只要将某一方的层间连接部B23相对于第1端子231或第2端子232以距离D3接近配置,就能够发挥上述作用效果。但是,如本实施方式所示,如果将层间连接部B23分别相对于第1端子231及第2端子232以距离D3接近配置,则能够更有效地发挥上述作用效果。
此外,在本实施方式中,无源器件230配置为在多层布线板210的内部且半导体芯片220的正下方对置。因而,无源器件230被位于其下方的布线层L23~L26及位于其上方的半导体芯片220屏蔽,能够减少外部噪声的流入。此外,通过将无源器件230配置在半导体芯片220的正下方,减小无源器件230与半导体芯片220间的布线长,所以能够进一步降低外部噪声对于无源器件230的影响。
(第3实施方式)
图15是表示本发明的第3实施方式的电子器件300的剖视图。电子器件300具有多层布线板310、半导体芯片320、无源器件330a~330d、保护层350a、350b。
多层布线板310具有绝缘层311~315及布线层L31~L36。布线层L31~L36从下方朝向上方依次配置,分别通过绝缘层311~315电气绝缘。另外,绝缘层311~315是由树脂等绝缘材料构成的层。此外,布线层L31~L36是具有由金属等导电性材料的图案构成的布线的层。布线层L31~L36间用导电性凸块等层间连接部B31~B35电气连接。
半导体芯片320由硅等半导体的芯片构成,与无源器件330a、330b一起配置在多层布线板310的内部中。作为半导体芯片320,例如可以使用CSP(芯片尺寸封装,ChipSizePackage)。即,能够使用以与半导体芯片自身相同程度的尺寸实现的超小型的封装,作为半导体芯片320。
另外,也可以在多层布线板310的主面上配置别的半导体芯片,用树脂等密封。即,可以将半导体芯片配置于多层布线板310的主面上及内部这两者上。
在本实施方式中,例如半导体芯片320由硅等半导体的芯片构成,构成放大器(例如,OP放大器)。此外,在半导体芯片320的上表面左端设有输入端321,在半导体芯片320的上表面右端设有输出端322。输入端321、输出端322分别通过焊料等连接于布线层L32。半导体芯片320将输入到输入端321中的信号放大,向输出端322输出。
无源器件330a~330d是构成电感器、电容器、电阻器等的芯片器件。无源器件330a、330b与半导体芯片320并列配置在多层布线板310的内部中,通过焊料等连接在布线层L32内的布线上。其中,无源器件330b配置在比截面靠后方,所以用虚线表示。无源器件330c、330d配置在多层布线板310的主面上,通过焊料等连接在布线层L31上。
假如无源器件330a~330d都为电阻,则半导体芯片320和无源器件330a~330d构成与图16所示的反馈电路等价的电路。
在保护层350a、350b上形成有开口,形成有用于与外部电路及外部元件电气连接的未图示的金属端子。
如图15所示,无源器件330a的第1端子331a及第2端子332a、以及无源器件330b的未图示的端子,与构成多层布线板310的导电性部件即布线层L32连接,布线层L35的布线L35a相对于这些端子接近配置。此外,与无源器件330a的第1端子331a及第2端子332a间的距离D2、以及无源器件330b的未图示的端子间的距离相比,将这些端子与布线L35a的距离D4变小。
结果,从无源器件330a的第1端子331a及第2端子332a发生的AC噪声、以及从无源器件330b的未图示的端子发生的AC噪声被布线L35a吸收。因而,能够防止该AC噪声叠加到半导体芯片320上,所以能够进行半导体芯片320的输入端321及输出端322的电气分离。结果,能够防止半导体芯片320的谐振而得到希望的输出信号,并且能够防止半导体芯片320的破坏。
此外,布线L35a能够接地。在此情况下,由于上述AC噪声被释放到多层布线板310、即电子器件300的外部,所以能够更有效地抑制AC噪声对于半导体芯片320的叠加,能够更可靠地进行半导体芯片320的输入端321及输出端322的电气分离。
此外,在本实施方式中,无源器件330a及330b被配置在多层布线板310的内部。因而,这些无源器件330a及330b被多层布线板310的布线层L31~L36屏蔽,能够减少外部噪声的流入。
以上,基于上述具体例对本发明详细地进行了说明,但本发明并不限定于上述具体例,在不脱离本发明的范畴内能够进行各种变形及变更。
标号说明
100、200、300电子器件
110、210、310多层布线板
111~115、211~215、311~315绝缘层
L1~L6、L21~L25、L31~L35布线层
L2a、L2b、L4a、L4b、L22a、L22b、L35a布线
120、220、330半导体芯片
121、221、321输入端
122、222、322输出端
130、230、330a~330d无源器件
131、231、331a第1端子
132、232、332a第2端子
140、240、350密封层
150、250、350a、350b保护层
Claims (8)
1.一种电子器件,其特征在于,
具备:
多层布线板;
半导体芯片,配置于上述多层布线板的主面上或内部;以及
无源器件,配置于构成上述多层布线板的绝缘层的内部,具有与上述半导体芯片的输入端及输出端分别连接的第1端子及第2端子,
构成上述多层布线板的导电性部件配置在使得其距上述第1端子及上述第2端子的至少一方的距离比上述第1端子及第2端子间的距离小的位置上,
上述导电性部件与上述第1端子和上述第2端子隔开间隔配置。
2.如权利要求1所述的电子器件,其特征在于,
构成上述多层布线板的导电性部件配置在使得其距上述第1端子及上述第2端子的距离比上述第1端子及第2端子间的距离小的位置上。
3.如权利要求1或2所述的电子器件,其特征在于,
上述导电性部件接地。
4.如权利要求1或2所述的电子器件,其特征在于,
上述导电性部件是构成上述多层布线板的布线层。
5.如权利要求1或2所述的电子器件,其特征在于,
上述导电性部件是构成上述多层布线板的层间连接部。
6.如权利要求1或2所述的电子器件,其特征在于,
上述无源器件和上述半导体芯片相互对置地配置。
7.如权利要求1或2所述的电子器件,其特征在于,
上述无源器件是相对于上述半导体芯片的反馈元件。
8.如权利要求1或2所述的电子器件,其特征在于,
上述无源器件是从电感器、电容器及电阻器中选择的至少1个。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010003255 | 2010-01-08 | ||
JP2010-003255 | 2010-01-08 | ||
JP2010-278004 | 2010-12-14 | ||
JP2010278004A JP5136632B2 (ja) | 2010-01-08 | 2010-12-14 | 電子部品 |
PCT/JP2011/000002 WO2011083753A1 (ja) | 2010-01-08 | 2011-01-04 | 電子部品 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102726129A CN102726129A (zh) | 2012-10-10 |
CN102726129B true CN102726129B (zh) | 2016-03-30 |
Family
ID=44305489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201180005515.5A Active CN102726129B (zh) | 2010-01-08 | 2011-01-04 | 电子器件 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9066422B2 (zh) |
JP (1) | JP5136632B2 (zh) |
KR (1) | KR20120101591A (zh) |
CN (1) | CN102726129B (zh) |
TW (1) | TWI500365B (zh) |
WO (1) | WO2011083753A1 (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2502934B (en) | 2011-04-04 | 2015-08-12 | Murata Manufacturing Co | Chip component-embedded resin multilayer substrate and manufacturing method thereof |
JP2013045899A (ja) * | 2011-08-24 | 2013-03-04 | Dainippon Printing Co Ltd | 素子内蔵配線基板、及びその製造方法 |
WO2013054808A1 (ja) * | 2011-10-14 | 2013-04-18 | 株式会社村田製作所 | 多層基板および多層基板を備えるモジュール |
CN104106320B (zh) * | 2012-02-17 | 2017-04-19 | 株式会社村田制作所 | 元器件内置基板 |
WO2013121977A1 (ja) * | 2012-02-17 | 2013-08-22 | 株式会社村田製作所 | 部品内蔵基板 |
TWI522016B (zh) | 2014-07-02 | 2016-02-11 | 啟碁科技股份有限公司 | 降低聲噪的電路板裝置和電路裝置 |
CN105282958B (zh) * | 2014-07-07 | 2018-01-09 | 启碁科技股份有限公司 | 降低声噪的电路板装置和用以降低声噪的电路装置 |
TWI562687B (en) * | 2014-09-24 | 2016-12-11 | Wistron Corp | Circuit board assembly |
WO2016047446A1 (ja) * | 2014-09-26 | 2016-03-31 | 株式会社村田製作所 | 積層モジュール用基板、積層モジュールおよび積層モジュールの製造方法 |
US10433424B2 (en) * | 2014-10-16 | 2019-10-01 | Cyntec Co., Ltd | Electronic module and the fabrication method thereof |
CN109560183B (zh) * | 2015-04-29 | 2020-04-17 | 光宝光电(常州)有限公司 | 多层式电路板及发光二极管封装结构 |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
US10103069B2 (en) | 2016-04-01 | 2018-10-16 | X-Celeprint Limited | Pressure-activated electrical interconnection by micro-transfer printing |
US10222698B2 (en) | 2016-07-28 | 2019-03-05 | X-Celeprint Limited | Chiplets with wicking posts |
US11064609B2 (en) | 2016-08-04 | 2021-07-13 | X Display Company Technology Limited | Printable 3D electronic structure |
KR102565119B1 (ko) * | 2016-08-25 | 2023-08-08 | 삼성전기주식회사 | 전자 소자 내장 기판과 그 제조 방법 및 전자 소자 모듈 |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
KR102624986B1 (ko) * | 2018-12-14 | 2024-01-15 | 삼성전자주식회사 | 반도체 패키지 |
WO2021020331A1 (ja) * | 2019-08-01 | 2021-02-04 | 株式会社村田製作所 | モジュール |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1956183A (zh) * | 2005-10-27 | 2007-05-02 | 新光电气工业株式会社 | 电子部件内置式基板及其制造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001085803A (ja) * | 1999-09-14 | 2001-03-30 | Hitachi Ltd | 配線基板および電力制御装置 |
TW511415B (en) * | 2001-01-19 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Component built-in module and its manufacturing method |
JP4697828B2 (ja) * | 2001-03-13 | 2011-06-08 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
TW503496B (en) * | 2001-12-31 | 2002-09-21 | Megic Corp | Chip packaging structure and manufacturing process of the same |
US7038142B2 (en) * | 2002-01-24 | 2006-05-02 | Fujitsu Limited | Circuit board and method for fabricating the same, and electronic device |
JP4137659B2 (ja) * | 2003-02-13 | 2008-08-20 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
US7394663B2 (en) * | 2003-02-18 | 2008-07-01 | Matsushita Electric Industrial Co., Ltd. | Electronic component built-in module and method of manufacturing the same |
EP1601017A4 (en) * | 2003-02-26 | 2009-04-29 | Ibiden Co Ltd | MULTILAYER PRINTED PCB |
US7327554B2 (en) * | 2003-03-19 | 2008-02-05 | Ngk Spark Plug Co., Ltd. | Assembly of semiconductor device, interposer and substrate |
JP4387231B2 (ja) | 2004-03-31 | 2009-12-16 | 新光電気工業株式会社 | キャパシタ実装配線基板及びその製造方法 |
JP4513389B2 (ja) * | 2004-04-09 | 2010-07-28 | 株式会社村田製作所 | 多層配線基板及びその製造方法 |
WO2006035528A1 (ja) * | 2004-09-29 | 2006-04-06 | Murata Manufacturing Co., Ltd. | スタックモジュール及びその製造方法 |
JPWO2007069606A1 (ja) * | 2005-12-14 | 2009-05-21 | 新光電気工業株式会社 | チップ内蔵基板の製造方法 |
KR100656300B1 (ko) * | 2005-12-29 | 2006-12-11 | (주)웨이브닉스이에스피 | 3차원 알루미늄 패키지 모듈, 그의 제조방법 및 3차원알루미늄 패키지 모듈에 적용되는 수동소자 제작방법 |
JP2008283114A (ja) | 2007-05-14 | 2008-11-20 | Dainippon Printing Co Ltd | 電子部品実装配線板、及び電子部品実装配線板の電磁ノイズ除去方法 |
TWI338941B (en) * | 2007-08-22 | 2011-03-11 | Unimicron Technology Corp | Semiconductor package structure |
KR101194842B1 (ko) * | 2007-09-06 | 2012-10-25 | 삼성전자주식회사 | 반도체 패키지가 삽입된 인쇄회로기판 |
US8193624B1 (en) * | 2008-02-25 | 2012-06-05 | Amkor Technology, Inc. | Semiconductor device having improved contact interface reliability and method therefor |
JP2009246144A (ja) | 2008-03-31 | 2009-10-22 | Panasonic Corp | 電子部品内蔵基板及びその製造方法とこれを用いた半導体装置 |
JP5535494B2 (ja) * | 2009-02-23 | 2014-07-02 | 新光電気工業株式会社 | 半導体装置 |
JP5106460B2 (ja) * | 2009-03-26 | 2012-12-26 | 新光電気工業株式会社 | 半導体装置及びその製造方法、並びに電子装置 |
US8405229B2 (en) * | 2009-11-30 | 2013-03-26 | Endicott Interconnect Technologies, Inc. | Electronic package including high density interposer and circuitized substrate assembly utilizing same |
-
2010
- 2010-12-14 JP JP2010278004A patent/JP5136632B2/ja active Active
-
2011
- 2011-01-04 KR KR1020127020700A patent/KR20120101591A/ko not_active Application Discontinuation
- 2011-01-04 US US13/520,980 patent/US9066422B2/en active Active
- 2011-01-04 WO PCT/JP2011/000002 patent/WO2011083753A1/ja active Application Filing
- 2011-01-04 CN CN201180005515.5A patent/CN102726129B/zh active Active
- 2011-01-07 TW TW100100641A patent/TWI500365B/zh active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1956183A (zh) * | 2005-10-27 | 2007-05-02 | 新光电气工业株式会社 | 电子部件内置式基板及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201141329A (en) | 2011-11-16 |
KR20120101591A (ko) | 2012-09-13 |
WO2011083753A1 (ja) | 2011-07-14 |
US20120281379A1 (en) | 2012-11-08 |
JP2011159961A (ja) | 2011-08-18 |
CN102726129A (zh) | 2012-10-10 |
JP5136632B2 (ja) | 2013-02-06 |
US9066422B2 (en) | 2015-06-23 |
TWI500365B (zh) | 2015-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102726129B (zh) | 电子器件 | |
KR100753499B1 (ko) | 전자 부품 및 그 제조 방법 | |
US8476535B2 (en) | Multilayered printed wiring board and method for manufacturing the same | |
US7849591B2 (en) | Method of manufacturing a printed wiring board | |
JP2005517287A (ja) | 構成要素をベースに埋め込み接触を形成する方法 | |
KR20010108329A (ko) | 높은 양호도의 반응성 소자를 구비하는 집적 회로를 위한장치 및 방법 | |
CN105228341A (zh) | 印刷电路板、封装基板及其制造方法 | |
WO2006011320A1 (ja) | 複合型電子部品及びその製造方法 | |
KR102194721B1 (ko) | 인쇄회로기판 및 그 제조 방법 | |
JP2015032729A (ja) | 電子部品内蔵多層配線基板及びその製造方法 | |
KR20160066311A (ko) | 반도체 패키지 및 반도체 패키지의 제조방법 | |
WO2005122247A1 (ja) | 複合型電子部品 | |
US20230354512A1 (en) | Printed circuit board with integrated fusing and arc suppression | |
JP2006324568A (ja) | 多層モジュールとその製造方法 | |
CN108024441B (zh) | 布线基板以及使用了该布线基板的电子装置 | |
KR20150002492A (ko) | 배선 기판 | |
US7968800B2 (en) | Passive component incorporating interposer | |
KR20090049683A (ko) | 이형재를 이용한 임베디드 반도체 패키지 장치 및 그 제조 방법 | |
JP2005235807A (ja) | 積層型電子部品およびその製造方法 | |
JP6068167B2 (ja) | 配線基板およびその製造方法 | |
JP5823225B2 (ja) | 配線基板 | |
JP2006344631A (ja) | 部品内蔵基板 | |
US10720338B1 (en) | Low temperature cofired ceramic substrates and fabrication techniques for the same | |
CN101316479B (zh) | 电路板及其制作方法 | |
JPH10215049A (ja) | チップ・オン・ボード実装構造およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |