JPH0837190A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0837190A
JPH0837190A JP6170612A JP17061294A JPH0837190A JP H0837190 A JPH0837190 A JP H0837190A JP 6170612 A JP6170612 A JP 6170612A JP 17061294 A JP17061294 A JP 17061294A JP H0837190 A JPH0837190 A JP H0837190A
Authority
JP
Japan
Prior art keywords
film
bump
semiconductor device
electrode pad
gel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6170612A
Other languages
English (en)
Inventor
Teruo Kusaka
輝雄 日下
Naoharu Senba
直治 仙波
Atsushi Nishizawa
厚 西沢
Nobuaki Takahashi
信明 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6170612A priority Critical patent/JPH0837190A/ja
Priority to US08/505,152 priority patent/US5600180A/en
Priority to KR1019950021795A priority patent/KR0163782B1/ko
Publication of JPH0837190A publication Critical patent/JPH0837190A/ja
Pending legal-status Critical Current

Links

Classifications

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    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Abstract

(57)【要約】 【目的】実装時の雰囲気による汚染や酸化を防止できる
半導体装置を提供する。 【構成】ＩＣチップ１の上に形成した電極パッド２と接
続して形成したバンプ７を含む表面にゲル状のシール膜
８を形成してバンプ７の頭部上に薄いシール膜８を存在
させるようにバンプを埋込む。実装時にはバンプ７を回
路基板上の電極パッドに押し付けシール膜８を周囲に押
し出しながら接合することで雰囲気に触れることなく接
合できる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置に関し、特に
高密度実装用のＩＣパッケージに関する。
【０００２】
【従来の技術】半導体装置の高密度実装の一つとしてフ
リップチップ方式がある。
【０００３】図４は従来の半導体装置の一例を示す断面
図である。
【０００４】図４に示すように、半導体素子を形成した
ＩＣチップ１の上に形成した電極パッド２と、電極パッ
ド２を含む表面に形成した絶縁膜９と、絶縁膜９に形成
した開孔部を含む表面に形成した金属膜５をめっき電極
として金属膜５の上に形成した半田からなるバンプ７を
有しており、図４に示すように、回路基板１１の電極パ
ッド１２にバンプ７をリフローして接合した後、ＩＣチ
ップ１と回路基板１１との間隙にエポキシ系樹脂膜１３
を注入して封止していた。
【０００５】
【発明が解決しようとする課題】この従来の半導体装置
は、バンプの表面が露出しているため雰囲気により汚染
されたり、酸化されたりして実装時にコンタクト不良を
生ずるという問題があった。
【０００６】本発明の目的は、汚染や酸化を防止して実
装時の良好なコンタクトを実現できる半導体装置を提供
することにある。
【０００７】
【課題を解決するための手段】本発明の半導体装置は、
半導体素子を形成したＩＣチップの上に形成した電極パ
ッドと、前記電極パッドを含む表面に形成した絶縁膜
と、前記絶縁膜に形成して前記電極パッドの表面を露出
させた開孔部と、前記開孔部の前記電極パッドと接続し
て形成したバンプと、前記バンプを含む表面に形成して
前記バンプの頭部上に薄い膜を有するように前記バンプ
を埋込んだゲル状の絶縁性シール膜とを備えている。
【０００８】
【実施例】次に、本発明について図面を参照して説明す
る。
【０００９】図１（ａ），（ｂ）および図２は本発明の
一実施例の製造方法を説明するための工程順に示した断
面図である。
【００１０】まず、図１（ａ）に示すように、半導体素
子を形成したＩＣ（半導体集積回路）チップ１の上にＡ
ｌ膜等からなり１００μｍ平方程度の寸法と１５０μｍ
程度のピッチで配置された電極パッド２を形成し、電極
パッド２を含む表面に厚さ数μｍのポリイミド膜等から
なる有機絶縁膜３を形成する。次に、電極パッド２の上
の有機絶縁膜３を選択的にエッチングして３０〜８０μ
ｍ平方の第１の開孔部４を形成して電極パッド２の表面
を露出させ、この開孔部４を含む表面に厚さ０．１〜
２．０μｍのＣｒ／Ｃｕ積層金属膜５を形成する。
【００１１】次に、図１（ｂ）に示すように、金属膜５
の上にフォトレジスト膜６を２〜１５μｍの厚さに塗布
してフォトリソグラフィ技術によりパターニングし開孔
部４を含み且つ開孔部４よりも口径の大きい第２の開孔
部を形成する。次に、金属膜５を電流経路として第２の
開孔部の金属膜５の上にＰｂ−Ｓｎ半田膜を電気めっき
し、厚さ２０μｍ程度のマッシュルーム形のバンプ７を
形成する。なお、フォトレジスト膜６の厚さを更に厚く
して電気めっきのＰｎ−Ｓｎ半田膜の上面をフォトレジ
スト膜６の上面以下にとどめたストレート形と呼ばれる
柱状のバンプを形成しても良い。
【００１２】次に、図２に示すように、フォトレジスト
膜を除去した後、バンプ７をマスクとして金属膜５をウ
ェットエッチングして除去する。次に、バンプ７を含む
表面にゲルタイプのシリコーン（例えば、東レ・ダウコ
ーニング社 ＪＣＲ ６１１０あるいは ＳＥ １８８
０）等からなる粘度１０００〜２０００ｃＰのシール膜
８を形成してバンプ７の頭部上に薄いシール膜８を有す
る状態でバンプ７を埋め込み、表面をほぼ平坦化する。
【００１３】図３は本発明により形成した半導体装置の
実装方法を説明するための断面図である。
【００１４】図３に示すように、回路基板１１に形成し
た電極パッド１２に本発明で形成した半導体装置のバン
プ７を位置合わせして上部より圧力を加えバンプ７の頭
部に形成したシール膜８の薄い膜をバンプ７と電極パッ
ド１２で圧接して周囲に押し出しバンプ７をリフローさ
せて電極パッド１２に接合する。
【００１５】
【発明の効果】以上説明したように本発明は、バンプを
形成したＩＣチップのバンプを含む表面にゲル状のシー
ル膜を形成してバンプの頭部の上に薄いシール膜が存在
するようにバンプを埋没させて形成することにより、Ｉ
Ｃチップおよびバンプが運搬や保管時にも外気に晒され
ることがなく、また、実装時にも雰囲気に触れることな
く接合できるため、コンタクト不良を低減して信頼性を
向上できるという効果を有する。
【図面の簡単な説明】
【図１】本発明の一実施例の製造方法を説明するための
工程順に示した断面図。
【図２】本発明の一実施例の製造方法を説明するための
工程順に示した断面図。
【図３】本発明により形成した半導体装置の実装方法を
説明するための断面図。
【図４】従来の半導体装置の一例を示す断面図。
【図５】従来の半導体装置の実装方法を説明するための
断面図。
【符号の説明】 １ ＩＣチップ ２，１２ 電極パッド ３ 有機絶縁膜 ４ 開孔部 ５ 金属膜 ６ フォトレジスト膜 ７ バンプ ８ シール膜 ９ 絶縁膜 １１ 回路基板 １３ エポキシ系樹脂膜
フロントページの続き (72)発明者 高橋 信明 東京都港区芝五丁目７番１号 日本電気株 式会社内

Claims (3)

    【特許請求の範囲】
  1. 【請求項１】 半導体素子を形成したＩＣチップの上に
    形成した電極パッドと、前記電極パッドを含む表面に形
    成した絶縁膜と、前記絶縁膜に形成して前記電極パッド
    の表面を露出させた開孔部と、前記開孔部の前記電極パ
    ッドと接続して形成したバンプと、前記バンプを含む表
    面に形成して前記バンプの頭部上に薄い膜を有するよう
    に前記バンプを埋込んだゲル状の絶縁性シール膜とを備
    えたことを特徴とする半導体装置。
  2. 【請求項２】 ゲル状絶縁性シール膜がゲルタイプのシ
    リコーンからなる請求項１記載の半導体装置。
  3. 【請求項３】 ゲル状絶縁性シール膜の粘度が１０００
    〜２０００ｃＰである請求項２記載の半導体装置。
JP6170612A 1994-07-22 1994-07-22 半導体装置 Pending JPH0837190A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6170612A JPH0837190A (ja) 1994-07-22 1994-07-22 半導体装置
US08/505,152 US5600180A (en) 1994-07-22 1995-07-21 Sealing structure for bumps on a semiconductor integrated circuit chip
KR1019950021795A KR0163782B1 (ko) 1994-07-22 1995-07-22 반도체 집적 회로 칩상의 범프용 실링구조

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6170612A JPH0837190A (ja) 1994-07-22 1994-07-22 半導体装置

Publications (1)

Publication Number Publication Date
JPH0837190A true JPH0837190A (ja) 1996-02-06

Family

ID=15908094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6170612A Pending JPH0837190A (ja) 1994-07-22 1994-07-22 半導体装置

Country Status (3)

Country Link
US (1) US5600180A (ja)
JP (1) JPH0837190A (ja)
KR (1) KR0163782B1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323542B1 (en) 1997-01-17 2001-11-27 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19512725C1 (de) * 1995-04-05 1996-09-12 Orga Kartensysteme Gmbh Ausweiskarte o.dgl. in Form einer Chipkarte
CN1123067C (zh) * 1995-05-22 2003-10-01 日立化成工业株式会社 具有与布线基板电连接的半导体芯片的半导体器件
JPH0997791A (ja) * 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
JP3310499B2 (ja) * 1995-08-01 2002-08-05 富士通株式会社 半導体装置
US5736790A (en) * 1995-09-21 1998-04-07 Kabushiki Kaisha Toshiba Semiconductor chip, package and semiconductor device
KR100438256B1 (ko) * 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
US5869869A (en) * 1996-01-31 1999-02-09 Lsi Logic Corporation Microelectronic device with thin film electrostatic discharge protection structure
JP3376203B2 (ja) 1996-02-28 2003-02-10 株式会社東芝 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法
JP3080579B2 (ja) * 1996-03-06 2000-08-28 富士機工電子株式会社 エアリア・グリッド・アレイ・パッケージの製造方法
US5891795A (en) * 1996-03-18 1999-04-06 Motorola, Inc. High density interconnect substrate
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
KR100186333B1 (ko) * 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JP2825083B2 (ja) * 1996-08-20 1998-11-18 日本電気株式会社 半導体素子の実装構造
KR100239695B1 (ko) 1996-09-11 2000-01-15 김영환 칩 사이즈 반도체 패키지 및 그 제조 방법
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP3960560B2 (ja) * 1996-09-27 2007-08-15 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 回路素子と伝送線路とを有する装置
KR100278561B1 (ko) * 1996-10-15 2001-02-01 포만 제프리 엘 테이퍼를구비하며에칭성이감소된다층의금속샌드위치구조및그형성방법
US6002172A (en) * 1997-03-12 1999-12-14 International Business Machines Corporation Substrate structure and method for improving attachment reliability of semiconductor chips and modules
JPH10303252A (ja) * 1997-04-28 1998-11-13 Nec Kansai Ltd 半導体装置
JPH10335567A (ja) * 1997-05-30 1998-12-18 Mitsubishi Electric Corp 半導体集積回路装置
US6245594B1 (en) * 1997-08-05 2001-06-12 Micron Technology, Inc. Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly
JP3846094B2 (ja) * 1998-03-17 2006-11-15 株式会社デンソー 半導体装置の製造方法
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6168972B1 (en) 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
JP2000311921A (ja) * 1999-04-27 2000-11-07 Sony Corp 半導体装置およびその製造方法
US6861345B2 (en) * 1999-08-27 2005-03-01 Micron Technology, Inc. Method of disposing conductive bumps onto a semiconductor device
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
JP3700563B2 (ja) * 2000-09-04 2005-09-28 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
JP2002118199A (ja) * 2000-10-10 2002-04-19 Mitsubishi Electric Corp 半導体装置
DE10059765A1 (de) * 2000-11-30 2002-06-06 Koninkl Philips Electronics Nv Baugruppe mit Verbindungsstruktur
US6543674B2 (en) 2001-02-06 2003-04-08 Fujitsu Limited Multilayer interconnection and method
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6787443B1 (en) * 2003-05-20 2004-09-07 Intel Corporation PCB design and method for providing vented blind vias
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
KR100771467B1 (ko) * 2006-10-30 2007-10-30 삼성전기주식회사 회로기판 및 그 제조방법
US20090091027A1 (en) * 2007-10-05 2009-04-09 Powertech Technology Inc. Semiconductor package having restraining ring surfaces against soldering crack
US9675443B2 (en) 2009-09-10 2017-06-13 Johnson & Johnson Vision Care, Inc. Energized ophthalmic lens including stacked integrated components
KR20100079183A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 반도체 패키지 장치와 그 제조 방법
US20110169158A1 (en) * 2010-01-14 2011-07-14 Qualcomm Incorporated Solder Pillars in Flip Chip Assembly
US8692390B2 (en) * 2011-02-18 2014-04-08 Chipbond Technology Corporation Pyramid bump structure
US8950862B2 (en) 2011-02-28 2015-02-10 Johnson & Johnson Vision Care, Inc. Methods and apparatus for an ophthalmic lens with functional insert layers
US9233513B2 (en) 2011-03-18 2016-01-12 Johnson & Johnson Vision Care, Inc. Apparatus for manufacturing stacked integrated component media inserts for ophthalmic devices
US10451897B2 (en) 2011-03-18 2019-10-22 Johnson & Johnson Vision Care, Inc. Components with multiple energization elements for biomedical devices
US9698129B2 (en) 2011-03-18 2017-07-04 Johnson & Johnson Vision Care, Inc. Stacked integrated component devices with energization
US9804418B2 (en) 2011-03-21 2017-10-31 Johnson & Johnson Vision Care, Inc. Methods and apparatus for functional insert with power layer
CN104204914B (zh) * 2012-01-26 2018-06-15 庄臣及庄臣视力保护公司 用于眼科装置的堆叠式集成部件介质插入物
US8857983B2 (en) 2012-01-26 2014-10-14 Johnson & Johnson Vision Care, Inc. Ophthalmic lens assembly having an integrated antenna structure
US10361404B2 (en) 2014-08-21 2019-07-23 Johnson & Johnson Vision Care, Inc. Anodes for use in biocompatible energization elements
US10381687B2 (en) 2014-08-21 2019-08-13 Johnson & Johnson Vision Care, Inc. Methods of forming biocompatible rechargable energization elements for biomedical devices
US9715130B2 (en) 2014-08-21 2017-07-25 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form separators for biocompatible energization elements for biomedical devices
US9383593B2 (en) 2014-08-21 2016-07-05 Johnson & Johnson Vision Care, Inc. Methods to form biocompatible energization elements for biomedical devices comprising laminates and placed separators
US9941547B2 (en) 2014-08-21 2018-04-10 Johnson & Johnson Vision Care, Inc. Biomedical energization elements with polymer electrolytes and cavity structures
US9599842B2 (en) 2014-08-21 2017-03-21 Johnson & Johnson Vision Care, Inc. Device and methods for sealing and encapsulation for biocompatible energization elements
US10361405B2 (en) 2014-08-21 2019-07-23 Johnson & Johnson Vision Care, Inc. Biomedical energization elements with polymer electrolytes
US10627651B2 (en) 2014-08-21 2020-04-21 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers
US9793536B2 (en) 2014-08-21 2017-10-17 Johnson & Johnson Vision Care, Inc. Pellet form cathode for use in a biocompatible battery
US10345620B2 (en) 2016-02-18 2019-07-09 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices
US10497657B1 (en) * 2018-06-13 2019-12-03 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
KR20220009218A (ko) 2020-07-15 2022-01-24 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
US11955396B2 (en) * 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01302823A (ja) * 1988-05-31 1989-12-06 Fujitsu Ltd 半導体基板の平坦化方法
JPH03209840A (ja) * 1990-01-12 1991-09-12 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH06140405A (ja) * 1991-06-30 1994-05-20 Mitsumi Electric Co Ltd フリップチップバンプの構造

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160946A (ja) * 1984-12-31 1986-07-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体装置の接続構造体
US5283468A (en) * 1988-05-30 1994-02-01 Canon Kabushiki Kaisha Electric circuit apparatus
JPH02142134A (ja) * 1988-11-22 1990-05-31 Hitachi Ltd 半導体装置の製造方法およびそれにより得られた半導体装置
JP3150351B2 (ja) * 1991-02-15 2001-03-26 株式会社東芝 電子装置及びその製造方法
WO1994024704A1 (en) * 1993-04-12 1994-10-27 Bolger Justin C Area bonding conductive adhesive preforms

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01302823A (ja) * 1988-05-31 1989-12-06 Fujitsu Ltd 半導体基板の平坦化方法
JPH03209840A (ja) * 1990-01-12 1991-09-12 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH06140405A (ja) * 1991-06-30 1994-05-20 Mitsumi Electric Co Ltd フリップチップバンプの構造

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323542B1 (en) 1997-01-17 2001-11-27 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US6518651B2 (en) 1997-01-17 2003-02-11 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US7235881B2 (en) 1997-01-17 2007-06-26 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US7307351B2 (en) 1997-01-17 2007-12-11 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US7485973B2 (en) 1997-01-17 2009-02-03 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US7755205B2 (en) 1997-01-17 2010-07-13 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US7888177B2 (en) 1997-01-17 2011-02-15 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US8399999B2 (en) 1997-01-17 2013-03-19 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument

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US5600180A (en) 1997-02-04
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