CN1411045A - 半导体装置 - Google Patents
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Abstract
本发明的课题是抑制芯片的弯曲来提高凸点的接合性。本发明的半导体装置是经设置在半导体芯片1上的功能凸点2将半导体芯片1导电性地连接到芯片安装构件4上的倒装芯片结构的半导体装置,使对抗半导体芯片1的局部的弯曲力的虚设凸点3介于半导体芯片1与芯片安装构件4之间。
Description
(一)技术领域
本发明涉及使用了功能凸点的倒装芯片结构的半导体装置,特别是涉及使上述功能凸点的接合可靠性提高了的半导体装置。
(二)背景技术
图15是示出了在现有的半导体装置的芯片100上的功能凸点200的配置例。如图16中所示,在将该功能凸点200安装在芯片安装构件、例如安装基板400上设置的导体400a上后,通过对芯片100加热加压来连接两导体100a、400a。再有,利用保护膜600覆盖了基板400的上表面。
(三)发明内容
但是,例如像合并使用超声波的热压接键合法那样,在对该芯片100施加了超声波振动的情况下,由于该施加压力的缘故,对于芯片100来说,存在在垂直方向上发生弯曲的可能性。其结果是,如图15中所示,在不均匀地分布了凸点200的情况下,其分布密度低的部分、特别是图15中用虚线包围的角部120的弯曲变大,凸点200的接合性变差。
本发明是鉴于上述问题而进行的,其目的在于得到可抑制芯片的弯曲以提高凸点的接合性的半导体装置。
为了达到上述目的,本发明的半导体装置是经设置在芯片上的功能凸点将上述芯片导电性地连接到芯片安装构件上的倒装芯片结构的半导体装置,其特征在于:使对抗上述芯片的局部的弯曲力的支撑构件介于上述芯片与上述芯片安装构件之间。
按照本发明,为了将功能凸点连接到芯片安装构件上而对芯片加压时,支撑构件对抗作用于芯片上的施加压力。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在以上述芯片的中心为基准的上述功能凸点的点对称的空的位置上配置了上述支撑构件。
按照本发明,利用支撑构件支撑以芯片的中心为基准的功能凸点的点对称的空的位置。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,将上述点对称的空的位置限定于上述芯片的规定的角部区域。
按照本发明,利用支撑构件支撑规定的角部区域的点对称的空的位置。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片的一方和另一方的边长分别为D和E的情况下,将上述角部区域设定为(D/3)×(E/3)的大小。
按照本发明,将上述角部区域限制于由上述芯片的一方和另一方的边长D和E规定的(D/3)×(E/3)的大小。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片上已设定的规定的凸点配置位置上且在最接近各角部的部分上配置了上述支撑构件。
按照本发明,利用支撑构件支撑最接近芯片的各角部的凸点配置位置。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是设置在上述芯片上的、且不与上述芯片安装构件导电性地连接的虚设凸点。
按照本发明,利用虚设凸点来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片安装构件的芯片安装面上用电绝缘性的保护膜覆盖了上述虚设凸点接触的区域。
按照本发明,可减少在虚设凸点进行金属接合时成为问题的对于功能凸点的接合能的供给损耗。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是在上述功能凸点的突出方向上以环状从上述芯片伸出的金属引线。
按照本发明,利用环状的金属引线来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是从上述芯片和上述芯片安装构件的某一方朝向另一方突出的具有弹性的突起物。
按照本发明,利用弹性突起物来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是从上述芯片和上述芯片安装构件的双方起相对地突出的具有弹性的突起物。
按照本发明,利用从芯片和芯片安装构件的双方突出的的突起物来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是与上述芯片和上述芯片安装构件的双方独立的具有弹性的衬垫。
按照本发明,利用与芯片和芯片安装构件的双方独立的衬垫来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂。
按照本发明,底垫树脂抑制因半导体装置接受的热应力引起的凸点接合部的断裂现象。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是具有弹性的充填剂,在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂,在上述底垫树脂内埋置了上述充填剂。
按照本发明,利用埋置于底垫树脂内的充填剂来支撑芯片。
(四)附图说明
图1是示出本发明的实施例1的半导体装置的虚设凸点的配置例的平面图。
图2是示出本发明的实施例2的半导体装置的虚设凸点的配置例的平面图。
图3是示出本发明的实施例3的半导体装置的虚设凸点的配置例的平面图。
图4是示出上述实施例3的凸点配置位置的另一例的平面图。
图5是示出上述实施例3的凸点配置位置的又一例的平面图。
图6是示出上述实施例3的凸点配置位置的又一例的平面图。
图7是示出本发明的实施例4的半导体装置的的结构的剖面图。
图8是示出本发明的实施例5的半导体装置的的结构的剖面图。
图9是示出本发明的实施例6的半导体装置的的结构的剖面图。
图10是示出上述实施例6的突起物的变例的剖面图。
图11是示出上述实施例6的突起物的另一变例的剖面图。
图12是示出本发明的实施例7的半导体装置的的结构的剖面图。
图13是示出本发明的实施例8的半导体装置的的结构的剖面图。
图14是示出本发明的实施例9的半导体装置的的结构的剖面图。
图15是示出现有的半导体装置的凸点的配置例的平面图。
图16是示出上述现有的半导体装置中的对于芯片的弯曲力的作用形态的剖面图。
具体实施方式
以下,参照附图,详细地说明本发明的半导体装置的优选实施例。
实施例1.
图1是示出本发明的实施例1的半导体装置的虚设凸点的配置例的平面图。
在该实施例1中,设置了对于半导体芯片1在半导体装置的工作功能方面所必要的金属凸点(以下,称为功能凸点2)和不影响半导体装置的工作功能的、即不起到作为电源、地、信号传送等的导体的作用的凸点(以下,称为虚设凸点3)。
各功能凸点2不一定设置在相对于半导体芯片1的中心呈点对称的位置上。因此,在该实施例1中,在该点对称性不成立的功能凸点2的点对称的空的位置上设置上述虚设凸点3。
按照该实施例1,由于将功能凸点2与虚设凸点3合在一起的凸点组相对于半导体芯片1的中心以点对称的方式分布,故即使在例如像合并使用超声波的热压接键合法那样,在对半导体芯片1施加了超声波振动的情况下,避免了半导体芯片1中的不存在功能凸点2的部位、或功能凸点2的分布密度小的部位局部地发生大的弯曲这样的不良情况,提高了功能凸点2的接合性。
实施例2.
接着,说明本发明的实施例2。该实施例2是只在半导体芯片1的各角部区域应用了上述的实施例1的技术的实施例。即,在半导体芯片1的各角部区域中,相对于点对称性不成立的功能凸点2,在其点对称的空的位置上设置上述虚设凸点3。
按照该实施例2,避免了半导体芯片1的相对的各角部区域的一方局部地发生大的弯曲这样的不良情况,提高了功能凸点2的接合性。此外,即使在例如图1那样在半导体芯片1的内部区域中存在功能凸点2的情况下,由于虚设凸点3的排列位置被限定于上述角部区域,故可得到减少该虚设凸点3的配置数目的优点。
再有,在该实施例2中,在半导体芯片1的一方和另一方的边长分别为D和E的情况下,将上述角部区域设定为(D/3)×(E/3)的大小。但是,该区域的大小也可根据凸点2、3的排列密度等适当地变更。
实施例3.
接着,说明本发明的实施例3。图3中示出的半导体芯片1将其凸点配置位置设定为矩阵状,以便在该半导体芯片1的整个区域中均等地分布。此外,图4和5中示出的半导体芯片1将其凸点配置位置设定于边缘部上,再者,图6中示出的半导体芯片1将其凸点配置位置设定于边缘和内部的一部分上。
在该实施例3中,在设定了上述那样的凸点配置位置的情况下,至少在最接近于半导体芯片1的各角部的凸点配置位置上配置虚设凸点3。因而,即使在半导体芯片1的角部附近发生了垂直方向的弯曲的情况下,也只在虚设凸点3中发生接合不良。即,避免了在功能凸点2中的接合不良。
实施例4.
接着,参照图7说明本发明的实施例4。该实施例4在芯片安装构件4(基板,或下侧芯片)中具有用不与虚设凸点3进行金属接合的电绝缘性的保护膜覆盖了虚设凸点3接触的面的结构。再有,在该图7中,符号1a表示在半导体芯片1上设置的焊区(pad)等的导体,符号4a表示在芯片安装构件4上设置的接合区(land)等的导体。
按照该实施例4,可减少在虚设凸点3进行金属接合时成为问题的对功能凸点2的接合能的供给损耗。
再有,作为上述的绝缘性的保护膜6,可使用在作为基板的表面上设置的保护膜的材料而使用的阻焊剂或作为半导体芯片1表面的保护膜的材料使用的聚酰亚胺涂膜等。
在此,功能凸点2和虚设凸点3除了用溅射法或电镀法形成的凸点外,还包含由含有导电性粒子的粘结剂构成的凸点。
实施例5.
如图8中所示,在该实施例5中,使用了形成为环状的金属制的引线7来代替上述的实施例1~4中的虚设凸点3。
该金属引线7由以金、铜、铅、锡等的金属为主成分的金属细线或在其表面上涂敷了绝缘性覆盖膜的细线构成,利用与一般的引线键合方法同样的方法将其两端连接到半导体芯片1的导体1a上。
按照该实施例5,由于可用宽的面积来抑制半导体芯片1的垂直方向的弯曲,故可进一步提高功能凸点2的接合性。
实施例6.
如图9中所示,在该实施例6中,设置了具有弹性的突起物8来代替上述的实施例1~4中的虚设凸点3。该弹性突起物8具有半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙大致同等的高度,例如图示那样,被设置在半导体芯片1的表面上。
如图10中所示,也可在芯片安装构件4的表面上设置上述弹性突起物8。
按照该实施例6,与设置了虚设凸点3的情况相同,可确保位于半导体芯片1的角部的功能凸点2的良好的接合性。
再有,如图11中所示,也可分别在半导体芯片1和芯片安装构件4的表面上相向地设置具有上述弹性突起物8的大致1/2高度的2个弹性突起物8a和弹性突起物8b,使这2个突起物相接。
实施例7.
如图12中所示,该实施例7具有使与半导体芯片1和芯片安装构件4独立的、且具有同半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙大致同等的厚度的具有弹性的衬垫9介入该间隙中的结构。
按照该实施例7,不在半导体芯片1和芯片安装构件4的表面上附加具有弹性的构件,而是利用使之介于其间的弹性衬垫9,可得到与使用了上述的虚设凸点3的情况同样的提高功能凸点2的接合性的效果。
实施例8.
如图13中所示,该实施例8具有在上述的实施例1~7中在半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙中充填了底垫(underfill)树脂10的结构。再有,图13示出了在图7中示出的半导体芯片1与芯片安装构件4之间充填了底垫树脂10的状态。
按照该实施例8,可抑制因半导体装置接受的热应力而引起的凸点接合部的断裂现象,可得到使凸点接合部的寿命提高的效果。
实施例9.
如图14中所示,该实施例9具有在底垫树脂10内埋置了具有与半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙大致同等的高度的、具有弹性的充填剂11来代替上述的实施例8中的虚设凸点3的结构。
按照该实施例9,不需要形成虚设凸点3用的附加操作,利用埋置于底垫树脂10内的弹性充填剂11,可得到与使用了该虚设凸点3的实施例8同样的效果。
如以上所说明的那样,按照本发明,在为了将功能凸点连接到芯片安装构件上而对芯片加压时,由于支撑构件对抗作用于芯片的施加压力,故可抑制施加上述超声波振动时的芯片的弯曲。
按照本发明的下一个方面,由于利用支撑构件来支撑以芯片的中心为基准的功能凸点的点对称的空的位置,故避免了芯片中的不存在功能凸点的部位、或功能凸点的分布密度小的部位局部地发生大的弯曲这样的不良情况,提高了该凸点的接合性。
按照本发明的下一个方面,由于将点对称的空的位置限定于芯片的规定的角部区域,故可得到减少支撑构件的配置数目的优点。
按照本发明的下一个方面,由于支撑构件在容易产生弯曲的芯片的(D/3)×(E/3)的角部区域中支撑芯片,故可减少支撑构件的配置数目。
按照本发明的下一个方面,由于利用支撑构件支撑最接近于芯片的各角部的凸点配置位置,故即使在芯片的角部附近发生了垂直方向的弯曲的情况下,也只在支撑构件中发生接合不良。即,避免了功能凸点的接合不良。
按照本发明的下一个方面,由于使用虚设凸点作为支撑构件,故利用该虚设凸点来支撑芯片。
按照本发明的下一个方面,由于用电绝缘性的保护膜覆盖住虚设凸点接触的芯片安装构件的面,故可减少在上述虚设凸点进行金属接合时成为问题的对于功能凸点的接合能的供给损耗。
按照本发明的下一个方面,由于利用环状的金属引线来支撑芯片,故可用宽的面积来抑制该芯片的垂直方向的弯曲。
按照本发明的下一个方面,利用从芯片和芯片安装构件的某一方朝向另一方突出的弹性突起物的支撑力抑制芯片的弯曲。
按照本发明的下一个方面,利用从芯片和芯片安装构件的双方突出的突起物的支撑力抑制芯片的弯曲。
按照本发明的下一个方面,由于使用与芯片和芯片安装构件的双方独立的衬垫作为支撑构件,故没有必要在芯片和基板的表面上附加具有弹性的构件。
按照本发明的下一个方面,由于在芯片与芯片安装构件之间形成的间隙中充填底垫树脂,故可抑制因半导体装置接受的热应力而引起的凸点接合部的断裂现象。
按照本发明的下一个方面,可利用由底垫树脂保持了的充填剂来抑制芯片的弯曲。
Claims (13)
1.一种半导体装置,该半导体装置是经设置在芯片上的功能凸点将上述芯片导电性地连接到芯片安装构件上的倒装芯片结构的半导体装置,其特征在于:
使对抗上述芯片的局部的弯曲力的支撑构件介于上述芯片与上述芯片安装构件之间。
2.如权利要求1中所述的半导体装置,其特征在于:
在以上述芯片的中心为基准的上述功能凸点的点对称的空的位置上配置了上述支撑构件。
3.如权利要求2中所述的半导体装置,其特征在于:
将上述点对称的空的位置限定于上述芯片的规定的角部区域。
4.如权利要求3中所述的半导体装置,其特征在于:
在上述芯片的一方和另一方的边长分别为D和E的情况下,将上述角部区域设定为(D/3)×(E/3)的大小。
5.如权利要求1中所述的半导体装置,其特征在于:
在上述芯片上已设定的规定的凸点配置位置上且在最接近各角部的部分上配置了上述支撑构件。
6.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是设置在上述芯片上的、且不与上述芯片安装构件导电性地连接的虚设凸点。
7.如权利要求6中所述的半导体装置,其特征在于:
在上述芯片安装构件的芯片安装面上用电绝缘性的保护膜覆盖住上述虚设凸点接触的区域。
8.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是在上述功能凸点的突出方向上以环状从上述芯片伸出的金属引线。
9.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是从上述芯片和上述芯片安装构件的某一方朝向另一方突出的具有弹性的突起物。
10.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是从上述芯片和上述芯片安装构件的双方起相向地突出的具有弹性的突起物。
11.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是与上述芯片和上述芯片安装构件的双方独立的具有弹性的衬垫。
12.如权利要求1中所述的半导体装置,其特征在于:
在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂。
13.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是具有弹性的充填剂,在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂,在上述底垫树脂内埋置了上述充填剂。
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2002
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- 2002-04-24 KR KR1020020022393A patent/KR20030026206A/ko not_active Application Discontinuation
- 2002-05-22 DE DE10222678A patent/DE10222678A1/de not_active Withdrawn
- 2002-05-27 CN CN02120621A patent/CN1411045A/zh active Pending
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CN100456464C (zh) * | 2005-06-09 | 2009-01-28 | 恩益禧电子股份有限公司 | 半导体装置以及用于制造该半导体装置的方法 |
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CN104064477A (zh) * | 2013-03-22 | 2014-09-24 | 瑞萨电子株式会社 | 制造半导体装置的方法和半导体装置 |
CN104064477B (zh) * | 2013-03-22 | 2017-09-22 | 瑞萨电子株式会社 | 制造半导体装置的方法和半导体装置 |
CN106206329A (zh) * | 2015-05-29 | 2016-12-07 | 株式会社东芝 | 半导体装置 |
CN106206329B (zh) * | 2015-05-29 | 2018-12-14 | 东芝存储器株式会社 | 半导体装置 |
CN111341761A (zh) * | 2018-12-19 | 2020-06-26 | 南亚科技股份有限公司 | 半导体结构 |
CN112614821A (zh) * | 2020-12-15 | 2021-04-06 | Oppo广东移动通信有限公司 | 封装结构及其制备方法、电子设备 |
Also Published As
Publication number | Publication date |
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US20030060035A1 (en) | 2003-03-27 |
KR20030026206A (ko) | 2003-03-31 |
US6677677B2 (en) | 2004-01-13 |
DE10222678A1 (de) | 2003-06-26 |
JP2003100801A (ja) | 2003-04-04 |
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