CN1411045A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN1411045A
CN1411045A CN02120621A CN02120621A CN1411045A CN 1411045 A CN1411045 A CN 1411045A CN 02120621 A CN02120621 A CN 02120621A CN 02120621 A CN02120621 A CN 02120621A CN 1411045 A CN1411045 A CN 1411045A
Authority
CN
China
Prior art keywords
chip
semiconductor device
salient point
mentioned
installation component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN02120621A
Other languages
English (en)
Inventor
木村通孝
岩崎俊宽
畑中康道
若宫敬一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN1411045A publication Critical patent/CN1411045A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135Alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165Alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751Function
    • H01L2224/17515Bump connectors having different functions
    • H01L2224/17517Bump connectors having different functions including bump connectors providing primarily mechanical support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139Guiding structures on the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114Guiding structures outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141Guiding structures both on and outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

本发明的课题是抑制芯片的弯曲来提高凸点的接合性。本发明的半导体装置是经设置在半导体芯片1上的功能凸点2将半导体芯片1导电性地连接到芯片安装构件4上的倒装芯片结构的半导体装置,使对抗半导体芯片1的局部的弯曲力的虚设凸点3介于半导体芯片1与芯片安装构件4之间。

Description

半导体装置
(一)技术领域
本发明涉及使用了功能凸点的倒装芯片结构的半导体装置,特别是涉及使上述功能凸点的接合可靠性提高了的半导体装置。
(二)背景技术
图15是示出了在现有的半导体装置的芯片100上的功能凸点200的配置例。如图16中所示,在将该功能凸点200安装在芯片安装构件、例如安装基板400上设置的导体400a上后,通过对芯片100加热加压来连接两导体100a、400a。再有,利用保护膜600覆盖了基板400的上表面。
(三)发明内容
但是,例如像合并使用超声波的热压接键合法那样,在对该芯片100施加了超声波振动的情况下,由于该施加压力的缘故,对于芯片100来说,存在在垂直方向上发生弯曲的可能性。其结果是,如图15中所示,在不均匀地分布了凸点200的情况下,其分布密度低的部分、特别是图15中用虚线包围的角部120的弯曲变大,凸点200的接合性变差。
本发明是鉴于上述问题而进行的,其目的在于得到可抑制芯片的弯曲以提高凸点的接合性的半导体装置。
为了达到上述目的,本发明的半导体装置是经设置在芯片上的功能凸点将上述芯片导电性地连接到芯片安装构件上的倒装芯片结构的半导体装置,其特征在于:使对抗上述芯片的局部的弯曲力的支撑构件介于上述芯片与上述芯片安装构件之间。
按照本发明,为了将功能凸点连接到芯片安装构件上而对芯片加压时,支撑构件对抗作用于芯片上的施加压力。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在以上述芯片的中心为基准的上述功能凸点的点对称的空的位置上配置了上述支撑构件。
按照本发明,利用支撑构件支撑以芯片的中心为基准的功能凸点的点对称的空的位置。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,将上述点对称的空的位置限定于上述芯片的规定的角部区域。
按照本发明,利用支撑构件支撑规定的角部区域的点对称的空的位置。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片的一方和另一方的边长分别为D和E的情况下,将上述角部区域设定为(D/3)×(E/3)的大小。
按照本发明,将上述角部区域限制于由上述芯片的一方和另一方的边长D和E规定的(D/3)×(E/3)的大小。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片上已设定的规定的凸点配置位置上且在最接近各角部的部分上配置了上述支撑构件。
按照本发明,利用支撑构件支撑最接近芯片的各角部的凸点配置位置。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是设置在上述芯片上的、且不与上述芯片安装构件导电性地连接的虚设凸点。
按照本发明,利用虚设凸点来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片安装构件的芯片安装面上用电绝缘性的保护膜覆盖了上述虚设凸点接触的区域。
按照本发明,可减少在虚设凸点进行金属接合时成为问题的对于功能凸点的接合能的供给损耗。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是在上述功能凸点的突出方向上以环状从上述芯片伸出的金属引线。
按照本发明,利用环状的金属引线来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是从上述芯片和上述芯片安装构件的某一方朝向另一方突出的具有弹性的突起物。
按照本发明,利用弹性突起物来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是从上述芯片和上述芯片安装构件的双方起相对地突出的具有弹性的突起物。
按照本发明,利用从芯片和芯片安装构件的双方突出的的突起物来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是与上述芯片和上述芯片安装构件的双方独立的具有弹性的衬垫。
按照本发明,利用与芯片和芯片安装构件的双方独立的衬垫来支撑芯片。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂。
按照本发明,底垫树脂抑制因半导体装置接受的热应力引起的凸点接合部的断裂现象。
本发明的下一个方面的半导体装置的特征在于:在上述的发明中,上述支撑构件是具有弹性的充填剂,在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂,在上述底垫树脂内埋置了上述充填剂。
按照本发明,利用埋置于底垫树脂内的充填剂来支撑芯片。
(四)附图说明
图1是示出本发明的实施例1的半导体装置的虚设凸点的配置例的平面图。
图2是示出本发明的实施例2的半导体装置的虚设凸点的配置例的平面图。
图3是示出本发明的实施例3的半导体装置的虚设凸点的配置例的平面图。
图4是示出上述实施例3的凸点配置位置的另一例的平面图。
图5是示出上述实施例3的凸点配置位置的又一例的平面图。
图6是示出上述实施例3的凸点配置位置的又一例的平面图。
图7是示出本发明的实施例4的半导体装置的的结构的剖面图。
图8是示出本发明的实施例5的半导体装置的的结构的剖面图。
图9是示出本发明的实施例6的半导体装置的的结构的剖面图。
图10是示出上述实施例6的突起物的变例的剖面图。
图11是示出上述实施例6的突起物的另一变例的剖面图。
图12是示出本发明的实施例7的半导体装置的的结构的剖面图。
图13是示出本发明的实施例8的半导体装置的的结构的剖面图。
图14是示出本发明的实施例9的半导体装置的的结构的剖面图。
图15是示出现有的半导体装置的凸点的配置例的平面图。
图16是示出上述现有的半导体装置中的对于芯片的弯曲力的作用形态的剖面图。
具体实施方式
以下,参照附图,详细地说明本发明的半导体装置的优选实施例。
实施例1.
图1是示出本发明的实施例1的半导体装置的虚设凸点的配置例的平面图。
在该实施例1中,设置了对于半导体芯片1在半导体装置的工作功能方面所必要的金属凸点(以下,称为功能凸点2)和不影响半导体装置的工作功能的、即不起到作为电源、地、信号传送等的导体的作用的凸点(以下,称为虚设凸点3)。
各功能凸点2不一定设置在相对于半导体芯片1的中心呈点对称的位置上。因此,在该实施例1中,在该点对称性不成立的功能凸点2的点对称的空的位置上设置上述虚设凸点3。
按照该实施例1,由于将功能凸点2与虚设凸点3合在一起的凸点组相对于半导体芯片1的中心以点对称的方式分布,故即使在例如像合并使用超声波的热压接键合法那样,在对半导体芯片1施加了超声波振动的情况下,避免了半导体芯片1中的不存在功能凸点2的部位、或功能凸点2的分布密度小的部位局部地发生大的弯曲这样的不良情况,提高了功能凸点2的接合性。
实施例2.
接着,说明本发明的实施例2。该实施例2是只在半导体芯片1的各角部区域应用了上述的实施例1的技术的实施例。即,在半导体芯片1的各角部区域中,相对于点对称性不成立的功能凸点2,在其点对称的空的位置上设置上述虚设凸点3。
按照该实施例2,避免了半导体芯片1的相对的各角部区域的一方局部地发生大的弯曲这样的不良情况,提高了功能凸点2的接合性。此外,即使在例如图1那样在半导体芯片1的内部区域中存在功能凸点2的情况下,由于虚设凸点3的排列位置被限定于上述角部区域,故可得到减少该虚设凸点3的配置数目的优点。
再有,在该实施例2中,在半导体芯片1的一方和另一方的边长分别为D和E的情况下,将上述角部区域设定为(D/3)×(E/3)的大小。但是,该区域的大小也可根据凸点2、3的排列密度等适当地变更。
实施例3.
接着,说明本发明的实施例3。图3中示出的半导体芯片1将其凸点配置位置设定为矩阵状,以便在该半导体芯片1的整个区域中均等地分布。此外,图4和5中示出的半导体芯片1将其凸点配置位置设定于边缘部上,再者,图6中示出的半导体芯片1将其凸点配置位置设定于边缘和内部的一部分上。
在该实施例3中,在设定了上述那样的凸点配置位置的情况下,至少在最接近于半导体芯片1的各角部的凸点配置位置上配置虚设凸点3。因而,即使在半导体芯片1的角部附近发生了垂直方向的弯曲的情况下,也只在虚设凸点3中发生接合不良。即,避免了在功能凸点2中的接合不良。
实施例4.
接着,参照图7说明本发明的实施例4。该实施例4在芯片安装构件4(基板,或下侧芯片)中具有用不与虚设凸点3进行金属接合的电绝缘性的保护膜覆盖了虚设凸点3接触的面的结构。再有,在该图7中,符号1a表示在半导体芯片1上设置的焊区(pad)等的导体,符号4a表示在芯片安装构件4上设置的接合区(land)等的导体。
按照该实施例4,可减少在虚设凸点3进行金属接合时成为问题的对功能凸点2的接合能的供给损耗。
再有,作为上述的绝缘性的保护膜6,可使用在作为基板的表面上设置的保护膜的材料而使用的阻焊剂或作为半导体芯片1表面的保护膜的材料使用的聚酰亚胺涂膜等。
在此,功能凸点2和虚设凸点3除了用溅射法或电镀法形成的凸点外,还包含由含有导电性粒子的粘结剂构成的凸点。
实施例5.
如图8中所示,在该实施例5中,使用了形成为环状的金属制的引线7来代替上述的实施例1~4中的虚设凸点3。
该金属引线7由以金、铜、铅、锡等的金属为主成分的金属细线或在其表面上涂敷了绝缘性覆盖膜的细线构成,利用与一般的引线键合方法同样的方法将其两端连接到半导体芯片1的导体1a上。
按照该实施例5,由于可用宽的面积来抑制半导体芯片1的垂直方向的弯曲,故可进一步提高功能凸点2的接合性。
实施例6.
如图9中所示,在该实施例6中,设置了具有弹性的突起物8来代替上述的实施例1~4中的虚设凸点3。该弹性突起物8具有半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙大致同等的高度,例如图示那样,被设置在半导体芯片1的表面上。
如图10中所示,也可在芯片安装构件4的表面上设置上述弹性突起物8。
按照该实施例6,与设置了虚设凸点3的情况相同,可确保位于半导体芯片1的角部的功能凸点2的良好的接合性。
再有,如图11中所示,也可分别在半导体芯片1和芯片安装构件4的表面上相向地设置具有上述弹性突起物8的大致1/2高度的2个弹性突起物8a和弹性突起物8b,使这2个突起物相接。
实施例7.
如图12中所示,该实施例7具有使与半导体芯片1和芯片安装构件4独立的、且具有同半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙大致同等的厚度的具有弹性的衬垫9介入该间隙中的结构。
按照该实施例7,不在半导体芯片1和芯片安装构件4的表面上附加具有弹性的构件,而是利用使之介于其间的弹性衬垫9,可得到与使用了上述的虚设凸点3的情况同样的提高功能凸点2的接合性的效果。
实施例8.
如图13中所示,该实施例8具有在上述的实施例1~7中在半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙中充填了底垫(underfill)树脂10的结构。再有,图13示出了在图7中示出的半导体芯片1与芯片安装构件4之间充填了底垫树脂10的状态。
按照该实施例8,可抑制因半导体装置接受的热应力而引起的凸点接合部的断裂现象,可得到使凸点接合部的寿命提高的效果。
实施例9.
如图14中所示,该实施例9具有在底垫树脂10内埋置了具有与半导体芯片1与芯片安装构件4(基板或下侧芯片)之间的间隙大致同等的高度的、具有弹性的充填剂11来代替上述的实施例8中的虚设凸点3的结构。
按照该实施例9,不需要形成虚设凸点3用的附加操作,利用埋置于底垫树脂10内的弹性充填剂11,可得到与使用了该虚设凸点3的实施例8同样的效果。
如以上所说明的那样,按照本发明,在为了将功能凸点连接到芯片安装构件上而对芯片加压时,由于支撑构件对抗作用于芯片的施加压力,故可抑制施加上述超声波振动时的芯片的弯曲。
按照本发明的下一个方面,由于利用支撑构件来支撑以芯片的中心为基准的功能凸点的点对称的空的位置,故避免了芯片中的不存在功能凸点的部位、或功能凸点的分布密度小的部位局部地发生大的弯曲这样的不良情况,提高了该凸点的接合性。
按照本发明的下一个方面,由于将点对称的空的位置限定于芯片的规定的角部区域,故可得到减少支撑构件的配置数目的优点。
按照本发明的下一个方面,由于支撑构件在容易产生弯曲的芯片的(D/3)×(E/3)的角部区域中支撑芯片,故可减少支撑构件的配置数目。
按照本发明的下一个方面,由于利用支撑构件支撑最接近于芯片的各角部的凸点配置位置,故即使在芯片的角部附近发生了垂直方向的弯曲的情况下,也只在支撑构件中发生接合不良。即,避免了功能凸点的接合不良。
按照本发明的下一个方面,由于使用虚设凸点作为支撑构件,故利用该虚设凸点来支撑芯片。
按照本发明的下一个方面,由于用电绝缘性的保护膜覆盖住虚设凸点接触的芯片安装构件的面,故可减少在上述虚设凸点进行金属接合时成为问题的对于功能凸点的接合能的供给损耗。
按照本发明的下一个方面,由于利用环状的金属引线来支撑芯片,故可用宽的面积来抑制该芯片的垂直方向的弯曲。
按照本发明的下一个方面,利用从芯片和芯片安装构件的某一方朝向另一方突出的弹性突起物的支撑力抑制芯片的弯曲。
按照本发明的下一个方面,利用从芯片和芯片安装构件的双方突出的突起物的支撑力抑制芯片的弯曲。
按照本发明的下一个方面,由于使用与芯片和芯片安装构件的双方独立的衬垫作为支撑构件,故没有必要在芯片和基板的表面上附加具有弹性的构件。
按照本发明的下一个方面,由于在芯片与芯片安装构件之间形成的间隙中充填底垫树脂,故可抑制因半导体装置接受的热应力而引起的凸点接合部的断裂现象。
按照本发明的下一个方面,可利用由底垫树脂保持了的充填剂来抑制芯片的弯曲。

Claims (13)

1.一种半导体装置,该半导体装置是经设置在芯片上的功能凸点将上述芯片导电性地连接到芯片安装构件上的倒装芯片结构的半导体装置,其特征在于:
使对抗上述芯片的局部的弯曲力的支撑构件介于上述芯片与上述芯片安装构件之间。
2.如权利要求1中所述的半导体装置,其特征在于:
在以上述芯片的中心为基准的上述功能凸点的点对称的空的位置上配置了上述支撑构件。
3.如权利要求2中所述的半导体装置,其特征在于:
将上述点对称的空的位置限定于上述芯片的规定的角部区域。
4.如权利要求3中所述的半导体装置,其特征在于:
在上述芯片的一方和另一方的边长分别为D和E的情况下,将上述角部区域设定为(D/3)×(E/3)的大小。
5.如权利要求1中所述的半导体装置,其特征在于:
在上述芯片上已设定的规定的凸点配置位置上且在最接近各角部的部分上配置了上述支撑构件。
6.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是设置在上述芯片上的、且不与上述芯片安装构件导电性地连接的虚设凸点。
7.如权利要求6中所述的半导体装置,其特征在于:
在上述芯片安装构件的芯片安装面上用电绝缘性的保护膜覆盖住上述虚设凸点接触的区域。
8.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是在上述功能凸点的突出方向上以环状从上述芯片伸出的金属引线。
9.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是从上述芯片和上述芯片安装构件的某一方朝向另一方突出的具有弹性的突起物。
10.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是从上述芯片和上述芯片安装构件的双方起相向地突出的具有弹性的突起物。
11.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是与上述芯片和上述芯片安装构件的双方独立的具有弹性的衬垫。
12.如权利要求1中所述的半导体装置,其特征在于:
在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂。
13.如权利要求1~5的任一项中所述的半导体装置,其特征在于:
上述支撑构件是具有弹性的充填剂,在上述芯片与上述芯片安装构件之间的间隙中充填了底垫树脂,在上述底垫树脂内埋置了上述充填剂。
CN02120621A 2001-09-25 2002-05-27 半导体装置 Pending CN1411045A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP292136/2001 2001-09-25
JP2001292136A JP2003100801A (ja) 2001-09-25 2001-09-25 半導体装置

Publications (1)

Publication Number Publication Date
CN1411045A true CN1411045A (zh) 2003-04-16

Family

ID=19114154

Family Applications (1)

Application Number Title Priority Date Filing Date
CN02120621A Pending CN1411045A (zh) 2001-09-25 2002-05-27 半导体装置

Country Status (5)

Country Link
US (1) US6677677B2 (zh)
JP (1) JP2003100801A (zh)
KR (1) KR20030026206A (zh)
CN (1) CN1411045A (zh)
DE (1) DE10222678A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100456464C (zh) * 2005-06-09 2009-01-28 恩益禧电子股份有限公司 半导体装置以及用于制造该半导体装置的方法
CN102959699A (zh) * 2010-08-06 2013-03-06 松下电器产业株式会社 电路基板及其制造方法
CN102956590A (zh) * 2011-08-17 2013-03-06 台湾积体电路制造股份有限公司 用于减少应力的伪倒装芯片凸块
CN101685205B (zh) * 2008-09-23 2013-05-29 瀚宇彩晶股份有限公司 芯片、芯片-玻璃接合的封装结构及液晶面板
CN104064477A (zh) * 2013-03-22 2014-09-24 瑞萨电子株式会社 制造半导体装置的方法和半导体装置
CN106206329A (zh) * 2015-05-29 2016-12-07 株式会社东芝 半导体装置
CN111341761A (zh) * 2018-12-19 2020-06-26 南亚科技股份有限公司 半导体结构
CN112614821A (zh) * 2020-12-15 2021-04-06 Oppo广东移动通信有限公司 封装结构及其制备方法、电子设备

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004104102A (ja) * 2002-08-21 2004-04-02 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6960830B2 (en) * 2002-10-31 2005-11-01 Rohm Co., Ltd. Semiconductor integrated circuit device with dummy bumps
US6750552B1 (en) * 2002-12-18 2004-06-15 Netlogic Microsystems, Inc. Integrated circuit package with solder bumps
US6762495B1 (en) * 2003-01-30 2004-07-13 Qualcomm Incorporated Area array package with non-electrically connected solder balls
US6930400B1 (en) * 2003-10-21 2005-08-16 Integrated Device Technology, Inc. Grid array microelectronic packages with increased periphery
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
JP3819395B2 (ja) * 2004-02-20 2006-09-06 沖電気工業株式会社 半導体装置の製造方法
JP2005302759A (ja) * 2004-04-06 2005-10-27 Matsushita Electric Ind Co Ltd 半導体装置
JP2005310837A (ja) * 2004-04-16 2005-11-04 Elpida Memory Inc 半導体装置及びその製造方法
US7109583B2 (en) * 2004-05-06 2006-09-19 Endwave Corporation Mounting with auxiliary bumps
DE102004029587B4 (de) * 2004-06-18 2006-05-24 Infineon Technologies Ag Substratbasiertes BGA-Gehäuse, insbesondere FBGA-Gehäuse
JP4566678B2 (ja) * 2004-10-04 2010-10-20 日立オートモティブシステムズ株式会社 パワーモジュール
CN100552948C (zh) * 2004-12-28 2009-10-21 松下电器产业株式会社 半导体芯片的安装结构体和其制造方法
JP2006222374A (ja) * 2005-02-14 2006-08-24 Fuji Film Microdevices Co Ltd 半導体チップ
US7659623B2 (en) * 2005-04-11 2010-02-09 Elpida Memory, Inc. Semiconductor device having improved wiring
US7215026B2 (en) * 2005-04-14 2007-05-08 Samsung Electonics Co., Ltd Semiconductor module and method of forming a semiconductor module
US20070069378A1 (en) * 2005-04-15 2007-03-29 Chang-Yong Park Semiconductor module and method of forming a semiconductor module
KR100702969B1 (ko) 2005-04-19 2007-04-03 삼성전자주식회사 더미 솔더 볼을 갖는 bga형 반도체 칩 패키지의 기판 실장 구조
US7118940B1 (en) * 2005-08-05 2006-10-10 Delphi Technologies, Inc. Method of fabricating an electronic package having underfill standoff
KR101247138B1 (ko) * 2005-09-14 2013-03-29 하테체 베타일리궁스 게엠베하 플립-칩 모듈 및 플립-칩 모듈의 제조 방법
US7863727B2 (en) * 2006-02-06 2011-01-04 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
FR2918212B1 (fr) * 2007-06-27 2009-09-25 Fr De Detecteurs Infrarouges S Procede pour la realisation d'une matrice de rayonnements electromagnetiques et procede pour remplacer un module elementaire d'une telle matrice de detection.
JP4693852B2 (ja) * 2008-02-22 2011-06-01 パナソニック株式会社 半導体装置および半導体装置の製造方法
WO2009116517A1 (ja) * 2008-03-17 2009-09-24 日本電気株式会社 電子装置及びその製造方法
JP2010278318A (ja) 2009-05-29 2010-12-09 Renesas Electronics Corp 半導体装置
JP2010287592A (ja) 2009-06-09 2010-12-24 Renesas Electronics Corp 半導体装置、半導体ウェハおよびその製造方法
KR101632399B1 (ko) * 2009-10-26 2016-06-23 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20120091691A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법
JP5286382B2 (ja) 2011-04-11 2013-09-11 株式会社日立製作所 半導体装置およびその製造方法
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
US8659126B2 (en) * 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8610247B2 (en) 2011-12-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a transformer with magnetic features
CN103208501B (zh) 2012-01-17 2017-07-28 奥林巴斯株式会社 固体摄像装置及其制造方法、摄像装置、基板、半导体装置
JP6021383B2 (ja) * 2012-03-30 2016-11-09 オリンパス株式会社 基板および半導体装置
KR20130096990A (ko) * 2012-02-23 2013-09-02 삼성전자주식회사 반도체 장치
KR101383002B1 (ko) 2012-05-25 2014-04-08 엘지이노텍 주식회사 반도체 패키지 기판, 이를 이용한 패키지 시스템 및 이의 제조 방법
JP2014035293A (ja) * 2012-08-09 2014-02-24 Hitachi Medical Corp 放射線検出器及びx線ct装置
US9171798B2 (en) * 2013-01-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for transmission lines in packages
US9773724B2 (en) * 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
US9679868B2 (en) * 2013-06-19 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Ball height control in bonding process
US9570421B2 (en) * 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
JP5770258B2 (ja) * 2013-12-20 2015-08-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2017034224A (ja) * 2015-07-29 2017-02-09 京セラ株式会社 電子モジュール
KR102478381B1 (ko) 2015-12-21 2022-12-20 삼성전자주식회사 반도체 패키지
CN106971949B (zh) * 2016-01-14 2019-06-28 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US10068866B2 (en) 2016-09-29 2018-09-04 Intel Corporation Integrated circuit package having rectangular aspect ratio
US10692813B2 (en) * 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
CN107621710A (zh) * 2017-11-10 2018-01-23 京东方科技集团股份有限公司 驱动芯片、显示基板、显示装置及显示装置的制作方法
JP2020150117A (ja) * 2019-03-13 2020-09-17 株式会社リコー 電子装置、および電子装置の製造方法
JP7321009B2 (ja) * 2019-07-01 2023-08-04 新光電気工業株式会社 配線基板、接合型配線基板及び配線基板の製造方法
KR20210051535A (ko) 2019-10-30 2021-05-10 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20220151307A (ko) 2021-05-06 2022-11-15 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224428A (ja) 1985-03-29 1986-10-06 Toshiba Corp 半導体装置
JP2506861B2 (ja) 1987-12-08 1996-06-12 松下電器産業株式会社 電気的接続接点の形成方法
JPH01238148A (ja) 1988-03-18 1989-09-22 Fuji Electric Co Ltd 半導体装置
US5176853A (en) * 1988-08-16 1993-01-05 Delco Electronics Corporation Controlled adhesion conductor
KR0153387B1 (ko) * 1993-12-16 1998-12-01 가네꼬 히사시 칩 캐리어 반도체 디바이스 어셈블리 및 그 형성 방법
US5400950A (en) 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
JPH07263490A (ja) 1994-03-22 1995-10-13 Hitachi Ltd フリップチップボンディング型半導体装置及びマイクロボンディング方法
JP3534842B2 (ja) 1994-09-30 2004-06-07 京セラ株式会社 半導体素子
JPH09115910A (ja) 1995-10-16 1997-05-02 Oki Electric Ind Co Ltd フリップチップの接続構造
US5719440A (en) * 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
JP3863213B2 (ja) * 1996-03-27 2006-12-27 株式会社ルネサステクノロジ 半導体装置
JP3688801B2 (ja) * 1996-04-25 2005-08-31 株式会社日立製作所 半導体装置及びその製造方法並びにその実装方法
JPH1074803A (ja) * 1996-08-30 1998-03-17 Sony Corp 電子部品及びその実装方法
US6329383B1 (en) * 1999-01-25 2001-12-11 Pharmacia Ab 2-amino-5-pyrimidine acetic acid compounds
JP4009380B2 (ja) 1999-02-18 2007-11-14 ローム株式会社 半導体チップの製造方法
JP3066963B1 (ja) * 1999-03-31 2000-07-17 インターナショナル・ビジネス・マシーンズ・コーポレ−ション はんだバンプの成形方法及び成形装置
TW434848B (en) * 2000-01-14 2001-05-16 Chen I Ming Semiconductor chip device and the packaging method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100456464C (zh) * 2005-06-09 2009-01-28 恩益禧电子股份有限公司 半导体装置以及用于制造该半导体装置的方法
CN101685205B (zh) * 2008-09-23 2013-05-29 瀚宇彩晶股份有限公司 芯片、芯片-玻璃接合的封装结构及液晶面板
US9198284B2 (en) 2010-08-06 2015-11-24 Panasonic Intellectual Property Management Co., Ltd. Circuit board and method for manufacturing same
CN102959699A (zh) * 2010-08-06 2013-03-06 松下电器产业株式会社 电路基板及其制造方法
CN102959699B (zh) * 2010-08-06 2015-12-09 松下电器产业株式会社 电路基板及其制造方法
CN102956590B (zh) * 2011-08-17 2015-11-25 台湾积体电路制造股份有限公司 用于减少应力的伪倒装芯片凸块
CN102956590A (zh) * 2011-08-17 2013-03-06 台湾积体电路制造股份有限公司 用于减少应力的伪倒装芯片凸块
CN104064477A (zh) * 2013-03-22 2014-09-24 瑞萨电子株式会社 制造半导体装置的方法和半导体装置
CN104064477B (zh) * 2013-03-22 2017-09-22 瑞萨电子株式会社 制造半导体装置的方法和半导体装置
CN106206329A (zh) * 2015-05-29 2016-12-07 株式会社东芝 半导体装置
CN106206329B (zh) * 2015-05-29 2018-12-14 东芝存储器株式会社 半导体装置
CN111341761A (zh) * 2018-12-19 2020-06-26 南亚科技股份有限公司 半导体结构
CN112614821A (zh) * 2020-12-15 2021-04-06 Oppo广东移动通信有限公司 封装结构及其制备方法、电子设备

Also Published As

Publication number Publication date
US20030060035A1 (en) 2003-03-27
KR20030026206A (ko) 2003-03-31
US6677677B2 (en) 2004-01-13
DE10222678A1 (de) 2003-06-26
JP2003100801A (ja) 2003-04-04

Similar Documents

Publication Publication Date Title
CN1411045A (zh) 半导体装置
CN1197153C (zh) 半导体器件
CN1207785C (zh) 半导体器件、电子装置的制造方法、电子装置和携带式信息终端
CN1229863C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1235286C (zh) 一种电子装置与制作此装置的方法
CN1265455C (zh) 半导体器件及其制造方法
CN1199268C (zh) 半导体装置及其制造方法
CN1266764C (zh) 半导体器件及其制造方法
CN1266766C (zh) 半导体器件及其制造方法
CN1135610C (zh) 各向异性导电膜和半导体芯片的安装方法以及半导体装置
CN1185698C (zh) 半导体装置及其制造方法、电路板以及电子设备
CN101080958A (zh) 部件内置模块及其制造方法
CN1790651A (zh) 芯片集成基板的制造方法
CN1744304A (zh) 使用电极气密密封的高可靠性半导体装置
CN1835661A (zh) 配线基板的制造方法
CN1577813A (zh) 电路模块及其制造方法
CN1262784A (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1340851A (zh) 电子器件及其制造方法
CN1674241A (zh) 半导体器件、其制造方法及其液晶模块和半导体模块
CN1943029A (zh) 半导体器件及其制造方法
CN1606154A (zh) 半导体器件及其制造方法
CN1674242A (zh) 半导体芯片、半导体装置、半导体装置的制造方法
CN1601736A (zh) 半导体集成电路装置及电子设备
CN1155997C (zh) 各向异性导电膜、半导体芯片的安装方法和半导体装置
CN1294652C (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication