CN1135610C - 各向异性导电膜和半导体芯片的安装方法以及半导体装置 - Google Patents
各向异性导电膜和半导体芯片的安装方法以及半导体装置 Download PDFInfo
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Abstract
本发明提供一种各向异性导电膜3,该各向异性导电膜粘接半导体芯片1与基板2,同时成为半导体芯片1与基板2的电导通媒体,该各向异性导电膜3通过层叠由掺入了导电性粒子的树脂构成的导电性粒子含有层31和由其流动性比导电性粒子含有层低的树脂构成的非导电层32并使其成为一体而构成。
Description
技术领域
本发明涉及各向异性导电膜和半导体芯片的安装方法以及半导体装置,特别是涉及适合于使半导体芯片的有源元件形成面朝向基板一侧来进行安装的各向异性导电膜和半导体芯片的安装方法以及半导体装置。
背景技术
在使半导体芯片的形成了电极的面朝下来进行安装的半导体芯片的安装方法、即所谓的倒装芯片安装中,经常使用各向异性导电膜。各向异性导电膜是将各向异性导电粘接剂形成为片状的膜,也称为ACF(各向异性导电膜)。厚度为50μm左右。通常,将其整体形成为细长的带状,此外,在使用前的状态下,在其表面背面上粘贴了覆盖膜。
此外,其材料结构的主流是,在环氧系列、聚氨酯系列等的热硬化性树脂中作为导电性粒子掺入了对环氧树脂粒子等进行了诸如Ni或Au的金属的电镀的粒子。再者,也存在对进行了金属电镀的树脂粒子再进行树脂覆盖的树脂粒子。此时,在树脂粒子相互间、或树脂粒子与半导体芯片的凸点接触时,通过破坏表面的树脂覆盖层,来确保其导电性的导通。
在此,说明使用了现有的各向异性导电膜的半导体芯片的代表性的安装例。图8是示出利用现有的各向异性导电膜的半导体芯片的安装状态的剖面图,(1)是示出利用现有的各向异性导电膜的半导体芯片的热压接状态的剖面图,(2)是示出利用现有的各向异性导电膜在有翘曲的基板上安装了半导体芯片的状态的剖面图。如图8(1)中所示,首先在基板2的设置了布线图形21上粘贴各向异性导电膜3。其次,在各向异性导电膜3上放置半导体芯片1,使得在半导体芯片1的电极上形成的凸点11与布线图形21相对。再者,利用加热加压工具51,一边从与设置了凸点11的面的相反一侧的面对半导体芯片1进行加热,一边向箭头A的方向按压。
通过加热,各向异性导电膜3的流动性提高,充填凸点11和布线图形21的周围的空间,进而,从半导体芯片1与基板2的粘接面向外部流出,粘附到半导体芯片1的侧面。另一方面,导电性粒子36的一部分在被夹住的状态下介于凸点11与布线图形21之间。
在该热压接之后,各向异性导电膜3的硬化一结束,就由各向异性导电膜3将半导体芯片1与基板2粘接在一起。特别是,附着于半导体芯片1的侧面的各向异性导电膜3形成镶边(fillet)34,使半导体芯片1与基板2的机械性连接变得牢固。此外,夹在凸点11与布线图形21之间的导电性粒子36起到作为半导体芯片1与基板2的导通媒体的作用。
但是,在以上已说明的那样的现有技术中发生了以下那样的问题。
即,在各向异性导电膜3的流动性比较大的情况下,在利用加热加压工具51对半导体芯片1进行加热、加压时,不仅附着于半导体芯片1的侧面、而且如图8(1)的已附着的部分35所示,因过度地流动而附着到加热加压工具51上。如果频繁地发生各向异性导电膜3的一部分附着于加热加压工具51上的情况,则当然必须与此相应而频繁地进行加热加压工具51的清洗,对半导体芯片进行热压接的工序的管理负担加重。
此外,在各向异性导电膜3的流动性比较小的情况下,如图8(2)中所示,即使利用加热加压工具51对半导体芯片1进行加热、加压,树脂也容易遗留在凸点11与布线图形21之间,在基板2上存在翘曲的情况下,各向异性导电膜与基板不密接,如点接触状态部分39所示,一部分凸点11与布线图形21变成点接触等,在凸点11的连接电阻方面出现离散性。根据情况,发生不能导电性地连接凸点11与布线图形21的情况。
发明内容
本发明的目的在于,为了解决上述的现有技术的缺点,提供下述一种各向异性导电膜,其中,在能充分地得到基板与半导体芯片的导电性的连接的同时,可防止各向异性导电膜附着于加热加压工具上,由此,能可靠地进行半导体芯片与基板的导电性的连接,此外,该工序的管理变得容易。
此外,其目的在于,提供一种使用了该各向异性导电膜的半导体装置。
为了达到上述目的,与本发明的第1方面有关的各向异性导电膜粘接半导体芯片与基板,同时成为上述半导体芯片与上述基板的电导通媒体,成为层叠了含有导电性粒子而构成的至少1层第1层和具有其流动性比上述第1层的流动性高的特性的至少1层第2层而构成的结构。
按照上述那样构成的与本发明的第1方面有关的各向异性导电膜,可对第1层和第2层的加热时的流动性设置差别。因此,使第1层的流动性低,使其较硬,由此,在将半导体芯片热压接到基板上时,可防止导电性粒子从半导体芯片与基板之间流出,可使介于半导体芯片的电极与基板的电极之间的导电性粒子的数目增加。另一方面,使第2层的流动性比第1层的流动性高,使其较软,由此,在将半导体芯片热压接到基板上时,容易从半导体芯片与基板之间流出,不妨碍芯片电极与基板电极的接触,同时,可使其附着于半导体芯片的侧面,形成镶边。
再者,由于与现有的各向异性导电膜相比,可减少从半导体芯片与基板之间流出的树脂的量,故可防止各向异性导电膜附着于加热加压工具上。
其结果,既可充分地确保半导体芯片与基板的机械性连接,又可提高导电性的连接的可靠性,同时,半导体芯片与基板的连接工序的管理变得容易。
再有,为了减少附着于半导体芯片的侧面的各向异性导电膜的量,上述的各向异性导电膜的厚度最好与现有的各向异性导电膜的厚度相等。此外,如果在导电性粒子含有层中包含的导电性粒于的密度与现有的各向异性导电膜的密度相等,则由于每同一容积中的导电性粒子数与以往相比减少,故作为半导体芯片与基板的导通媒体的功能下降。因此,最好使该密度与现有的各向异性导电膜相比稍高。
此外,将与本发明的第2方面有关的各向异性导电膜作成在上述第1层上形成上述第2层而构成的结构。
按照上述那样构成的与本发明的第2方面有关的各向异性导电膜,由于在第1层与半导体芯片的有源元件形成面和基板的布线图形形成面之间介入第2层,故可减少第1层中包含的导电性粒子与有源元件形成面的没有形成凸点的区域和布线图形形成面的没有形成布线图形的区域直接接触的情况。因此,由于即使使用镍粒子等的具有尖锐的凸部的金属粒子,也能减少对有源元件形成面和布线图形形成面的上述区域造成损伤的情况,故可扩展导电性粒子的材料选择的余地。
再者,通过使2个第2层分别与基板和半导体芯片相接,流动性高的第2层根据有源元件形成面和布线图形形成面的的凹凸和翘曲而流动,可实现各向异性导电膜与半导体芯片和基板的充分的密接。其结果,既可充分地确保半导体芯片与基板的机械性连接,又可提高导电性的连接的可靠性。
此外,与本发明的第3方面有关的各向异性导电膜成为在2个上述第2层之间夹住上述第1层而构成的结构。
按照上述那样构成的与本发明的第3方面有关的各向异性导电膜,由于第2层介于第1层与半导体芯片的有源元件形成面及基板的布线图形形成面之间,故可减少第1层中包含的导电性粒子与有源元件形成面的没有形成凸点的区域和布线图形形成面的没有形成布线图形的区域直接接触的情况。因此,由于即使使用镍粒子等的具有尖锐的凸部的金属粒子,也能减少对有源元件形成面和布线图形形成面的上述区域造成损伤的情况,故可扩展导电性粒子的材料选择的余地。
此外,与本发明的第4方面有关的各向异性导电膜成为上述第1层的厚度被形成得比上述第2层厚的结构。
按照上述那样构成的与本发明的第4方面有关的各向异性导电膜,由于可适度地确保第1层中含有的导电性粒子相互间的间隔,故可防止导电性粒子在串接状态下介于半导体芯片的凸点间而引起短路的情况。另外,可将附着于半导体芯片的侧面的各向异性导电膜抑制到最小限度的范围内。
此外,与本发明的第5方面有关的各向异性导电膜成为由流动性低的材料形成上述第1层的结构。
按照上述那样构成的与本发明的第5方面有关的各向异性导电膜,能可靠地抑制导电性粒子的过度的流动。
此外,与本发明的第6方面有关的各向异性导电膜成为上述流动性高的材料含有其密度比上述流动性低的材料的密度低的上述导电性粒子而构成的结构。
按照上述那样构成的与本发明的第6方面有关的各向异性导电膜,由于流动性高的材料也有助于半导体芯片与基板的导电性的连接,故可更加可靠地确保其导电性的连接。
此外,与本发明的第7方面有关的各向异性导电膜成为在上述第1层或上述第2层的至少某一方的边缘部上设置了其流动性比上述第2层的流动性低的带状体而构成的结构。
按照上述那样构成的与本发明的第7方面有关的各向异性导电膜,由于带状体防止第2层的过度的流动,故可防止形成过分大的镶边。
而且,与本发明的第8方面有关的电路基板成为设置了本发明的第1方面至第7方面的任一方面中所述的各向异性导电膜而构成的结构。
按照上述那样构成的与本发明的第8方面有关的电路基板,在对半导体芯片进行热压接时,可防止各向异性导电膜过分地流出到半导体芯片的周围以致附着于电路基板上的其它区域上。此外,能可靠地连接半导体芯片,可提供可靠性高的电路基板。
另外,与本发明的第9方面有关的电子装置作成具备本发明的第8方面所述的电路基板而构成的结构。
按照上述那样构成的与本发明的第9方面有关的电子装置,由于使用半导体芯片安装的可靠性高的电路基板,故可提高电子装置本身的可靠性。
再者,与本发明的第10方面有关的半导体装置是具备利用各向异性导电膜安装了半导体芯片的基板的半导体装置,其中,将上述各向异性导电膜作成层叠了含有导电性粒子而构成的至少1层第1层和具有其流动性比上述第1层的流动性高的特性的至少1层第2层来构成的结构。
按照上述那样构成的与本发明的第10方面有关的半导体装置,可对第1层和第2层的加热时的流动性设置差别。因此,使第1层的流动性低,使其较硬,由此,在将半导体芯片热压接到基板上时,可防止导电性粒子从半导体芯片与基板之间流出,可使介于半导体芯片的电极与基板的电极之间的导电性粒子的数目增加。另一方面,使第2层的流动性比第1层的流动性高,使其较软,由此,在将半导体芯片热压接到基板上时,容易从半导体芯片与基板之间流出,不妨碍芯片电极与基板电极的接触,同时,可使其附着于半导体芯片的侧面,形成镶边。
此外,与本发明的第11方面有关的半导体装置是在上述第1层上形成上述第2层而构成的结构。
按照上述那样构成的与本发明的第11方面有关的半导体装置,在将半导体芯片热压接到基板上时,可使与半导体芯片相接的第2层同时发挥下述2种作用,即,既充填半导体芯片的有源元件形成面附近的空间、又在半导体芯片的侧面上形成镶边以提高半导体芯片的连接性的作用和使导电性粒子滞留在半导体芯片与基板之间来确保导电性的连接的作用。
再者,关于在上述各装置中所述的基板的材料,可以是使用了塑料基板、柔性基板等的有机系列材料的基板、或使用了陶瓷基板等的无机系列材料的基板的任一种基板。
附图说明
图1是示出在基板与半导体芯片之间配置了与本发明的第1实施形态有关的各向异性导电膜的结构的剖面图。
图2是示出在基板与半导体芯片之间配置了与本发明的第2实施形态有关的各向异性导电膜的结构的剖面图。
图3是示出使用了与本发明的第1实施形态有关的各向异性导电膜安装了半导体芯片的状态的剖面图。
图4是示出在与本发明的第1和第2实施形态有关的各向异性导电膜中设置了以低浓度掺入导电性粒子的层来代替非导电层的状态的剖面图。
图5是示出与本发明的第1实施形态有关的各向异性导电膜的变形例的斜视图。
图6是示出与本发明的第2实施形态有关的各向异性导电膜的变形例的斜视图。
图7是示出在与本发明的第1和第2实施形态有关的各向异性导电膜中以框状设置了带状体的情况的斜视图。
图8是示出利用现有的各向异性导电膜半导体芯片的安装状态的剖面图,(1)是示出利用现有的各向异性导电膜的半导体芯片的热压接状态的剖面图,(2)是示出利用现有的各向异性导电膜在有翘曲的基板上安装了半导体芯片的状态的剖面图。
图9是利用与本发明的某一实施形态有关的各向异性导电膜安装了半导体芯片的电路基板的说明图。
图10是与本发明的实施形态有关的笔记本型个人计算机的说明图。
图11是与本发明的实施形态有关的携带电话机的说明图。
具体实施方式
以下,参照附图详细地说明本发明的优选实施形态。
图1是示出在基板与半导体芯片之间配置了与本发明的第1实施形态有关的各向异性导电膜的结构的剖面图。此外,图2是示出在基板与半导体芯片之间配置了与本发明的第2实施形态有关的各向异性导电膜的结构的剖面图。此外,图3是示出使用了与本发明的第1实施形态有关的各向异性导电膜安装了半导体芯片的状态的剖面图。此外,图4是示出在与本发明的第1和第2实施形态有关的各向异性导电膜中设置了以低浓度掺入导电性粒子的层来代替非导电层的状态的剖面图。此外,图5是示出与本发明的第1实施形态有关的各向异性导电膜的变形例的斜视图。此外,图6是示出与本发明的第2实施形态有关的各向异性导电膜的变形例的斜视图。此外,图7是示出在与本发明的第1和第2实施形态有关的各向异性导电膜中以框状设置了带状体的情况的斜视图。此外,图9是利用与本发明的某一实施形态有关的各向异性导电膜安装了半导体芯片的电路基板的说明图。图10是与本发明的实施形态有关的笔记本型个人计算机的说明图。图11是与本发明的实施形态有关的携带电话机的说明图。
在本发明的第1实施形态中,如图1中所示,将各向异性导电膜3作成使由掺入了导电性粒子36的树脂构成的导电性粒子含有层31和由其流动性比导电性粒子含有层31的流动性高的树脂构成且没有掺入导电性粒子36的非导电层32成为一体而层叠的结构。此外,这些厚度的合计与现有的各向异性导电膜相等。
此外,导电性粒子含有层31以分子量大的树脂作为材料。因此,由于其流动性比非导电层32的流动性低、较硬,故即使被加热,仍保持其流动性较低的状态。因而,即使对半导体芯片1施加按压力,导电性粒子含有层31也具有难以从半导体芯片1与基板2之间被压出、难以附着于半导体芯片1的侧面的性质。由于非导电层32以分子量小的树脂作为材料,故具有其流动性比导电性粒子含有层31的流动性高、较软的特性。因而,非导电层32在其热压接时在半导体芯片1与基板2之间的空间中顺畅地流动。
将具有以上的结构的各向异性导电膜3设置成导电性粒子含有层31位于基板2一侧,非导电层32位于半导体芯片1一侧。通过以这种方式进行设置,在将半导体芯片1热压接到基板2上时,与半导体芯片相接的导电性粒子含有层31一边充填半导体芯片1的凸点11的周围的间隙等,一边与半导体芯片1的有源元件形成面密接。同时,在半导体芯片的侧面上形成镶边,发挥提高半导体芯片的连接性的作用。另外,导电性粒子含有层31起到使导电性粒子36滞留在半导体芯片与基板之间以确保半导体芯片1与基板2的导电性的连接的作用。
关于上述作用,更详细地进行说明。在进行了半导体芯片1与基板2的热压接时,各向异性导电膜3成为被夹持于在半导体芯片1的未图示的电极焊区上形成的凸点11与在基板2上形成的布线图形21之间的状态。此时,由于形成导电性粒子含有层31的树脂较硬,故在凸点11与布线图形21之间按原样遗留导电性粒子含有层31的一部分。因而,即使在热压接之后,被掺入到导电性粒子含有层31中的导电性粒子36也不从凸点11与布线图形21之间选出,按被夹持的状态遗留下来,因此,可充分地确保半导体芯片1与基板2的电导通。
此外,如上所述,非导电层32的流动性比导电性粒子含有层31的流动性高,较软,在该热压接时,在半导体芯片1与基板2的空间中顺畅地流动。因此,由于根据半导体芯片1和基板2的粘接面的凹凸、基板2的翘曲而流动,以充填间隙的方式而流入,故可提高各向异性导电膜3与半导体芯片1和基板2的密接性。再者,由于从半导体芯片与基板之间流出,形成图3中示出的镶边34,故可使半导体芯片1与基板2的机械性连接变得牢固。因而,附着于半导体芯片1的侧面上且成为镶边34这一点几乎都来源于非导电层32,故与现有的各向异性导电膜相比,可抑制附着于侧面上的量。
再有,导电性粒子含有层31由环氧系列的树脂形成。该树脂构成以固形树脂为75重量%~99重量%和液状环氧系列树脂1重量%~25重量%的比率来配制。
此外,非导电层32由环氧系列的树脂形成。该树脂构成以固形树脂为50重量%~75重量%和液状环氧系列树脂25重量%~50重量%的比率来配制。
另外,为了减少从半导体芯片与基板之间流出的量、充分地确保夹持于凸点11与布线图形21之间而介入的导电性粒子36的量,最好使导电性粒子含有层31的厚度91比非导电层32的厚度92薄。具体地说,如果考察上述那样的双方的层的特性,则使非导电层32的厚度92比导电性粒子含有层31的厚度91稍厚的结构是较为理想的。例如,最好使导电性粒子含有层31的厚度91为各向异性导电膜3整体的厚度的40%左右,使非导电层32的厚度92为60%左右,具体地说,最好分别为20μm左右、30μm左右。
再者,通过根据半导体芯片1的厚度以及使各向异性导电膜的面积对于半导体芯片1的设置了凸点11的面的面积为相同等诸条件,适当地调整2个层的厚度,也可设定各向异性导电膜的特性(更硬一些、或软一些等)。
如以上所说明的那样,与本发明的第1实施形态有关的各向异性导电膜,通过作成硬的导电性粒子含有层31和与导电性粒于含有层31相比较软的非导电层32的2层结构,可防止导电性粒子从半导体芯片与基板之间流出。此外,与现有的各向异性导电膜中的整体由软的树脂构成的各向异性导电膜相比,由于能减薄软的层(非导电层32)、可减少从半导体芯片与基板之间流出的量,故可抑制各向异性导电膜附着于加热加压工具的情况。此外,与整体由硬的树脂构成的各向异性导电膜相比,由于非导电层32的流动性高、顺畅地在半导体芯片1与基板2之间的空间中流动,充填间隙,故半导体芯片1与基板2的粘接性良好。
再者,与现有的各向异性导电膜中的整体由软的树脂构成的各向异性导电膜相比,在热压接时,在凸点11与布线图形21之间夹持较厚的树脂,有时影响导电性的连接,但在本实施形态的情况下,与现有的各向异性导电膜相比,硬的层(导电性粒子含有层31)较薄,能可靠地确保导电性的连接。此外,即使将导电性粒子36定为金属粒子,由于半导体芯片1的形成了凸点11的面与导电性粒子含有层31不直接接触,故导电性粒子36也不会对半导体芯片1的形成了凸点11的面造成损伤。即,通过由性质不同的2种树脂形成各向异性导电膜3,各向异性导电膜3成为同时具有硬软两方的性质的各向异性导电膜,没有与现有技术有关的各向异性导电膜存在的缺点。
其次,叙述使用与本发明的第1实施形态有关的各向异性导电膜将半导体芯片连接到基板上的顺序。首先,在使导电性粒子含有层31朝向基板2一侧、使非导电层32朝向半导体芯片一侧的状态下进行粘贴,使其覆盖连接半导体芯片1的基板2的布线图形21。其次,在使凸点11与布线图形21相对的状态下,将半导体芯片1放置在各向异性导电膜3上。
其次,利用图8(1)中所述的加热加压工具51,一边在约180℃~200℃的温度下对半导体芯片1的背面一侧进行加热,一边对其加压。此时,如上所述,导电性粒子含有层31不太流动,遗留在半导体芯片1与基板2之间,非导电层32流动,与半导体芯片1和基板2密接,同时从半导体芯片1与基板2之间流出,附着于半导体芯片1的侧面上。
如果以这种方式对半导体芯片1进行热压接,则各向异性导电膜3硬化,如图3中所示,导电性粒子在充分地被夹住的状态下介于凸点11与布线图形21之间,此外,在半导体芯片1的侧面上形成不附着于加热加压工具51的程度的大小的镶边34。
再有,关于本发明的第1实施形态,为了一边使非导电层32的流动性维持得足够高、一边防止非导电层32过分地附着于半导体芯片的侧面上,可作成以下所述的那样的结构。即,如图5(A)中所示,可在导电性粒子含有层31和非导电层32的两端部设置带状体38。带状体38由与导电性粒子含有层31同等程度或其以上的硬的树脂构成。因此,在对半导体芯片1进行热压接的情况下,由于被设置在其两端部的带状体38抑制非导电层32的流动,故即使非导电层32的流动性高、也不会过分地附着于半导体芯片的侧面上。
再有,在设置带状体38的情况下,导电性粒子含有层31和非导电层32的宽度最好与被安装的半导体芯片的宽度大体相等。如果这样做,则在对半导体芯片1进行热压接时,带状体38起到塞住半导体芯片与基板之间的空间的盖的作用,抑制非导电层32从半导体芯片与基板之间的空间流出。
此外,带状体38的形状不限于图5(A)中所示的形状,只要形成为能抑制非导电层32的流动即可。例如,可如图5(B)或图5(C)中所示那样来形成。再者,可如图7中所示,将带状体形成为框状,作成框体40,在框体40内设置各向异性导电膜3。
其次,说明与本发明的第2实施形态有关的各向异性导电膜。如图2中所示,在该实施形态中,在各向异性导电膜3中设置了2个非导电层32。如图示那样,以在该2个非导电层32之间夹住导电性粒子含有层31的方式进行了层叠。再有,导电性粒子含有层31和非导电层32的材料等,与第1实施形态中有关的材料相同。
在本实施形态的情况下,与上述实施形态相比,其结构变得复杂,但由于在软的非导电层32与半导体芯片1的形成了凸点11的面和基板2的形成了布线图形21的面双方相接的状态下对半导体芯片1进行热压接,故可根据基板2的凹凸充分地流动,与硬的导电性粒子含有层31与基板2相接的上述实施形态的情况相比,各向异性导电膜3与基板2良好地密接。因此,更牢固地粘接半导体芯片1与基板2,其连接的可靠性更高。
再有,在本实施形态中,关于导电性粒子含有层31的厚度93和非导电层32的厚度94,如果考察双方的层的特性,则最好使非导电层32的厚度94比导电性粒子含有层31的厚度93稍厚,导电性粒子含有层31的厚度93为各向异性导电膜3整体的厚度的40%左右,非导电层32的厚度94为60%左右。特别是,最好使导电性粒子含有层31的厚度93为20μm左右,非导电层32的厚度94(1层)为15μm左右(如果将2个非导电层32的厚度加起来,则为30μm左右)。
此外,与本发明的第1实施形态的情况相同,如图6(A)、(B)、(C)所示,可在导电性粒子含有层31和非导电层32的两端部上设置带状体38。
此外,在上述各实施形态中,最好使各向异性导电膜3的面积与半导体芯片1的有源元件形成面的面积大体相等,或比其稍大。通过定成这样的大小,即使各向异性导电膜3的粘贴位置多少有些偏移,也可避免对半导体芯片1的安装产生影响。其结果,不那么要求各向异性导电膜3的粘贴位置的准确性,各向异性导电膜3的粘贴工序的管理变得容易。同时,由于各向异性导电膜3的面积没有不必要的增大,故不会在半导体芯片1的周围形成过分大的镶边。
再有,与上述各实施形态有关的各向异性导电膜3作成对半导体芯片与基板的导电性的连接有贡献的部分只是导电性粒子含有层31的结构,但如图4(A)、(B)、(C)中所示,也可设置导电性粒子低含有层37来代替非导电层32。与导电性粒子含有层31相比,导电性粒子低含有层37的导电性粒子的含有量低,由与非导电层32相同的树脂构成。如果这样来构成,则在导电性粒子低含有层37中含有的导电性粒子对半导体芯片与基板的导电性的连接也有贡献。再有,最好将在导电性粒子低含有层37中含有的导电性粒子密度设定为不使半导体芯片的凸点11相互间短路的范围内。
此外,在上述的各实施形态中,掺入到各向异性导电粘接剂中的导电性粒子可以是金属粒子、或对树脂制的粒子进行了金属电镀的粒子等的任一种,不管其材料、形状如何。此外,也可不在半导体芯片的电极上设置凸点,而是在基板的电极上设置凸点。
此外,在上述的各实施形态中,以在半导体芯片的形成了电极的面上的全部4边上设置了电极的情况为例进行了讨论,但所设置的电极的配置不限于此,也可只在2边或在该面的整个面上设置了电极。
此外,关于半导体芯片的电极的配置,可以是配置在有源元件形成面的整个周边上,或在其一部分上、或在该面的整个面上等之任一种。
此外,与上述的各实施形态有关的各向异性导电膜可用于半导体芯片与基板的连接以外的目的。
如上所述,在本发明的实施形态中,在将半导体芯片热压接到基板上时,各向异性导电膜不会附着于加热加压工具上。此外,由于可在半导体芯片的侧面上形成适度的大小的镶边,故半导体芯片与基板的机械性连接的可靠性提高。另外,由于导电性粒子充分地介于半导体芯片电极与基板电极之间,故可充分地确保与基板的导电性的连接。
再者,图9示出作为利用以上已说明的各向异性导电膜安装了半导体芯片的例子。即,图9示出了利用与本发明的某一实施形态有关的各向异性导电膜4安装了半导体芯片110的电路基板100。再有,一般使用例如玻璃环氧基板等有机系列基板作为电路基板100。在电路基板100上形成了例如由铜构成的键合部,使其成为所希望的电路。而且,通过以机械方式连接键合部与半导体芯片110的外部电极,可谋求其电导通。
再有,可将半导体芯片110的安装面积减小到用裸芯片安装的面积,如果将该电路基板100用于电子装置,则可谋求电子装置本身的小型化。此外,在相同面积内,可确保更大的安装空间,也可谋求高性能化。
而且,作为具备该电路基板100的电子装置,图10中示出了笔记本型个人计算机120,图11中示出了携带电话机130。
产业上利用的可能性
如以上所叙述的那样,本发明是这样一种各向异性导电膜,该各向异性导电膜粘接半导体芯片与基板,同时成为上述半导体芯片与上述基板的电导通媒体,其特征在于:层叠含有导电性粒子而构成的至少1层第1层和具有其流动性比上述第1层的流动性高的特性的至少1层第2层而构成,第2层充分地流动,充填半导体芯片的电极和有源元件形成面的周围的空间,提高半导体芯片与基板的粘接性。由于第1层的流动性相对地较低,故导电性粒子滞留在半导体芯片的电极与基板的布线之间,提高了两者的导电性的连接的可靠性。于是,提高了使用各向异性导电膜的半导体装置的可靠性。
Claims (11)
1.一种各向异性导电膜,该各向异性导电膜粘接半导体芯片与基板,同时成为上述半导体芯片与上述基板的电导通媒体,其特征在于:
层叠含有导电性粒子而构成的第1层和具有其流动性比上述第1层的流动性高的特性的第2层而构成。
2.如权利要求1中所述的各向异性导电膜,其特征在于:
在上述第1层上形成上述第2层而构成。
3.如权利要求1中所述的各向异性导电膜,其特征在于:
在2个上述第2层之间夹住上述第1层而构成。
4.如权利要求2或3中所述的各向异性导电膜,其特征在于:
上述第1层的厚度被形成得比上述第2层厚。
5.如权利要求1至权利要求4的任一项中所述的各向异性导电膜,其特征在于:
由流动性低的材料形成上述第1层。
6.如权利要求2或3中所述的各向异性导电膜,其特征在于:
上述第2层含有其密度比上述第1层的密度低的上述导电性粒子。
7.如权利要求1至权利要求6的任一项中所述的各向异性导电膜,其特征在于:
在上述第1层或上述第2层的边缘部上设置了其流动性比上述第2层的流动性低的带状体。
8.一种电路基板,其特征在于:
在半导体芯片与基板之间设置了权利要求1至权利要求7的任一项中所述的各向异性导电膜。
9.一种电子装置,其特征在于:
具备权利要求8中所述的电路基板。
10.一种半导体装置,该半导体装置具备利用各向异性导电膜安装了半导体芯片的基板,其特征在于:
层叠含有导电性粒子而构成的第1层和具有其流动性比上述第1层的流动性高的特性的第2层来构成上述各向异性导电膜。
11.如权利要求10中所述的半导体装置,其特征在于:
在上述第1层上形成上述第2层而构成。
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JP34308198 | 1998-12-02 | ||
JP343081/1998 | 1998-12-02 |
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CN1135610C true CN1135610C (zh) | 2004-01-21 |
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US (1) | US6426566B1 (zh) |
KR (1) | KR100386758B1 (zh) |
CN (1) | CN1135610C (zh) |
TW (1) | TW457603B (zh) |
WO (1) | WO2000033375A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101681858B (zh) * | 2007-06-06 | 2012-01-11 | 索尼化学&信息部件株式会社 | 电子部件的连接方法及接合体 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7244675B2 (en) * | 2000-03-23 | 2007-07-17 | Sony Corporation | Electrical connection materials and electrical connection method |
US20020098620A1 (en) * | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
US6651319B2 (en) * | 2001-09-07 | 2003-11-25 | Visteon Global Technologies, Inc. | Compliant standoff for low pressure sensing device |
US20040191955A1 (en) * | 2002-11-15 | 2004-09-30 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
US20050012225A1 (en) * | 2002-11-15 | 2005-01-20 | Choi Seung-Yong | Wafer-level chip scale package and method for fabricating and using the same |
US7265994B2 (en) * | 2003-01-31 | 2007-09-04 | Freescale Semiconductor, Inc. | Underfill film for printed wiring assemblies |
US6905342B2 (en) * | 2003-04-01 | 2005-06-14 | Hewlett-Packard Development Company, L.P. | Protected electrical interconnect assemblies |
CN1325983C (zh) * | 2003-05-27 | 2007-07-11 | 友达光电股份有限公司 | 液晶显示面板的封装结构及其制作工艺 |
US7019403B2 (en) * | 2003-08-29 | 2006-03-28 | Freescale Semiconductor, Inc. | Adhesive film and tacking pads for printed wiring assemblies |
US8604613B2 (en) * | 2003-11-14 | 2013-12-10 | Industrial Technology Research Institute | Electronic assembly having a multilayer adhesive structure |
US7960830B2 (en) * | 2003-11-14 | 2011-06-14 | Industrial Technology Research Institute | Electronic assembly having a multilayer adhesive structure |
TWI393226B (zh) * | 2004-11-04 | 2013-04-11 | Taiwan Semiconductor Mfg | 基於奈米管之填充物 |
US8017873B2 (en) * | 2008-03-03 | 2011-09-13 | Himax Technologies Limited | Built-in method of thermal dissipation layer for driver IC substrate and structure thereof |
KR20100079183A (ko) * | 2008-12-30 | 2010-07-08 | 주식회사 동부하이텍 | 반도체 패키지 장치와 그 제조 방법 |
FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
JP5400545B2 (ja) * | 2009-09-25 | 2014-01-29 | 積水化学工業株式会社 | 異方性導電材料、接続構造体の製造方法及び接続構造体 |
KR20140100511A (ko) * | 2011-12-16 | 2014-08-14 | 아사히 가세이 이-매터리얼즈 가부시키가이샤 | 이방 도전성 필름 부착 반도체칩, 이방 도전성 필름 부착 반도체 웨이퍼, 및 반도체 장치 |
DE112011105967T5 (de) * | 2011-12-20 | 2014-09-25 | Intel Corporation | Mikroelektronisches Gehäuse und gestapelte mikroelektronische Baugruppe und Rechensystem mit denselben |
JP2013243344A (ja) * | 2012-04-23 | 2013-12-05 | Nichia Chem Ind Ltd | 発光装置 |
CN104698689B (zh) * | 2015-04-07 | 2017-07-14 | 京东方科技集团股份有限公司 | 一种各向异性导电胶膜、显示装置及其返修方法 |
KR102422077B1 (ko) * | 2015-11-05 | 2022-07-19 | 삼성디스플레이 주식회사 | 도전성 접착 필름 및 이를 이용한 전자기기의 접착 방법 |
WO2018125164A1 (en) * | 2016-12-29 | 2018-07-05 | Intel Corporation | Semiconductor package having package substrate containing non-homogeneous dielectric layer |
CN112968116A (zh) * | 2020-10-15 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | 芯片的键合方法和系统、存储介质、电子装置 |
CN116079647A (zh) * | 2023-01-16 | 2023-05-09 | 昆山联滔电子有限公司 | 一种导电膜安装设备及导电膜安装设备的使用方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5001542A (en) * | 1988-12-05 | 1991-03-19 | Hitachi Chemical Company | Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips |
WO1996042107A1 (en) * | 1995-06-13 | 1996-12-27 | Hitachi Chemical Company, Ltd. | Semiconductor device, wiring board for mounting semiconductor and method of production of semiconductor device |
JPH1013002A (ja) * | 1996-06-20 | 1998-01-16 | Matsushita Electric Ind Co Ltd | 半導体素子の実装方法 |
JPH10125725A (ja) * | 1996-10-18 | 1998-05-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH10270624A (ja) * | 1997-03-27 | 1998-10-09 | Toshiba Corp | チップサイズパッケージ及びその製造方法 |
JPH11135567A (ja) * | 1997-10-30 | 1999-05-21 | Toshiba Corp | 異方性導電膜、半導体装置の製造方法 |
JPH11306861A (ja) * | 1998-04-09 | 1999-11-05 | Minnesota Mining & Mfg Co <3M> | 導電性接着剤組成物、それを有する異方導電性接着フィルム及びそのフィルムを用いた接続方法 |
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CN101681858B (zh) * | 2007-06-06 | 2012-01-11 | 索尼化学&信息部件株式会社 | 电子部件的连接方法及接合体 |
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US6426566B1 (en) | 2002-07-30 |
CN1289453A (zh) | 2001-03-28 |
KR100386758B1 (ko) | 2003-06-09 |
WO2000033375A1 (en) | 2000-06-08 |
TW457603B (en) | 2001-10-01 |
KR20010034451A (ko) | 2001-04-25 |
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