CN1235375A - 半导体芯片的安装结构体、液晶装置和电子装置 - Google Patents

半导体芯片的安装结构体、液晶装置和电子装置 Download PDF

Info

Publication number
CN1235375A
CN1235375A CN99104085A CN99104085A CN1235375A CN 1235375 A CN1235375 A CN 1235375A CN 99104085 A CN99104085 A CN 99104085A CN 99104085 A CN99104085 A CN 99104085A CN 1235375 A CN1235375 A CN 1235375A
Authority
CN
China
Prior art keywords
mentioned
semiconductor chip
liquid
substrate
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN99104085A
Other languages
English (en)
Other versions
CN100370603C (zh
Inventor
内山宪治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display West Inc
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1235375A publication Critical patent/CN1235375A/zh
Application granted granted Critical
Publication of CN100370603C publication Critical patent/CN100370603C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/2939Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29399Coating material
    • H01L2224/294Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29438Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Wire Bonding (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明的课题是在使用各向异性导电膜(ACF)等的粘接剂将半导体芯片安装在基板上的安装结构体中防止在粘接剂中产生残留应力以提高电极端子间的连接可靠性。该安装结构体包括具备多个凸点16的半导体芯片6和具备多条输出布线11和输入端子12的电路基板3。在电路基板3中被布线11和端子12的接合区部分包围的区域内分散地配置多个贯通孔10,使压接处理时成为多余的ACF4通过这些贯通孔而逸出,由此来防止在ACF4中产生大的内部应力。

Description

半导体芯片的安装结构体、液晶装置和电子装置
本发明涉及通过使用ACF(各向异性导电膜)等的粘接剂将半导体芯片粘接到基板上而构成的半导体芯片的安装结构体,特别是涉及对半导体芯片中设置的多个凸点(bump)与在基板上设置的多个接合区(land)进行导电性连接的结构的安装结构体。此外,本发明涉及使用了该安装结构的液晶装置和使用了该液晶装置的电子装置。
目前,在携带电话机、携带信息终端等的电子装置中广泛地使用了液晶装置。在很多情况下,为了显示文字、数字、图形等的可视信息而使用了该液晶装置。
一般来说,在该液晶装置中,具有由一对透先性基板夹住的液晶,通过控制施加到该液晶上的电压来控制该液晶的取向,因而对入射到该液晶上的光进行调制。在该液晶装置中,为了控制施加到该液晶上的电压,必须使用液晶驱动用IC、即半导体芯片,将该IC直接地或通过基板间接地连接到上述透光性基板上。
现在,如果考虑通过基板将液晶驱动用IC连接到液晶装置的透光性基板上的情况,则例如,如图9中所示,通过使用ACF53将液晶驱动用IC51连接到基板52上来形成安装结构体58,再使用FPC(柔性印刷基板)54等的连接部件将该安装结构体58内的基板52连接到液晶装置56的透光性基板57a上。液晶装置56的构成包括一对透光性基板57a、57b和封入这些基板之间的液晶59。在基板57a、57b的外侧表面上粘贴偏振片60,还在基板57a的表面上设置反射板61。
但是,在现有的安装结构体58中,一般来说,如图10中所示,在基板52中用于安装液晶驱动用IC51的区域A是与除此以外的表面区域相同的平坦面。其结果,如果ACF53的量过多的话,则在ACF53的压接连接时在该ACF53的内部产生大的残留应力,因此,存在随着时间的推移产生连接不良的问题。
再有,在图10中符号62表示相对于IC51的输入布线,符号63表示来自IC51的输出布线。这些布线实际上形成多条,但在图中示出这些布线的一部分,用点划线将剩下的部分省略。
本发明是鉴于上述的问题而完成的,其目的在于,在使用ACF等的粘接剂将液晶驱动用IC等的半导体芯片安装到基板上的安装结构体中提高电极端子间的连接可靠性。
(1)为了达到上述目的,与本发明有关的半导体芯片的安装结构体是包括具备多个凸点的半导体芯片和多个接合区的基板、同时通过使用粘接剂来连接上述半导体芯片和上述基板以便使这些凸点与这些接合区互相导通而构成的半导体芯片的安装结构体。而且,该安装结构体的特征在于,在上述基板中,在被上述多个接合区包围的区域内分散地配置多个贯通孔。
按照该半导体芯片的安装结构体,通过在其间夹住粘接剂的状态下将半导体芯片挤压到基板上,利用该粘接剂将半导体芯片固定在基板上。在这种情况下,在粘接剂的量过多时,在将半导体芯片挤压到基板上时多余的粘接剂进入贯通孔中,于是,不会在粘接剂的内部产生残留应力。其结果,能可靠地防止在连接部中随着时间的推移产生连接不良的情况。
再有,作为本发明的半导体芯片的安装结构,例如可考虑COB(板上的芯片)方式的安装结构或COF(FPC上的芯片)方式的安装结构等。COB方式的安装结构是例如在环氧基板等上安装半导体芯片的结构。此外,COF方式的安装结构是在具有柔性且较薄的基板、例如柔性印刷基板(FPC:柔性印刷基板)上安装半导体芯片的结构。
按照实开平3-39876号公报,公开了在片状部件而不是在半导体芯片的安装区域的内部设置贯通孔的技术。但是,在该处示出的贯通孔是为了容易形成片状部件的安装部的凹陷,其目的不是为了在粘接剂中不产生残留应力。因此,在该现有文献中没有示出在被与半导体芯片的凸点对应地配置在基板一侧的多个接合区包围的区域内形成贯通孔和在分散状态下配置这些多个贯通孔的技术要点。
本发明者对于本发明中在基板中形成的多个贯通孔的配置形态进行了模拟,得到了下述的结果。以下,考虑图7中示出的模型作为压接前的状态,考虑图8中示出的模型作为压接后的状态。在这些图中各符号具有以下的意义。
X、Y:液晶驱动用IC(即,半导体芯片)6的外形尺寸
x、y:凸点16的外形尺寸
h:凸点16的高度
n:凸点16的数目
t:ACF(即,粘接剂)4的厚度
T:基板3的厚度
H:接合区13的厚度
d:通孔(即,贯通孔)9的孔径
N:通孔9的孔数
(A)在将液晶驱动用IC6压接到基板3上时,由液晶驱动用IC6挤压的ACF4的体积V是:
V=X·Y·t……(1)
(B)在图8中示出的压接完了的状态下,被凸点16排出的ACF4的体积v1是:
v1=x·y·h·n……(2)
此外,在图8中示出的压接完了的状态下,被接合区13排出的ACF4的体积v2是:
v2=x·y·H·n……(3)
其中,为了简单起见,将接合区13的尺寸设定为与凸点16的尺寸相等。
(C)假定在压接时没有从IC芯片6的外形向外侧伸出的ACF4。因压接而成为多余的(即,被排出的)ACF4的体积v0是:
v0=X·Y·(t-h)+v1+v2……(4)
再有,在上式中,(t-h)表示因压接引起的ACF4的厚度的减少量。
(D)如果假定成为多余的体积v0的ACF4全部充填到基板3的孔9内,再假定孔9的总面积为S0,则
S0·T=v0
因而
S0={X·Y·(t-h)+v1+v2}/T……(5)
(E)在基板3中设置的孔9的总面积S0对液晶驱动用IC6的占有率R(%)是:
R=(S0/X·Y)×100……(6)
这里,不管孔9是圆孔、四角形孔、这些孔的组合、还是其它任意的形状都没有关系。
(F)例如,假定孔9为圆孔,再假定成为多余的体积v0的ACF4全部充填到该圆孔内,则下述的公式成立:
v0=(d/2)2·π·T·N……(7)
因而,
孔数N=v0/(d/2)2·7π·T
     ={X·Y·(t-h)+v1+v2}/(d/2)2·π·T
                   ……(8)
(G)模拟的结果如下表所示。【表1】
 R(%)     8.9     17.9     7.9     7.0     4.4     2.2     1.1     0.1
 X(μm)     3000     3000     3000     3000     3000     3000     3000     3000
 Y(μm)     10000     10000     10000     10000     10000     10000     10000     10000
 X(μm)     70     70     70     70     70     70     70     70
 y(μm)     70     70     70     70     70     70     70     70
 h(μm)     18     18     18     20     18     18     18     18
 n(个)     300     300     300     300     300     300     300     300
 t(μm)     35     35     25     35     35     35     35     27
 T(μm)     100     100     100     100     200     400     800     800
 H(μm)     9     0     0     9     9     9     9     9
 d(μm)     300     300     300     300     300     300     300     300
 N(个)     37.7     75.9     33.5     29.6     18.8     9.4     4.7     0.5
 R(%)     7.5     3.8     11.5     7.8
 X(μm)     3000     3000     3000     3000
 Y(μm)     10000     10000     10000     10000
 X(μm)     70     70     70     70
 y(μm)     70     70     70     70
 h(μm)     18     18     18     18
 n(个)     300     300     300     300
 t(μm)     28     28     20     30
 T(μm)     25     50     25     50
 H(μm)     9     9     0     9
 d(μm)     300     300     300     300
 N(个)     31.9     16.0     48.9     33.0
在上表中,R由上式(6)求出,N由上式(8)求出。此外,在上表中,T=100μm以上的数据涉及COB方式的安装结构,T=50μm以下的数据涉及COF方式的安装结构。
(H)在基板3中设置的孔9的占有率随液晶驱动用IC6的大小、凸点16的大小和数目、ACF4的厚度、基板3的厚度、接合区13的厚度等的组合而变化,但为了确保ACF4的连接可靠性,有必要使ACF4充分地充填在液晶驱动用IC6与基板3之间,也可选择适当的厚度的ACF4。
但是,在现实的压接操作中,有必要压接多种多样的部件的组合,要分别使用与这些多种多样的部件对应的的最佳的ACF4是困难的。与此不同,如果按照本申请的发明,则在ACF4的厚度厚的情况下,通过使多余的ACF4逸出到基板孔9中,可确保最佳的压接状态,因此,即使将ACF4的厚度的变动设定为一个小的范围内,也能适应多种类型的压接。
(2)如参照上述的模拟的结果,则基板孔9对液晶驱动用IC6(即,半导体芯片)的面积占有率R(%)在下述范围内是较为理想的:
    0%<R≤18%
利用该尺寸设定,能在进行压接时使粘接剂可靠地逸出到贯通孔中。
(3)基板孔9的面积占有率R(%)在下述范围内则更为理想:
    2%≤R≤10%
如按照该尺寸设定,则能在进行压接时使粘接剂可靠地逸出到贯通孔中,同时也能更多地留下用于形成布线图形的基板的面积。
(4)关于上述结构的半导体芯片的安装结构体,最好将设置在基板中的多个贯通孔设置在被多个接合区包围的区域的与中央部相比靠近这些接合区的位置上。如果这样做,则能可靠地使被凸点和接合区排出的全部粘接剂逸出到上述贯通孔中。
具体地说,在图8中,最好在IC芯片6的中央C与凸点16之间的距离D1的2/3以下的范围D2内设置贯通孔9。例如,如果将IC芯片6的宽度设为X=3mm(=3000μm),将从IC芯片6的端面到凸点16的内侧端面为止的距离设为D3=0.3mm,则下式成立:
D1=X/2-D3
  =3/2-0.3
  =1.2(mm)
因此,下式成立:
    D2=D1×2/3=0.8(mm)
即,在这种情况下,最好将贯通孔9设置在离凸点16的内侧端面的0.8mm的范围内。
(5)本发明中使用的基板可以由具备单一的布线层的基板形成,也可由包含利用多个导电性通孔互相进行导电性连接的多个布线层的基板构成。在使用具备这样的导电性通孔的基板的情况下,可将该基板中形成的导电性通孔用作使粘接剂逸出用的多个贯通孔。
目前,大多考虑将基板中形成的导电性通孔配置在IC芯片的安装区的外侧,但在进行在面积小的基板内形成高密度的布线图形的所谓精细安装的情况下,在IC芯片的安装区的的内部配置导电性通孔是非常有效的,在这样的图形配置时,如果将这些多个导电性通孔作为使粘接剂逸出用的贯通孔来利用,则是非常有效的。
(6)其次,与本发明有关的液晶装置是这样的液晶装置:它具有被一对透光性基板夹住的液晶,通过控制施加到该液晶上的电压来控制该液晶的取向,因而对入射到该液晶上的光进行调制。而且该液晶装置具有与上述一对透光性基板的至少一方粘接的半导体芯片的安装结构体,该安装结构体包括具备多个凸点的液晶驱动用IC和具备多个接合区的基板,同时通过使用粘接剂来连接上述液晶驱动用IC与上述基板以便使这些凸点与这些接合区互相导通而构成。而且,在上述基板中,在被上述多个接合区包围的区域内在分散的状态下配置多个贯通孔。
在制造该液晶装置时,通过在其间夹住粘接剂的状态下将液晶驱动用IC(即,半导体芯片)挤压到基板上,利用该粘接剂将液晶驱动用IC固定在基板上。在这种情况下,在粘接剂的量过多时,在将液晶驱动用IC压接到基板上时多余的粘接剂进入贯通孔中,于是,不会在粘接剂的内部产生残留应力。
(7)在上述(6)记载的液晶装置中,如果将贯通孔的合计面积对液晶驱动用IC的面积的占有率设为R,则R在下述范围内是较为理想的:
    0%<R≤18%
利用该尺寸设定,能在进行压接时使粘接剂可靠地逸出到贯通孔中。
(8)在上述(6)记载的液晶装置中,如果将贯通孔的合计面积对液晶驱动用IC的面积的占有率设为R,则R在下述范围内更为理想:
    2%≤R≤10%
如按照该尺寸设定,则能在进行压接时使粘接剂可靠地逸出到贯通孔中,同时也能更多地留下用于形成布线图形的基板的面积。
(9)关于上述(6)至(8)中记载的液晶装置,最好将用于使粘接剂逸出的贯通孔设置在被上述多个接合区包围的区域的与中央部相比靠近这些接合区的位置上。如果这样做,则能在将液晶驱动用IC压接到基板上时可靠地且自然地使被凸点和接合区排出的全部粘接剂逸出到贯通孔中。
(10)关于上述(6)至(9)中记载的液晶装置,基板可以是具备利用多个导电性通孔互相进行导电性连接的多个布线层的基板,在这种情况下,可由这些通孔来构成使粘接剂逸出用的多个贯通孔。如果这样做,则由于没有必要为了使粘接剂逸出而设置专用的贯通孔,故可将基板的面积作为布线区域等,可有效地加以利用。
(11)其次,与本发明有关的电子装置是包含液晶装置而构成的电子装置,其特征在于,该液晶装置是上述(6)至(10)中记载的液晶装置。作为这样的电子装置,例如可考虑携带电话机、携带信息终端等。
图1是将与本发明有关的半导体芯片的安装结构体的一实施例分解后示出的斜视图。
图2是示出图1的安装结构体的主要部分的斜视图。
图3是示出与本发明有关的液晶装置的一实施例的斜视图。
图4是示出图3示出的液晶装置的主要部分的剖面结构的剖面图。
图5是示出与本发明有关的电子装置的一实施例的斜视图。
图6是示出图5示出的电子装置的内部结构的主要部分的剖面图。
图7是示意性地示出与本发明有关的半导体芯片的安装结构体的特别是在安装完了前的状态的图。
图8是示意性地示出图7中示出的半导体芯片的安装结构体的在安装完了后的状态的图。
图9是示出具备半导体芯片的安装结构体的液晶装置的现有例的图。
图10是将图9中示出的半导体芯片的安装结构体分解后示出的斜视图。
(关于半导体芯片的安装结构体的实施例)
图1示出了与本发明有关的半导体芯片的安装结构体的一实施例。
在这里示出的的安装结构体1的构成包括:安装了片状电容器、片状电阻等所谓的电子片状部件2的电路基板3;由作为粘接剂的ACF(各向异性导电膜)4连接到电路基板3的表面上的液晶驱动用IC6;以及由ACF7连接到电路基板3的表面上的输入用电缆8。
电子片状部件2是构成用于驱动液晶装置的驱动电路用的电路部件。这些电子片状部件2例如可用焊锡连接到电路基板3上。此外,也可使用银膏等所谓的导电性粘接剂或ACF进行连接。
电路基板3例如通过下述方法来形成:在玻璃环氧基体材料的表面背面覆盖铜箔,利用刻蚀形成布线图形,再通过通孔9实现表面背面的导通。在布线图形的表面上进行Ni-Au电镀,这对于防止发生迁移(migration)等的不良情况的效果很好。
在电路基板3的表面上设定安装液晶驱动用IC6用的区域、即IC安装区A。此外,形成多条输出布线11和多个输入端子12作为布线图形,如图2中所示,这些布线和端子的前端在IC安装区A的内部区域中形成接合区13。在输出布线的背面一侧、即在与液晶驱动用IC6相反的一侧的面上,如图4中所示,与各输出布线11对应地形成输出端子14,这些输出端子14与各输出布线11利用通孔9进行导电性连接。
在图1中,液晶驱动用IC6在其底面、即有源面上具有多个凸点16,这些凸点16通过ACF4与电路基板3上的多条输出布线11分别进行导电性连接。ACF4可通过使对粒径为5μm的聚苯乙烯粒子进行Ni-Au电镀而形成的导电粒子分散在以环氧系列粘接剂为主要成分的粘接剂中而形成。在使用该ACF4的情况下,可在温度180℃、压力10gf/凸点、加压时间30秒的条件下进行热压接。
在输入用电缆8的前端的下表面上形成布线图形17,这些布线图形17通过ACF7与电路基板3的输入端子12进行导电性连接。ACF7使用由粒径约为3~10μm的镍金属粒子形成的导电粒子和以环氧系列粘接剂为主要成分的粘接剂构成的材料,在温度170℃、压力3MPa、加压时间20秒的条件下进行连接。
此外,可利用以往进行的焊锡焊接,用手工操作或机械将电路基板3与输入用电缆8连接起来。再者,最好在电路基板3与输入用电缆8的连接部处覆盖硅酮树脂、丙烯酸树脂或尿烷树脂等模塑材料,以便防湿、防尘和防止因机械接触而引起的损伤。关于电路基板3与下述的液晶屏的连接部、液晶驱动用IC6与电路基板3的连接部、电子部件2与电路基板3的连接部,也可同样使用这样的模塑材料。
在与本实施例有关的半导体芯片的安装结构体1中,如图2中所示,在IC安装区A的内部、特别是被多条输出布线11的接合区13和多个输入端子12的接合区13包围的区域B中分散地配置多个贯通孔10。
现在,如果将贯通孔10的合计面积对液晶驱动用IC6的朝向基板3的安装面的面积的占有率设为R,则根据模拟结果、随时间推移的连接不良的测定以及液晶驱动用IC6与电路基板3的连接强度的实验,将R设定在下述范围内是较为理想的:
    0%<R≤18%
按照这一点,如果占有率R是0%,则会留下残留应力,发生显著的随时间推移的连接不良,此外,如果占有率R大于18%,则不能确保足够的连接强度。将R设定在下述范围内则更为理想:
    2%≤R≤10%
通过这样来设定,则由于既能确保液晶驱动用IC6与电路基板3的连接强度,又能使多余的ACF4通过贯通孔10逸出,故可降低残留应力。此外,通过将贯通孔10的设定位置定为被接合区包围的区域B的与中央部相比尽可能靠近凸点的位置,可在各凸点与对应的接合区的连接部中使多余的ACF迅速地逸出。
在与本实施例有关的半导体芯片的安装结构体中,由于在电路基板3的IC安装区A的内部、特别是在被接合区包围的区域B(参照图2)的内部以分散状态形成多个贯通孔10,故在将液晶驱动用IC6压接到电路基板3时,在利用压接头挤压ACF4时,多余的ACF4进入这些贯通孔10中,从液晶驱动用IC6逸出。因而,由于在IC6和基板3之间始终存在适量的ACF4,于是在ACF4的压接连接时,在该ACF4的内部不会产生大的残留应力,因此,也不会产生随时间推移的连接不良,其结果,可提高IC6的凸点16与基板3上的接合区之间的连接可靠性。
(变形例)
关于上述的安装结构体,可考虑以下的变形例。首先,在上述实施例中,作为单纯的贯通孔10形成了使ACF4等粘接剂逸出用的的贯通孔,但在安装液晶驱动用IC6的电路基板3是在表面背面两面上具有布线层的两面电路基板、而且将导通这些布线层的导电性通孔设置在IC安装区A的内部区域中时,可将这样的导电性通孔兼作使粘接剂逸出用的贯通孔之用。
此外,作为电路基板3的基体材料,可使用由①芳族聚酰胺纤维或②玻璃纤维和芳族聚酰胺纤维的混合材料构成的第1材料以及由③聚酰亚胺系列树脂或④BT(bismaleid triazine双马来酰亚胺三嗪)树脂等构成的第2材料的复合材料,来代替玻璃纤维与环氧系列树脂的复合材料、即玻璃环氧基体材料。
此外,也可使用环氧系列树脂、聚酰亚胺系列树脂、BT树脂等的单独材料,或由这些材料的混合或化合材料构成的基板材料来形成电路基板。
此外,关于电路基板3,可使用单面布线基板,也可使用3层、4层等多层基板,来代替上述实施例那样的两面布线基板。在使用单面布线基板的情况下,虽然在与液晶驱动用IC6的安装面相同的面上形成输出端子,但可使基板的成本降低。此外,在使用多层基板的情况下,可比较容易地实现设置接地层或使电源布线图形变粗等降低噪声的对策。
(液晶装置的实施例)
图3示出了使用图1中示出的安装结构体1的液晶装置。在这里示出的液晶装置20由该安装结构体1和与其连接的液晶屏19构成。
如图4中所示,液晶屏19通过用密封材料27粘贴一对透光性基板21a和21b并在这些基板之间封入液晶22来形成。在一个透光性基板21a的内侧表面上形成透光性电极23a,在另一个透光性基板21b的内侧表面上形成透光性电极23b。
透光性基板21a伸出到对置的透光性基板21b的外侧,在该伸出部上形成屏一侧的端子24。在该屏一侧的端子24中包含从透光性电极23a直接延伸出来的部分和通过配置在两基板21a和21b间的导通材料(图中未示出)与透光性电极23b连接的部分这样的2种类型。在各透光性基板21a和21b的外侧表面上粘贴偏振片26、26。
在对半导体芯片的安装结构体1进行定位以使电路基板3的输出端子14与屏一侧的端子24在位置上一致的状态下,利用配置在它们间的ACF28进行导电性连接。在本实施例中,作为ACF28,使用由对粒径为10μm的聚苯乙烯粒子进行Ni-Au电镀而形成的导电粒子和以环氧系列粘接剂为主要成分的粘接剂构成的ACF,在温度170℃、压力3MPa、加压时间20秒的压接条件下进行连接。
再有,可只使用不含有导电粒子的粘接剂使电路基板3的输出端子14与屏一侧的端子24直接接触而导通,来代替使用ACF28的连接方法。如果按照该连接方法,则可消除因使用ACF时产生的导电粒子引起的短路不良情况的担心,可实现更微细的间距的连接。
关于如上所述那样构成的液晶装置20,也如图4中所示那样,在半导体芯片的安装结构体1中,由于在电路基板3的IC安装区A的内部、特别是在被输出布线11和输入端子12的接合区13包围的区域B的内部以分散状态形成了多个贯通孔10,故在压接液晶驱动用IC6时,多余的ACF4进入这些贯通孔10中,于是,可防止在ACF4的压接连接时在该ACF4的内部产生大的残留应力。
(电子装置的实施例)
图5示出了与本发明有关的电子装置的一例、即携带电话机的一实施例。在这里示出的携带电话机30通过在外壳36中安置天线31、扬声器32、液晶装置20、键开关33、话筒34等各种构成要素而构成。液晶装置20由图3中示出的液晶装置构成。
图6示出了图5中示出的携带电话机的内部结构的主要部分,将由液晶屏19和安装结构体1构成的液晶装置20安装在携带电话机30的本体基板37内。例如,使用粘接剂将液晶屏19固定到以硅橡胶或发泡尿烷为基体材料的具有减震性的固定部件38上,或利用以无纺布为基体材料的两面胶带将液晶屏19固定到本体基板37的预定位置上。
在本体基板37上形成将电源和输入信号供给液晶装置20用的端子41,而且设有与该端子连接的凹形的连接器42。液晶装置20通过以可插拔的方式将输入用电缆8插入连接器42中,与本体基板37的电源一侧进行连接。
在这里例示的携带电话机中,也通过使用图1中示出的安装结构体1,在使用ACF4将液晶驱动用IC6安装到电路基板3上时,由于能使多余的ACF4逸出到贯通孔10中,故可提高IC6的连接可靠性。
(其它的实施例)
以上举出了优选的实施例说明了本发明,但本发明不限定于这些实施例,在权利要求中记载的发明的范围内可进行各种改变。
例如,本发明中使用的半导体芯片不限于液晶驱动用IC,可以是用于各种目的的各种IC。此外,安装半导体芯片的基板也不限于图1中示出的两面布线结构的基板,也可以是单层的基板或多层的基板。
此外,在图1中将凸点16和贯通孔10作为直线状的列来排列,但排列形态不限于特别的形态。例如,也可将凸点16和贯通孔10排列成锯齿状。
按照与本发明有关的半导体芯片的安装结构体、液晶装置和电子装置,由于在基板中设置了贯通孔,故在其间夹住多量的粘接剂的状态下将半导体芯片压接到基板上时,可使多余的粘接剂逸出到贯通孔中,因此,在使用粘接剂的压接连接时,可防止在该粘接剂的内部产生大的残留应力,因此,可防止随时间推移产生的连接不良。
此外,特别是按照本发明,由于将多个贯通孔配置在被多个接合区包围的区域内,而且这些贯通孔不集中在1个部位、而是以分散状态来配置,故能使多余的粘接剂均匀地且可靠地逸出,于是在半导体芯片的整个面中可大体上完全防止在粘接剂的内部产生残留应力。

Claims (11)

1.一种半导体芯片的安装结构体,该半导体芯片的安装结构体包括具备多个凸点(bump)的半导体芯片和具备多个接合区(land)的基板、同时通过使用粘接剂来连接上述半导体芯片与上述基板以使这些凸点与这些接合区互相导通而构成,该安装结构体的特征在于:
在上述基板中,在被上述多个接合区包围的区域内分散地配置多个贯通孔。
2.如权利要求1中所述的半导体芯片的安装结构体,其特征在于:
上述贯通孔的合计面积对上述半导体芯片的面积的占有率R是:
        0%<R≤18%。
3.如权利要求1中所述的半导体芯片的安装结构体,其特征在于:
上述贯通孔的合计面积对上述半导体芯片的面积的占有率R是:
        2%≤R≤10%。
4.如权利要求1至权利要求3中的至少任一项中所述的半导体芯片的安装结构体,其特征在于:
将上述贯通孔设置在被上述多个接合区包围的区域的与中央部相比靠近上述接合区的位置上。
5.如权利要求1至权利要求4中的至少任一项中所述的半导体芯片的安装结构体,其特征在于:
上述基板具有导通表面背面两面的布线层的多个通孔,
上述多个贯通孔由这些通孔构成。
6.一种液晶装置,该液晶装置具有被一对透光性基板夹住的液晶,通过控制施加到该液晶上的电压来控制该液晶的取向,因而对入射到该液晶上的光进行调制,该液晶装置的特征在于:
该液晶装置具有与上述透光性基板的至少一方粘接的半导体芯片的安装结构体,
该半导体芯片的安装结构体包括具备多个凸点的液晶驱动用IC和具备多个接合区的基板,同时通过使用粘接剂来连接上述液晶驱动用IC与上述基板以使这些凸点与这些接合区互相导通而构成,
在上述基板中,在被上述多个接合区包围的区域内分散地配置多个贯通孔。
7.如权利要求6中所述的液晶装置,其特征在于:
上述贯通孔的合计面积对上述液晶驱动用IC的面积的占有率R是:
       0%<R≤18%。
8.如权利要求6中所述的液晶装置,其特征在于:
上述贯通孔的合计面积对上述液晶驱动用IC的面积的占有率R是:
       2%≤R≤10%。
9.如权利要求6至权利要求8中的至少任一项中所述的液晶装置,其特征在于:
将上述贯通孔设置在被上述多个接合区包围的区域的与中央部相比靠近上述接合区的位置上。
10.如权利要求6至权利要求9中的至少任一项中所述的液晶装置,其特征在于:
上述基板具有导通表面背面两面的布线层的多个通孔,
上述多个贯通孔由这些通孔构成。
11.一种包含液晶装置而构成的电子装置,其特征在于:
该液晶装置由权利要求6至权利要求10中的至少任一项中所述的液晶装置构成。
CNB991040856A 1998-03-24 1999-03-23 半导体芯片的安装结构体、液晶装置和电子装置 Expired - Fee Related CN100370603C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP7633498 1998-03-24
JP76334/98 1998-03-24
JP287099/98 1998-10-08
JP28709998A JP3610787B2 (ja) 1998-03-24 1998-10-08 半導体チップの実装構造体、液晶装置及び電子機器

Publications (2)

Publication Number Publication Date
CN1235375A true CN1235375A (zh) 1999-11-17
CN100370603C CN100370603C (zh) 2008-02-20

Family

ID=26417471

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB991040856A Expired - Fee Related CN100370603C (zh) 1998-03-24 1999-03-23 半导体芯片的安装结构体、液晶装置和电子装置

Country Status (5)

Country Link
US (1) US6265770B1 (zh)
JP (1) JP3610787B2 (zh)
KR (1) KR100545881B1 (zh)
CN (1) CN100370603C (zh)
TW (1) TW417263B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139060B2 (en) 2004-01-27 2006-11-21 Au Optronics Corporation Method for mounting a driver IC chip and a FPC board/TCP/COF device using a single anisotropic conductive film
US7164460B2 (en) 2000-02-24 2007-01-16 Seiko Epson Corporation Mounting structure for semiconductor device, electro-optical device, and electronic apparatus
CN100390941C (zh) * 2005-01-12 2008-05-28 精工爱普生株式会社 半导体装置及其制法、电路基板、电光学装置和电子仪器
CN100437236C (zh) * 2005-10-28 2008-11-26 友达光电股份有限公司 液晶显示面板与其上的线路布局
CN101197355B (zh) * 2006-12-04 2010-06-23 索尼株式会社 电子器件及其制造方法、发光二极管显示单元及其制造方法
CN106155405A (zh) * 2015-04-28 2016-11-23 深圳欧菲光科技股份有限公司 柔性电路板及应用该柔性电路板的电子设备

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3767474B2 (ja) * 2001-01-15 2006-04-19 セイコーエプソン株式会社 表示装置及びその製造方法
US6891276B1 (en) 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
US6936495B1 (en) 2002-01-09 2005-08-30 Bridge Semiconductor Corporation Method of making an optoelectronic semiconductor package device
US7190060B1 (en) 2002-01-09 2007-03-13 Bridge Semiconductor Corporation Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same
US6987034B1 (en) 2002-01-09 2006-01-17 Bridge Semiconductor Corporation Method of making a semiconductor package device that includes singulating and trimming a lead
JP3832823B2 (ja) * 2002-07-09 2006-10-11 株式会社 日立ディスプレイズ 表示装置
JP4428329B2 (ja) * 2005-05-30 2010-03-10 エプソンイメージングデバイス株式会社 電気光学装置及びその製造方法並びに電子機器
WO2008003545A1 (de) * 2006-07-04 2008-01-10 Continental Automotive Gmbh Flexibler leiterträger und verwendung eines glasfasergewebes und eines harzes für den flexiblen leiterträger
CN101574022B (zh) * 2007-02-22 2011-04-20 夏普株式会社 电子电路装置及其制造方法以及显示装置
CN105518885B (zh) 2013-12-02 2018-02-16 东芝北斗电子株式会社 发光装置
JP2017094580A (ja) * 2015-11-24 2017-06-01 セイコーエプソン株式会社 配線構造、memsデバイス、液体噴射ヘッド、液体噴射装置、memsデバイスの製造方法、液体噴射ヘッドの製造方法、および、液体噴射装置の製造方法
KR102354514B1 (ko) * 2017-05-11 2022-01-21 엘지디스플레이 주식회사 표시 장치
KR102555446B1 (ko) * 2018-04-26 2023-07-13 삼성디스플레이 주식회사 표시 장치

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5511361A (en) * 1978-07-11 1980-01-26 Citizen Watch Co Ltd Semiconductor fitting construction
JPS6350049A (ja) * 1986-08-19 1988-03-02 Mitsubishi Electric Corp 樹脂封止型半導体装置
JPS6364330A (ja) * 1986-09-04 1988-03-22 Mitsubishi Electric Corp 半導体装置
JP2544371B2 (ja) * 1987-02-25 1996-10-16 株式会社日立製作所 半導体装置
JP2531963B2 (ja) * 1987-12-03 1996-09-04 新光電気工業株式会社 半導体装置
JPH02177553A (ja) * 1988-12-28 1990-07-10 Matsushita Electric Ind Co Ltd 集積回路装置およびその製造方法
JPH0487643U (zh) * 1990-11-30 1992-07-30
JP3088877B2 (ja) * 1992-06-25 2000-09-18 日東電工株式会社 フィルムキャリアの製造方法および半導体装置
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
JP2962385B2 (ja) * 1993-01-07 1999-10-12 松下電子工業株式会社 半導体装置の製造方法
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
FR2723257B1 (fr) * 1994-07-26 1997-01-24 Sgs Thomson Microelectronics Boitier bga de circuit integre
JP2546192B2 (ja) * 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
JPH08293524A (ja) * 1995-04-21 1996-11-05 Toshiba Corp 半導体装置およびその製造方法
JP2825083B2 (ja) * 1996-08-20 1998-11-18 日本電気株式会社 半導体素子の実装構造
JP3394875B2 (ja) * 1996-11-29 2003-04-07 日立化成工業株式会社 半導体装置用チップ支持基板
US6064114A (en) * 1997-12-01 2000-05-16 Motorola, Inc. Semiconductor device having a sub-chip-scale package structure and method for forming same
US5893726A (en) * 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7164460B2 (en) 2000-02-24 2007-01-16 Seiko Epson Corporation Mounting structure for semiconductor device, electro-optical device, and electronic apparatus
US7139060B2 (en) 2004-01-27 2006-11-21 Au Optronics Corporation Method for mounting a driver IC chip and a FPC board/TCP/COF device using a single anisotropic conductive film
US7375787B2 (en) 2004-01-27 2008-05-20 Au Optronics Corporation Liquid crystal display devices
CN100390941C (zh) * 2005-01-12 2008-05-28 精工爱普生株式会社 半导体装置及其制法、电路基板、电光学装置和电子仪器
CN100437236C (zh) * 2005-10-28 2008-11-26 友达光电股份有限公司 液晶显示面板与其上的线路布局
CN101197355B (zh) * 2006-12-04 2010-06-23 索尼株式会社 电子器件及其制造方法、发光二极管显示单元及其制造方法
CN106155405A (zh) * 2015-04-28 2016-11-23 深圳欧菲光科技股份有限公司 柔性电路板及应用该柔性电路板的电子设备
CN106155405B (zh) * 2015-04-28 2024-04-26 安徽精卓光显技术有限责任公司 柔性电路板及应用该柔性电路板的电子设备

Also Published As

Publication number Publication date
JPH11340285A (ja) 1999-12-10
TW417263B (en) 2001-01-01
JP3610787B2 (ja) 2005-01-19
KR100545881B1 (ko) 2006-01-25
KR19990078144A (ko) 1999-10-25
CN100370603C (zh) 2008-02-20
US6265770B1 (en) 2001-07-24

Similar Documents

Publication Publication Date Title
CN1235375A (zh) 半导体芯片的安装结构体、液晶装置和电子装置
CN1199534C (zh) 电路基板及使用它的显示装置、以及电子设备
CN1134702C (zh) 液晶显示装置、其安装结构及电子设备
CN1242373C (zh) 矩阵型显示装置
CN1303646C (zh) 增强板粘着装置
CN1229863C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1235286C (zh) 一种电子装置与制作此装置的方法
CN1138629C (zh) 多层基板
CN1199533C (zh) 电路基板及其制造方法、以及使用电路基板的显示装置及电子设备
EP1734800A2 (en) Technique for manufacturing an overmolded electronic assembly
US20070127224A1 (en) Electronic circuit device and method of manufacturing the same
CN1135610C (zh) 各向异性导电膜和半导体芯片的安装方法以及半导体装置
CN1185698C (zh) 半导体装置及其制造方法、电路板以及电子设备
CN1340851A (zh) 电子器件及其制造方法
CN1790706A (zh) 多层构成半导体微型组件
CN1737656A (zh) 包括导电可压缩体的平板显示设备
CN1598649A (zh) 电光装置、挠性布线基板、电光装置制造方法及电子设备
CN1815733A (zh) 半导体装置及其制造方法
CN1338880A (zh) 电光装置及电子设备
CN1638120A (zh) 半导体组装体及其制造方法
CN1976557A (zh) 电路基板装置及基板间的连接方法
CN1678175A (zh) 电路部件模块及其制造方法
CN1734757A (zh) 电子回路装置
CN1601713A (zh) 半导体装置的制造方法
CN1783116A (zh) Rfid标签及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NANKAI UNIVERSITY

Free format text: FORMER OWNER: SEIKO EPSON CORP.

Effective date: 20100826

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20100826

Address after: Tokyo, Japan

Patentee after: Sony Corp.

Address before: Tokyo, Japan

Patentee before: Seiko Epson Corp.

ASS Succession or assignment of patent right

Owner name: NIPPON DISPLAY CO., LTD.

Free format text: FORMER OWNER: SONY CORPORATION

Effective date: 20121119

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20121119

Address after: Aichi

Patentee after: Japan display West Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: Sony Corp.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080220

Termination date: 20180323

CF01 Termination of patent right due to non-payment of annual fee