JPS5511361A - Semiconductor fitting construction - Google Patents

Semiconductor fitting construction

Info

Publication number
JPS5511361A
JPS5511361A JP8431778A JP8431778A JPS5511361A JP S5511361 A JPS5511361 A JP S5511361A JP 8431778 A JP8431778 A JP 8431778A JP 8431778 A JP8431778 A JP 8431778A JP S5511361 A JPS5511361 A JP S5511361A
Authority
JP
Japan
Prior art keywords
substrate
pattern
moulding
mould surface
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8431778A
Other languages
Japanese (ja)
Inventor
Kazuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP8431778A priority Critical patent/JPS5511361A/en
Publication of JPS5511361A publication Critical patent/JPS5511361A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: For obtaining large adhesive force even though the resin mould surface of the circuit substrate having a conductive pattern for mounting a semiconductor element is small, to supply a resin mould member also to the recess or through hole provoded on said resin mould surface.
CONSTITUTION: A circuit pattern 12 is provided glass epoxy on the circuit substrate 11 by etching and plating, and a semiconductor element 13 is sticked on the die-bond portion 12a of said pattern 12 with conductive adhesive. Next, the electrode of said element 13 is connected to the lead wire portion 12b provided on said pattern 12 by means of the thin wire of gold for example. Thereafter, a thermoplastic frame 15 is placed to cover said substrate 11 including said element 13, and moulding is made by supplying the moulding member 16 of epoxy resin for example to said frame 15 while avoiding the outflow thereof. At the same time, a through hole 11a with a diameter of about 0.3mm is provided in the mould surface of said substrate 11, and said moulding member 16 is supplied thereto also. Thereby, the adhesive force between said substrate 11 and member 16 can be increased considerably.
COPYRIGHT: (C)1980,JPO&Japio
JP8431778A 1978-07-11 1978-07-11 Semiconductor fitting construction Pending JPS5511361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8431778A JPS5511361A (en) 1978-07-11 1978-07-11 Semiconductor fitting construction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8431778A JPS5511361A (en) 1978-07-11 1978-07-11 Semiconductor fitting construction

Publications (1)

Publication Number Publication Date
JPS5511361A true JPS5511361A (en) 1980-01-26

Family

ID=13827125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8431778A Pending JPS5511361A (en) 1978-07-11 1978-07-11 Semiconductor fitting construction

Country Status (1)

Country Link
JP (1) JPS5511361A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63105346U (en) * 1986-12-24 1988-07-08
US5336931A (en) * 1993-09-03 1994-08-09 Motorola, Inc. Anchoring method for flow formed integrated circuit covers
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6265770B1 (en) * 1998-03-24 2001-07-24 Seiko Epson Corporation Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment
US6558981B2 (en) * 1998-09-16 2003-05-06 International Business Machines Corporation Method for making an encapsulated semiconductor chip module
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
USRE43404E1 (en) 1996-03-07 2012-05-22 Tessera, Inc. Methods for providing void-free layer for semiconductor assemblies
US10583808B2 (en) 2015-06-09 2020-03-10 Mitsuba Corporation Wiper device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63105346U (en) * 1986-12-24 1988-07-08
US5336931A (en) * 1993-09-03 1994-08-09 Motorola, Inc. Anchoring method for flow formed integrated circuit covers
USRE43404E1 (en) 1996-03-07 2012-05-22 Tessera, Inc. Methods for providing void-free layer for semiconductor assemblies
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US6265770B1 (en) * 1998-03-24 2001-07-24 Seiko Epson Corporation Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment
US6558981B2 (en) * 1998-09-16 2003-05-06 International Business Machines Corporation Method for making an encapsulated semiconductor chip module
US10583808B2 (en) 2015-06-09 2020-03-10 Mitsuba Corporation Wiper device

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