JPS53139468A - Mounting structure of resin mold semiconductor device - Google Patents

Mounting structure of resin mold semiconductor device

Info

Publication number
JPS53139468A
JPS53139468A JP5407077A JP5407077A JPS53139468A JP S53139468 A JPS53139468 A JP S53139468A JP 5407077 A JP5407077 A JP 5407077A JP 5407077 A JP5407077 A JP 5407077A JP S53139468 A JPS53139468 A JP S53139468A
Authority
JP
Japan
Prior art keywords
semiconductor device
mounting structure
resin mold
mold semiconductor
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5407077A
Other languages
Japanese (ja)
Inventor
Kazuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP5407077A priority Critical patent/JPS53139468A/en
Priority to US05/808,216 priority patent/US4143456A/en
Priority to GB26291/77A priority patent/GB1581587A/en
Publication of JPS53139468A publication Critical patent/JPS53139468A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To secure a good coating over the semiconductor chip surface with the resin as well as to obtain the shaping effect by reducing the resin flow and to reduce the cost, by providing a pierced hole to the circuit substrate and then injecting the mold resin through the rear surface of the substrate.
COPYRIGHT: (C)1978,JPO&Japio
JP5407077A 1976-06-28 1977-05-11 Mounting structure of resin mold semiconductor device Pending JPS53139468A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP5407077A JPS53139468A (en) 1977-05-11 1977-05-11 Mounting structure of resin mold semiconductor device
US05/808,216 US4143456A (en) 1976-06-28 1977-06-20 Semiconductor device insulation method
GB26291/77A GB1581587A (en) 1976-06-28 1977-06-23 Semi-conductor assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5407077A JPS53139468A (en) 1977-05-11 1977-05-11 Mounting structure of resin mold semiconductor device

Publications (1)

Publication Number Publication Date
JPS53139468A true JPS53139468A (en) 1978-12-05

Family

ID=12960350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5407077A Pending JPS53139468A (en) 1976-06-28 1977-05-11 Mounting structure of resin mold semiconductor device

Country Status (1)

Country Link
JP (1) JPS53139468A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4913930A (en) * 1988-06-28 1990-04-03 Wacker Silicones Corporation Method for coating semiconductor components on a dielectric film
US5304513A (en) * 1987-07-16 1994-04-19 Gao Gesellschaft Fur Automation Und Organisation Mbh Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
USRE43404E1 (en) 1996-03-07 2012-05-22 Tessera, Inc. Methods for providing void-free layer for semiconductor assemblies

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304513A (en) * 1987-07-16 1994-04-19 Gao Gesellschaft Fur Automation Und Organisation Mbh Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame
US4913930A (en) * 1988-06-28 1990-04-03 Wacker Silicones Corporation Method for coating semiconductor components on a dielectric film
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
USRE43404E1 (en) 1996-03-07 2012-05-22 Tessera, Inc. Methods for providing void-free layer for semiconductor assemblies

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