JPS6428830A - Substrate for mounting semiconductor - Google Patents
Substrate for mounting semiconductorInfo
- Publication number
- JPS6428830A JPS6428830A JP62184341A JP18434187A JPS6428830A JP S6428830 A JPS6428830 A JP S6428830A JP 62184341 A JP62184341 A JP 62184341A JP 18434187 A JP18434187 A JP 18434187A JP S6428830 A JPS6428830 A JP S6428830A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- recessed part
- mounting
- parts
- mounting semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE:To prevent an electrical disconnection and an electrical short-circuit by a method wherein gaps for performing a bonding are secured between a part, which is located on the surface of a substrate and is adjacent to a recessed part for mounting semiconductor element, and bonding wires. CONSTITUTION:In a substrate 1 for semiconductor mounting, a recessed part 2 for semiconductor element mounting and conductor circuits 3 are formed on the upper surface of the substrate consisting of a resin material. By performing a chamfering processing on parts, which are located on the surface of the substrate 1 and are in the vicinity of the recessed part 2, chamfering parts 10 are formed. The parts, which are located on the surface of the substrate 1 and are adjacent to the recessed part 2, are positioned lower that the surface of the substrate 1. Thereby, the contact of the vicinity of the recessed part 2 with bonding wires is prevented. Thereby, an electrical disconnection and an electrical short-circuit are prevented.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62184341A JPS6428830A (en) | 1987-07-23 | 1987-07-23 | Substrate for mounting semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62184341A JPS6428830A (en) | 1987-07-23 | 1987-07-23 | Substrate for mounting semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6428830A true JPS6428830A (en) | 1989-01-31 |
Family
ID=16151598
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62184341A Pending JPS6428830A (en) | 1987-07-23 | 1987-07-23 | Substrate for mounting semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6428830A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03184384A (en) * | 1989-12-13 | 1991-08-12 | Nec Corp | Optical module submount and manufacture thereof |
JP2012009865A (en) * | 2010-06-23 | 2012-01-12 | Lg Innotek Co Ltd | Ceramic substrate and method of manufacturing the same, and image sensor package and method of manufacturing the same |
JP2015099948A (en) * | 2015-03-02 | 2015-05-28 | ローム株式会社 | Light emitting device, manufacturing method of light emitting device, and optical device |
-
1987
- 1987-07-23 JP JP62184341A patent/JPS6428830A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03184384A (en) * | 1989-12-13 | 1991-08-12 | Nec Corp | Optical module submount and manufacture thereof |
JP2012009865A (en) * | 2010-06-23 | 2012-01-12 | Lg Innotek Co Ltd | Ceramic substrate and method of manufacturing the same, and image sensor package and method of manufacturing the same |
JP2015099948A (en) * | 2015-03-02 | 2015-05-28 | ローム株式会社 | Light emitting device, manufacturing method of light emitting device, and optical device |
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